challenges and opportunity in 3d integration packaging...interposer technology, challenges of...

SEMICON® Korea 2010 SEMI® Technology Symposium (STS)

Challenges and Opportunity in 3D Integration Packaging

Seung Wook YOON, Jae Hoon KU and Flynn CARSON* STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

* STATS ChipPAC Inc.47400 Kato Road Fremont, CA 94538 USA [email protected]

Abstract Demand for 3D integration is being driven by the need for

3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies.

3D packaging using the z-axis TSV stacking concept has been investigated by a number of semiconductor manufacturers and research institutes, and is believed to be one of the most promising technologies. There is a growing interest in the development and application of this new chip stacking approach to existing and future devices. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes. Applications have to be well understood and integrated in order to successfully be applied.

This paper addresses 3D integration technology, TSV interposer technology, challenges of assembly and packaging, .3D eWLB with TSV technology and future applications of 3D TSV integration.

I.INTRODUCTION The packaging and assembly industry imitated the

laminated multilayer circuit board by stacking packages. Package-on-package (PoP) and flex-based origami packages result substantially higher densities without significant infrastructure disruption. Wire bonded die stacks further increase packaging density. However, wire bonds increase interconnect parasitics and are incompatible with area array designs.

Many see through-silicon-vias (TSV) as the definitive step toward true 3D device integration. Short, vertical, low impedance, area array interconnects enable inter-wafer communication with no footprint penalty. While new test, thermal, and design issues emerge, the promise of 3D integration tempts even the most skeptical.

One of the hottest topics in the semiconductor industry today is 3D Packaging using Through Silicon Via (TSV) technology. Driven by the need for improved performance and the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. The industry is moving past the feasibility (R&D) phase for TSV technology into the commercialization phase, where economic realities will determine the technologies that can be adopted. Low-cost, high aspect ratio, reliable via formation and via filling

technologies are the need of the hour. Choosing the right process equipment and materials with innovative design solutions addressing thermal and electrical issues will be the key winner. As functional integration requirements increase, assembly and wafer fabrication companies are looking to 3D TSV technology, which allows stacking of LSIs thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to conventional packaging.

3D integration is progressing on three fronts starting with package-level (die, package stacking), wafer level (die-to-wafer bonding, fan out WLP) and more recently at the Si level (TSV) as shown in Fig.1.

Figure 1. 3D Integration- The solution space – 3D @ package level, wafer level & Si level

The demand for high density and multifunctional microelectronics leads to the development of 3D and wafer level packaging, which provides an optimal solution for the shortened interconnects, increased performance and functionality, miniaturization in size and weight, integration of hetero-generous technologies and complex multi-chip systems as well as reduced power consumption. Such packaging technology normally requires the use of ultrathin devices (less than 100µm in thickness). The key benefits from thinned wafers include improved heat dissipation and reduced electrical resistance which offers better flexibility for 3D stacking. However, it brings up a challenge for assembly and packaging; thinning and handling ultrathin semiconductor devices in both front-end and back-end processes due to its fragility and tendency to warp. [1]


Figure 2. 3D integration packaging with microbump and TSV

II. 3D TSV INTERPOSER TECHNOLOGY

3D interposers, whether silicon or glass-based, are a next-

gen substrate technology that is perceived as a ‘bridge’ platform between today’s 2D and the “true 3D” that is expected to debut in the 2012-2013 timeframe. Features such as the integration of mature logic and analog functions like IPDs will be key to the commercialization of 3D interposers in the short term. Silicon interposers with TSVs are being touted as a short-term bridge to full 3-D ICs. It is important to have a stepping-stone or bridge technology for 3D TSV.

Figure 3. PoP with TSV interposer with micro-bumped flipchips and embedded passives.

3D interposers are one of candidates that would be useful

for ELK devices and high performance applications. TSV interposers also have the potential to replace advanced substrates due to advantages in thermal performance, precise dimension control, fine line width/spacing, embedded passives as well as overall thickness. There should be cost/performance

crossover between Si interposer and advanced substrates in the near future.

Gaining in popularity for many reasons, 3D interposers are not just considered a temporary measure or stepping-stone anymore. The consensus is that interposers may act as a bridge to full 3D IC integration in some applications, but they will remain a viable enabling technology for new applications requiring high-density 3D package integration architectures.

TSV 3D interposer approach is an efficient and practical approach to solving die integration challenges. Many microsystem device applications that will have to move to wafer-level packaged silicon form factor devices, thereby also facilitating further integration using silicon TSV interposers. But business view point, it’s important to have a business justification for 3D interposers, not just a technology push behind it.

III. 3D TSV ASSEMBLY AND PACKAGING A. Microbump process and reliability In advanced 3D stacking technologies, one of the important steps is to develop and assembly fine pitch and high density solder microbumps. Solder microbumps for flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and enable high-performance signal and power connections. [2]

To evaluate the interconnection with microbump, test vehicles were fabricated on 8-inch size wafer. A test chip of 5 X 5 mm2 size was designed with >10000 I/O off-chip interconnects at 40 / 50 μm pitch in fully populated rows using Re-distribution layer (RDL) to evaluate the chip-to-wafer (CTW) bonding interconnections. Test vehicles fabrication is based on photolithography and electroplating processes, which is compatible with conventional IC fabrication as shown in Fig.4.

Figure 4. SEM micrograph of 40/ 50μm pitch

Flip chip package assembly was carried out to investigate

the bonding quality and interconnections with microbump flip chip as shown in Fig. 5.. After flip chip die fabrication with bump, the die attachment was carried out with thermo-compression flip chip bonders. Several DOE (degree of experimental)s were carried out to find optimized process

Micro-bump TV-1

TV-2


conditions as functions of time, stage temperature, pickup tool temperature as well as pressure.

40μm and 50μm both microbump test vehicles were sent to JEDEC standard reliability tests. Reliability samples passed MSL-3 with 3x reflow process at Pb-free 260oC peak temperature. All samples passed unbiased HAST and HTS reliability tests. There was no failure found after 500 T/C and 1000 T/C. B. TSV assembly Thin wafer handling system There are many ways to overcome current issues to get better process compatibility and repeatability of handling TSV thin wafers for packaging process. Because the TSV wafer is thinned down to 50um thickness, handling of this wafer for packaging process is another challenge in order to meet the different and varying needs, such as temperature and chemical stability, temporary adhesion strength et al. For example, polymer bonding/debonding process is based on high temperature, so it may not suitable for solder bumped wafer. And 12” wafer applications have more challenges than 8” applications and need to optimize the process as well as materials for larger area bonding/debonding.

(a)

(b)

Figure 5. (a) Micrograph of Chip-to-Wafer bonding and (b)SEM micrograph of 50um pitch with underfill in small gap

Thin Die Warpage Package warpage is also a challenge in the assembly process and reliability so the test vehicle as shown in Fig. 6 was fabricated with 50μm thin die and 150μm pitch Pb-free solder bump. The warpage was measured with a reflow temperature profile with THERMOIRE as shown in Fig. 7. It showed after reflow process, the thin flip chip die warpage difference was 60 um at room temperature between before-reflow and after-reflow. This serious warpage causes higher stress in TSV structures thus catastrophic failure will happen

at the package level. Therefore, it should be studied more and characterized with further experiments.

(a)

(b)

Figure 6. Package warpage test vehicle of (a) schematics and (b) optical micrograph of cross-section.

Table 1. Warpage behavior of thinned flipchip packaging

with reflow profile.

Figure 7. Plot of warpage behavior with temperature profile for thinned flipchip packaging after underfill process.

IV. 3D eWLB WITH TSV TECHNOLOGY

Demand for through silicon via (TSV) is being driven by

the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies.[6]

3D packaging using the z-axis TSV stacking concept has been investigated by a number of semiconductor manufacturers and research institutes, and is believed to be one of the most promising technologies. There is a growing interest in the development and application of this new chip stacking approach to existing and future devices. There are several steps involved in 3D chip stacking using TSV


technology. Each of these steps requires different techniques, materials and processes. Applications have to be well understood and integrated in order to successfully be applied. Still there are obstacles and barrier to overcome for mass production of TSV assembly and packaging beside TSV formation challenges, such as bonding/debonding process for temporary thin wafer handling, and microbump interconnects for assembly and packaging.

A. 3D eWLB with TSV technology

TSV is typically not a packaging solution by itself. TSV uses only back-end manufacturing techniques such as bonding, fine pitch bumping, back grinding and thin wafer handling. Final packaging is required to connect the device to the PWB. Due to assembly constraints, the choice of the final package solution could affect the entire TSV process flow. This final packaging could be a BGA package, a fan-out WLP type, an embedded die in substrate (EDS), or other. Here, it is interesting to notice how complementary 3D IC configurations with TSV and 3D packaging can be. In effect, 3D eWLB(embedded Wafer Level BGA) can enable designs to fully benefit from the 3D IC integration and can reduce the package footprint with more aggressive design rules than BGA packages.

Figure 8. Schematics of 3D eWLB packaging with TSV for 3D SiP

applications[4]. TSV is a new technology and 3D eWLB is a new

packaging technology as well. TSV is not limited to BGA types of packages. Some constraints can even be relaxed by coupling 3D IC TSV with 3D advanced packaging and then the full benefits of TSV can emerge. New opportunities should emerge and be realized in view of cost, yield, functionality, process flow as well as performance characteristics of TSV and 3D eWLB. Using a 3D eWLB approach with TSV may offer advantages such as:

• Eliminating TSV thin wafer handling issues • Integrating TSV & eWLB Technology for 3D

vertical interconnections • Integrating Memory & ASIC/ Processor and

heterogeneous functional integration in one package as well as at the wafer level

• Utilizing micro-bump and micro bonding process for interconnection

B. Further wafer level integration with 3D eWLB for heterogeneous functionality

There is a need for miniaturization at the IC, module (or sub-system), and system levels. At the IC level, scaling continues as it has over the last four decades according to Moore's Law. In addition, 3D chip stacking technology with through silicon vias (TSVs) has garnered a lot of attention recently due to its potential in improving the performance, form factor, cost, and reliability at the sub-system or module level. There is still a great deal of research and development required to bring this hetero-integration technology to cost-effective implementation with the required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system.

Although active and stacked ICs are a highly functional and important component of the overall system, they are only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely met by the current technology domain in the areas of through silicon vias (TSVs), 3D stacking, and wafer level packaging. There should be further study on integration, focusing on TSVs, 3D stacking and 3D eWLB with better electrical and thermal performance, greater system reliability, and reduced form factor and overall cost. It will go far beyond this to realize a truly seamless wafer level integrated 3D packaging module as shown in Fig. 13, that will incorporate aspects of 3D stacking, as well as Si package with embedded passive, actives in 3D eWLB packaging with TSV, flip chip, and microbump as well as 3-D WLPs.

Figure 9. Total solutions for 3-D packaging with eWLB(FO-WLP) and TSV technology. [3] V. FUTURE APPLICATIONS OF 3D TSV INTEGRATION The future looks bright for 3D TSVs and it may be here

even sooner than current expecting. Integration of simple memory chips, or IC with memory, is already happening very


successfully on a limited basis. Next generation for TSV will likely include graphic chips and processor packages with flash memory-enabling very impressive mobile applications. Biomedical devices with processors and sensors and true heterogeneous integration are also on the horizon. All of this, with the potential is to be less expensive and more reliable than current SoC or stacking methods.

There is 3D integration of memory with logic interposers first, then heterogeneous stacks (RF, analog, power, memory, MEMS with logic), stacked DRAM, and perhaps stacked NAND. For MEMS (Mechanical Electronic Micro System) applications, many applications in the wafer-level integration of MEMS and CMOS. MEMS processing has come a long way in recent years and the gap between acceptable MEMS wafer yields and CMOS wafer yields are shrinking-an absolute requirement to make wafer-level integration economically viable and there would be serious traction for TSVs in RF MEMS-related applications.

The primary products for 3D TSV today will be high performance/high speed stacked memories. The memory market is >20% of overall semiconductor market and there are more requirements for devices with higher speed, lower power consumption as well as higher capacity. For example, SSD (solid-state drive) applications require DRAM to boost read/write speed as buffer so stacked with DRAM + Flash Memory with TSV would be a potential application. Another application will be Memory + Logic with high bandwidth applications for increased electrical performance. Once TSV technology reaches a mature stage, it will be useful for 3D heterogeneous integration. However, uncertainties include transition time to embedded 3D TSV and the efficiencies of WLP vs. embedded TSV in terms of cost, performance and value-chain readiness.

VI. CONCLUSION

In this paper, 3D integration, TSV interposer technology and TSV packaging/assembly issues were discussed. For successful implementation of TSV technology to microsystem products, TSV process and TSV packaging/assembly both should be well prepared and established with close collaboration and clear understanding.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the TSV technology compares in terms of cost with existing technologies. CIS mage sensors for camera modules are already in mass production. For other applications, the adoption time is longer than originally expected, as is quite common with the introduction of new technologies. TSV technology itself is not a packaging technology apart from a few exceptions. 3D TSV and 3D packaging do not have to be considered as competitors but more as complementary areas. In recent years, the semiconductor industry has expressed some growing interest in these ideas and put some significant efforts in allowing the emergence of these new breakthrough technologies. Still, some challenges remain ahead for a wide adoption including cost, a shift in the design method paradigm, system co-design, new CAD tools, new

architectures, and more new challenges. While progress is being made, design, thermal, reliability and testing issues remain a barrier to TSV adoption in some applications.

There should be further study and understanding of TSV cost-ownership analysis, value-chain and systematic analysis of competitive advantages of TSV in business perspectives in order to move into high volume manufacturing. There is a common awareness that, although TSV could be adopted quickly in RF and memory based applications as described before, the industry is still lacking real test strategies to evaluate the reliability of these TSV interconnects. TSV engineers and researchers have been very focused on developing 3D TSV processes, but testing of these interconnects is still at its early stage. This is a very similar situation to SoC, SiP and WLP. A test strategy and methodology have to be defined in order to decide which type of measurements need to be made at which level (wafer, micro bumping, Chip-to-Wafer/Wafer-to-Wafer) bonding, packaging/assembly, final test) and which test infrastructure needs to be set up.

Major challenge of TSV 3D is probably not technical, but more that TSV is disruptive and emerging technology. Traditional CMOS scaling and predictive or planned roadmaps by shrinking transistor dimensions may not be the only one way to go. Whole semiconductor industry needs to be convinced of the additional values of 3D TSV integration approach. Things are moving, the momentum is still there, but the first products must show up in market to make 3D TSV a reality thus move further mainstream market and applications. 3D TSV must help to reduce overall semiconductor cost, improve performance or reduce form factor and reduce the time-to market.

REFERENCE

[1]. Mark Huang Shuangwu, David Li Wai Pang, Suthiwongsunthorn Nathapong and Pandi Marimuthu, “Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging,” Proceedings of 10th Electronic Packaging Technology Conference 2008, 11-14 Dec 2008, Singapore [2]. Knickerbocker, J. U. et al, “Development of next generation system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection,” IBM J. Res. Dev. Vol. 49, No. 4/5 (2005), pp. 725-754]. [3]. Newsletter on 3D Packaging, 3D IC, TSV, WLP & Embedded Technologies, MARCH 2009, No.10, Yole Development (2009). [4] Seung Wook YOON, Meenakshi PADMANATHAN, Andreas BAHR, Xavier BARATON and Flynn CARSON “3D eWLB (embedded wafer level BGA) Technology: Next Generation 3D Packaging solutions,” San Francisco, IWLPC 2009 (2009)

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