3dic & 2.5d tsv interconnect for advanced packaging 2014 report by yole developpement

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Copyrights © Yole Développement SA. All rights reserved. 1 1 3DIC & 2.5D TSV Interconnect for Advanced Packaging Advanced Packaging Team YOLE DEVELOPPEMENT COLLABORATION INNOVATION NEW PERSPECTIVES FROM TECHNOLOGIES TO MARKET 2014 Business Update Report

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3D TSV is in MEMS, CMOS Image Sensors and High-End Applications. When will it be used for mainstream consumer applications? TSV is a business…looking for wider adoption! Through Silicon Vias (TSV) technology was adopted in production a few years ago for MEMS and CMOS Image Sensors (CIS). Driven by consumer applications such as smartphones and tablets, this market is expected to continue to grow over the next several years. For high-end memories, 2015 will be the turning point for 3D adoption. Standards have now been established, therefore the industry will be ready to enter in high-volume manufacturing. Wide I/Os and logic-on-logic will follow, most probably around 2016-2017. Emerging applications, such as photonics based on interposer, are also being developed for future products. However, their market entrance is most likely not going to happen before 2019-2020. Figure1 illustrates the market adoption and growth for the next 5 years; additional information and details per application are available in the report (revenue, wspy, units 2013-2019, etc.). Many players, different applications…however, fundamentally only two TSV manufacturing options 3D technology and specifically Through Silicon Via processing offer different options for processing wafers. As a result, different business models have been developed. Today, mainly two TSV approaches are being commonly used: via last and via middle. IDMs and wafer foundries are the main adopters of via middle manufacturing for memories and logic dies. They integrate interconnections between the front and back end of the line structures, offering a full device integration. Most of via middle activities are being done on 300mm wafers, and standard features for these TSVs are being established. In comparison, OSATs and Mid-End fabs, as well as MEMS foundries, are mostly focusing on via last integration approaches. OSATs are capable of performing wafer back side thinning, as well as via reveal processes, prior to bumping and stacking the dies. Figure 2 shows a map with key players coming from different business models using via middle integration. The report provides insights and detailed information on worldwide through-silicon-via activities for both via middle and via last, the companies involved, and comparison of their activities. More information at http://www.i-micronews.com/reports/3DIC-2-5D-TSV-Interconnect-Packaging-2014-Business-Update/8/450/

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Page 1: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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3DIC & 2.5D TSV Interconnect for Advanced Packaging

Advanced Packaging Team

YOLE DEVELOPPEMENT

COLLABORATION

INNOVATION

NEW PERSPECTIVES

FROM TECHNOLOGIES TO MARKET

2014 – Business Update Report

Page 2: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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Yole’s research is focused on:

Applicative Packaging: moving to high performance, low cost, application driven packaging techniques

Advanced Packaging: moving to high performance, low cost, collective wafer level packaging techniques

Semiconductor Packaging

Camera Level Packaging Power Module Packaging MEMS Packaging LED Packaging

Lead-Frame LCC Wirebonding BGA WLCSP 3D WLP SIP

QFN PGA Flip Chip POP FOWLP 2.5D Interposer

2

YOLE

DEVELOPPEMENT

From TECHNOLOGIES to MARKET

Copyright @ Yole Developpement SA.. All rights reserved

FOCUS of this report

3DIC

Page 3: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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The Evolution of Semiconductor PackagingA bridging technology between ICs and PCBs

Feature sizes CMOS transistors: 28nm

Feature sizes of PCBs

1970through hole technology

1980Surface mountdevices

De

ve

lop

me

nt

in C

MO

S p

roce

ssin

g c

ap

ab

ilit

ies

De

ve

lop

me

nt

in P

CB

pro

cess

ing

ca

pa

bilit

ies

1990CSPs/BGAsSiPs

2000WLCSPmore SiPsFlip Chip BGAPoP

20103DICTSVFan-out WLCSPCu pillarsSilicon interposers

Page 4: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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The Evolution of Semiconductor PackagingA bridging technology between ICs and PCBs

Feature sizes CMOS transistors: 28nm

Feature sizes of PCBs

1970through hole technology

1980Surface mountdevices

De

ve

lop

me

nt

in C

MO

S p

roce

ssin

g c

ap

ab

ilit

ies

De

ve

lop

me

nt

in P

CB

pro

cess

ing

ca

pa

bilit

ies

1990CSPs/BGAsSiPs

2000WLCSPmore SiPsFlip Chip BGAPoP

20103DICTSVFan-out WLCSPCu pillarsSilicon interposers

….across several markets

Mobile:High-end MultimediaSmart-phones / PMP

High-densitySolid State

Storage & µ-Cards

Computing: Notebooks / MID ‘connectivity’ devices

Consumer:Gaming / Graphic

application engines

Industrial: HPC/ Network, Servers

Consumer: High-performance Digital Video

Wireless: Connectivity /

Network Center

Medical Military & AerospaceTransportation:Automotive,Trains,HEV/EV

Renewable Energy:Photovoltains, WindTurbines…

Telecom: PowerSupplies…

Industrial

Page 5: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Silicon / Interconnection trend

500

020406080100

Number I/O per cm²

20.000

10.000

1500

CMOS90 CMOS45CMOS28

CMOS16

CMOS65FinFET

Technology NodeCMOS [nm]

Scaling of Transistor Nodes => I/Os Density

Increase

Page 6: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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TSV in a nutshell

Logic Memory

CMOS Image

Sensors

MEMS

Photonics

Others(Power,

LED, RF…)

ThroughSilicon

ViaTSV

Page 7: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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77

YOLE

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7From TECHNOLOGIES to MARKET

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Page 8: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Global 3DIC / TSV Activity Worldwide

Broad range of key players involved in 3D Technology from different business models (Fabless, IDMs, OSATs, Foundries...)

Page 9: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Landscape Via Middle (non exhaustive list)

0

5

10

15

20

25

0 10 20 30 40 50 60 70 80 90 100 110 120 130

Dia

mete

r [µ

m]

Depth [µm]

VIA MIDDLE

2.5D

Interposer

3DIC

…and again much more players

with others TSV features!!!

Page 10: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Logic

CMOS Image

Sensors

MEMS

Photonics

Others(Power,

LED, RF…)

Memory

TSV in a nutshell

Memory

ThroughSilicon

ViaTSV

Page 11: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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DRAM Technology Trends2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

From JEDEC specifications

LPDDR1

DDR3

LPDDR2

LPDDR3

Wide I/O

DDR4

LPDDR4 / Wide I/O2

Tech

no

log

y(d

en

sity

/ba

nd

wit

hp

er

die

)

Depending on requirements in voltages and data transfer speeds differenttypes of DDR memory are being developed to fulfill the future needs

Page 12: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

Mobile DRAM Memory Trends

PC DRAM DDR3 DDR4

GraphicsDRAM GDDR5 HBM

3D MobileDRAM Wide I/O1 Wide I/O2

MobileDRAM LPDRR2 LPDRR3 LPDRR4

3D Technology

From JEDEC specifications

Page 13: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Markets Demand: High Performance, Lower Power Consumption

High Performance Computing (HPC)•Game Consoles•Microprocessors•Networking

Networking, Wired Applications•Servers, Storage•Graphics•Digital TV Networking

Consumer, Wireless, Mobile Computing•Smartphones•Tablets•Portable Consumer

Page 14: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Logic

MEMS

Photonics

Others(Power,

LED, RF…)

Memory

TSV in a nutshell

ThroughSilicon

ViaTSV

CMOS Image

Sensors

Page 15: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Main Trends in CMOS Image SensorFrom FSI to BSI to 3D Stacked

SOC FSI Imager

I/Os

I/Os

I/O

s

I/O

s

Power Management

An

alo

g

Analog

BSI Imager

Readout circuit

Hybridization

I/Os

I/Os

I/O

s

I/O

s

Power Management

An

alo

g

Analog

BSI is a key enabling technology to go to 3D integration• Pads of the read-out layer are located on the same side of the image sensor processing chip (DSP).

• That configuration makes the integration easier by having direct access to each pixel site.

With FSI sensors, the 3D integration would be very difficult because TSVs should crossthrough the whole active pixel array.

End of 2012, Sony released the first stacked image sensor (see right picture).

In the future, 3D stacking will become more used as more functionalities will berequired.

Mainstream since the 2000s

All BSI players since 2009 October 2012: Sony to release the first hydrid CIS “EXMOR

RS”

Page 16: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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CMOS Image Sensor Evolution

FSI BSI 3D Stacked BSI

20122008

TSV Hole to replace shellcase approach

Wafer Level PackagingInterconnection

Trench TSVBEOL Interconnection

TSV BEOL and DSP Interconnection

« Real 3D »

TSV

Cro

ss-s

ect

ion

SEM

TSV

Ne

ed

sIn

teg

rati

on

Sch

em

e

Page 17: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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Comparison with previous 8Mp sensorsSignificant Improvement brought by Sony

Phone Ref. (Year)CIS Manufacturer

Resolution/Techno

Pixel sizePixel ArrayArea

CIS AreaDies per wafer(12-inch)

Motorola Razor (2011) Omnivision 8Mp/BSI 1.4µm 16mm² 43mm² 1,500

Apple iPhone 4S (2011) Sony 8Mp/BSI 1.4µm 16mm² 35.4mm² 1,816

Samsung Galaxy SII (2011) Samsung 8Mp/BSI 1.4µm 16mm² 34.2mm² 1,884

Apple iPhone 5S (2013) Sony 8Mp/BSI 1.5µm 18mm² 28.5mm² 2,268

Courtesy System Plus Consulting

~50% ~60% ~60% ~90%

Increase of pixel area

Page 18: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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Our Global Presence

Yole Inc.

Yole Europe30%

40%

30% Yole Korea

Yole KK Japan

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From TECHNOLOGIES to MARKET

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Offices in Lyon (HQ),

Nantes, Nice & Paris

4

Page 19: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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From TECHNOLOGIES to MARKET

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MEDIANews feed / Webcasts

Technology Magazines

www.yole.fr

FINANCEM&A / Valuation / Due Diligence /

Technology brokerage

www.yolefinance.fr

www.i-micronews.com

REPORTSMarket & technology

Patent Investigation

Reverse costing

CONSULTINGMarket research

Technology & Strategy

Patent Investigation

Reverse costing

WORKSHOPSFocused seminars

Yole Group Activities

5%

Page 20: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

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The company is involved in the following areas:

30 full time global analysts with technical, marketing and management background

35000 interviews per year

Field of Research

Advanced Packaging Photovoltaics LED & Compound Semi Power Electronics

Microfluidics & Bio Tech MEMS & Sensors Semiconductor Manufacturing: Equipment & Materials

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Overview of Our Main Services

Technical comparison of new processes at material or device level

Detailed analysis of the cost structure of a specific technology

Analysis of technology evolutions and industrial implementation

Identification of new applications, services and markets

Set-up market segmentation a

Proposal of marketing and action plans

Market research & marketing analysis

Technical & reverse

costing analysis

Strategic analysis

Business Development

Specific Services for

Investors

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cations

Analysis of positioning to create value

Development of action plans to improve company performance

Support in implementation and fund raising

Contact with interesting companies and possible partners

Set up meetings (face to ace of by phone)

Follow up in order to implement the decision taken

Evaluation and analysis of business plans

Evaluation of production infrastructure

Expertise and due diligence before M&A

Technology brokerage

Providing forum and journalistic support with publishing articles

Organizing and coordinating webcasts

Providing journalistic help and coordination with focused on multiple action magazines

On-line Advertisement on i-Micronews website

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Breadth of the analysis

De

pth

of

the

an

aly

sis

Yole Custom Analysis

YoleAnnual Actions

Yole Standard Reports

Multiple reports(> 3) offer can be acquired through

annual subscription offer

Direct access to Yole’s analyst to discuss and obtain specific information quickly throughout the year

Custom projects are designed to meet your specific needs: Business development, Teardown reverse engineering & costing analysis, IP analysis, Strategic analysis, new product marketing analysis and segmentation of your market, due diligence, M&A, etc.

Workshops

YoleWorkshops

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Instead of buying 3-5 different reports to cover yourlist of questions, Yole analysts can prepare a“custom presentation” to be presented face-to-faceto your company

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Yole Developpement consultants provide market analysis, technology evaluation, and business plan along the entire value chain

Institutions, Investors

and Advocates

Materialsand

EquipmentSuppliers

Component and

Device Makers

Integrators and

End Users

Serving the Entire Value Chain

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From TECHNOLOGIES to MARKET

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….Some of our Customers

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Our team Thibault Buisson, Technology and Market AnalystThibault is a member of the Advanced Packaging team at Yole Développement. He graduated from INPG with aMaster of Research in Micro and Nano electronics and from Polytech’ Grenoble with an engineering degree inMaterial Sciences. He then joined NXP semiconductors as R&D process engineer in the thermal treatment areato develop CMOS technology node devices from 65 to 45nm. Afterwards, he joined IMEC Leuven and worked formore than 5 years as process integration engineer in the field of 3D technology. During this time, he has workedon several topics from TSV to micro-bumping and stacking. He has authored or co-authored fifteen internationalpublications in the semiconductor field.

Rozalia Beica, CTO and Business Unit DirectorRozalia Beica is the CTO and Business Unit Director leading Advanced/3D Packaging and SemiconductorManufacturing activities within Yole Développement. For more than 15 years she has been involved in theresearch, strategic marketing and application of WLP and 3D/TSV at materials (Rohm and Haas), equipment(Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. Rozalia hasauthored over 50 papers and publications and she is actively participating in several 3D & Advanced PackagingCommittees worldwide. Rozalia has a M.Sc in Chemical Engineering (Romania), a M. Sc. In Management ofTechnology (USA) and a GXMBA from IE University (Spain).

Amandine Pizzagalli, Technology and Market AnalystAmandine Pizzagalli is in charge of equipment & material fields for the Advanced Packaging & Manufacturingteam at Yole Développement after graduating as an engineer in Electronics, with a specialization inSemiconductors and Nano Electronics Technologies. She worked in the past for Air Liquide with an emphasis onCVD and ALD processes for semiconductor applications.

Jérôme Azémar, Technology and Market AnalystJérôme Azémar is a member of the Advanced Packaging & Manufacturing team. Upon graduating from INSAToulouse with a master’s in Microelectronics and Applied Physics, he joined ASML and worked in Veldhoven forthree years as an Application Support Engineer, specializing in immersion scanners. During this time he acquiredPhotolithography skills which he then honed over a two year stint as a Process Engineer at STMicroelectronics.While with ST he developed new processes, co-authored an international publication and worked on metrologystructures embedded on reticules before joining Yole Développement in 2013.

Page 26: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Report by Yole Developpement

orDer forM3DIC & 2.5D TSV Interconnect for Advanced Packaging – 2014 Business Update

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Founded in 1998, Yole Développement has grown to become a group of companies providing marketing, technology and strategy consulting, media in addition to corporate finance services. With a strong focus on emerging applications using silicon and/or micro manufacturing (technology or process), Yole Développement group has expanded to include more than 50 associates worldwide covering MEMS, Compound Semiconductors, LED, Image Sensors, Optoelectronics, Microfluidics & Medical, Photovoltaics, Advanced Packaging, Manufacturing, Nanomaterials and Power Electronics. The group supports industrial companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business.

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