Power Electronic System Design I Winter 2010

Steven Trigno, Satya Nimmala, Romeen Rao

Buck-Boost Converter Analysis

PWMVg

LC

VcR

iL

+

-

iC

Figure 1-Buck-boost circuit schematic implemented with practical switch

When the transistor is turned ON, the diode is reverse-biased; therefore, not conducting (turned OFF)

and the circuit schematic looks like as follows: 0 < t < DTs

Vg

LC

VcR

iL

+

-

iC

Transistor ON, Diode OFF

VL

+

_

V

ig

Figure 2-Schematic of buck-boost converter when the switch is ON

VL(t) = Vg – iL.RON ≈ Vg – iL.RON

iC(t) = -v(t) / R ≈ −𝑉

𝑅

ig(t) = iL(t) ≈ IL

When the transistor is OFF, the Diode is turned ON (DTs < t < Ts). The circuit is shown in fig 3:

Vg

LC

VcR

iL

+

-

iC

Transistor OFF, Diode ON

VL

+

_

V

ig

Figure 3 – Schematic Buck-boost converter when the switch is OFF

VL(t) = -v(t) ≈ -V

Ic(t) = 𝑖𝐿(𝑡) −𝑣(𝑡)

𝑅 ≈ 𝐼𝐿 −

𝑉

𝑅

Ig(t) = 0

volt.second balance:

<VL(t)> = 0 = D(Vg - IL.RON) + D’(-V)

charge balance:

<ic(t)> = 0 = D(-V/R) + D’(IL – V/R)

Average input current:

<ig> = Ig = D(IL) + D’(0)

Next, we construct the equivalent circuit for each loop equation:

Inductor loop equation: DVg - IL.DRon – D’V = <VL> = 0

+

_ +

_DVg D’V

DRon

IL

Capacitor node equation: 𝐷′ 𝐼𝐿 − 𝑉

𝑅= < 𝑖𝐶 > = 0

D’IL

R

+

_

V

Input current (node) equation: Ig = D.IL

D’IL

+

_

Vg

Ig

Then we draw the circuit models together as shown below:

DIL

+

_

Vg

Ig

DVg D’V D’IL

+

+

_

_

V

IL

+_

1:D transformer

reversed polarity marksD’:1 transformer

DRon

Model including ideal dc transformers:

+

_

Vg

Ig +

_

V

ILDRon

1:D D’:1

R

𝑽 = 𝑫

𝑫′𝑽𝒈

𝑹

𝑹 + 𝑫

(𝑫′)𝟐𝑹𝒐𝒏

→ 𝑽

𝑽𝒈=

𝑫

𝑫′

𝟏

𝟏 +𝑫

(𝑫′)𝟐𝑹𝒐𝒏𝑹

And for the efficiency (η):

η = 𝟏

𝟏+𝑫

(𝑫′ )𝟐+

𝑹𝒐𝒏𝑹

IL = 𝑽

𝑫′𝑹

Ploss = 𝑰𝑳𝟐. 𝑫𝑹𝑶𝑵

Discontinuous Conduction Mode in Buck-Boost Converter

PWM

Vg

L

+

_

C

VR

iL

+

-

Figure 4-Buck-boost converter

During D1Ts:

Vg

L

+

_

C

VR

iL

+

-

Figure 5-Transistor ON, Diode OFF

VL = Vg

During D2Ts:

Vg

L

+

_

C

VR

iL

+

-

VL

Figure 6 - Transistor OFF, Diode ON

VL = -V

During D3Ts:

Vg

L

+

_

C

VR

iL

+

-

VL

Figure 7 - Transistor OFF, Diode OFF

VL = 0

Boundary between modes:

CCM:

∆𝒊 = 𝑫𝑻𝒔𝑽𝒈

𝟐𝑳 (∆i = peak ripple in L)

∆𝑽 =𝑫𝑻𝒔𝑽

𝟐𝑹𝑪 (∆V = peak ripple in C)

IL = 𝑽

𝑫′𝑹 (average inductor current)

Boundary:

𝑰𝑳 > ∆𝑖 𝑓𝑜𝑟 𝐶𝐶𝑀

𝑰𝑳 < ∆𝑖 𝑓𝑜𝑟 𝐷𝐶𝑀

→ 𝑽

𝑫′𝑹 >

𝑫𝑻𝒔𝑽𝒈

𝟐𝑳

𝑽 = 𝑫

𝑫′𝑽𝒈 in CCM

→ 𝑫

(𝑫′)𝟐𝑽𝒈

𝑹 >

𝑫𝑻𝒔𝑽𝒈

𝟐𝑳

𝟐𝑳

𝑹𝑻𝒔 > (𝑫′)𝟐

Buck Boost Convertor

DTS D’TS

KVL

-Vg + VL = 0 -VL + V = 0

VL = Vg VL = V

KCL

ic =

−V

VR ic = iL −

VVR

Inductor volt sec balance:

< VL > = DVg + D′V = 0

D′V = -DVg

V

Vg =

−D

1−D

Capacitor Charge Balance:

< ic > = D −VVR

+ D′ i −V

VR

= −DV

VR+ D′iL − D′ V

VR

= D′ iL − DV

VR−D′ V

VR

= D′ iL −V

VR(D + D′)

= D′ iL − V

VR = 0

iL = 1

1−D

V

R

State Space Analysis

DTs:

Apply KVL to fig.1.

−𝑉𝑔 + 𝐿𝑑𝑖

𝑑𝑡= 0

𝑑𝑖

𝑑𝑡=

𝑉𝑔

𝐿

Apply KCL to fig.1.

𝐶𝑑𝑖

𝑑𝑡+

𝑉

𝑅= 0

𝑑𝑣

𝑑𝑡= −

𝑉

𝑅𝐶

𝑑

𝑑𝑡 𝑖𝑣 =

0 −1

𝐿1

𝑐−

1

𝑅𝐶

𝑖𝑣 +

1

𝐿

0 𝑉𝑔 → (1)

𝑑

𝑑𝑡 𝑖𝑣 = 𝐴1

𝑖𝑣 + 𝐵1 𝑉𝑔 → (2)

By comparing the equation’s (1) and (2) we get values of 𝐴1 and 𝐵1

𝐴1 = 0 −

1

𝐿1

𝑐−

1

𝑅𝐶

𝐵1 = 1

𝐿0

D’Ts:

Apply KVL to fig.2.

−𝐿𝑑𝑖

𝑑𝑡+ 𝑉 = 0

𝑑𝑖

𝑑𝑡=

𝑉

𝐿

Apply KCL to fig.2.

𝑖 + 𝐶𝑑𝑣

𝑑𝑡+

𝑉

𝑅= 0

𝑑𝑣

𝑑𝑡= −

𝑖

𝐶−

𝑉

𝑅𝐶

𝑑

𝑑𝑡 𝑖𝑣 =

01

𝐿

−1

𝐶−

1

𝑅𝐶

𝑖𝑉 +

00 𝑉𝑔 → (3)

𝑑

𝑑𝑡 𝑖𝑣 = 𝐴1

𝑖𝑣 + 𝐵1 𝑉𝑔 → (4)

By comparing the equation’s (3) and (4) we get values of 𝐴2 and 𝐵2

𝐴2 = 0

1

𝐿

−1

𝐶−

1

𝑅𝐶

𝐵2 = 00

𝐴 = 𝐷𝐴1 + 𝐷′𝐴2

𝐴 = 0

𝐷′

𝐿

−𝐷′

𝐶−

1

𝑅𝐶

𝐵 = 𝐷𝐵1 + 𝐷′𝐵2

𝐵 = 𝐷

𝐿0

𝑋 = −𝐴‾¹-----𝐵𝑉𝑔

𝑋 = 𝐼𝑉 = −

0𝐷′

𝐿

−𝐷′

𝐶−

1

𝑅𝐶

‾1 𝐷

𝐿0 𝑉𝑔

𝑋 = 𝐼𝑉 =

𝐷𝑉𝑔

𝐷′2𝑅

−𝐷𝑉𝑔

𝐷′

𝐼 =𝐷𝑉𝑔

𝐷′2𝑅

𝑉 = −𝐷𝑉𝑔

𝐷′

Calculating inductor current ripple and capacitor voltage ripple:

We know that the following formula for calculating the ripple values

∆𝑋 = (𝐴1𝑋 + 𝐵1𝑉𝑔)𝐷𝑇𝑠

∆𝑋 = ∆𝐼∆𝑉

=

𝐷𝑉𝑔𝑇𝑠

𝐿𝐷2𝑉𝑔𝑇𝑠

𝐷′𝑅𝐶

Inductor current ripple is

∆𝐼 =𝐷𝑉𝑔𝑇𝑠

𝐿

Capacitor voltage ripple is

∆𝑉 =𝐷2𝑉𝑔𝑇𝑠

𝐷′𝑅𝐶