bi-directional high-conversion-ratio cllc resonant

IEEJ Journal of Industry ApplicationsVol.9 No.5 pp.515–522 DOI: 10.1541/ieejjia.9.515

Paper

Bi-Directional High-Conversion-Ratio CLLC Resonant Converter with aNew Synchronous Rectification Scheme for Low Conduction Loss

Kai Sun∗a)Non-member, Yucheng Gao∗ Non-member

Huan Chen∗ Non-member

(Manuscript received June 28, 2019, revised April 9, 2020)

This paper proposes a new synchronous rectification (SR) scheme for frequency-modulated bi-directional CLLCresonant converters. By introducing a small-phase-shift between the two full-bridges and utilizing the switching tran-sient, the proposed scheme effectively avoids the magnetizing current being provided from the low voltage side. Thisleads to considerable reduction in the conduction losses and current stress of the switches in a high-step-down design.Furthermore, the output voltage characteristic is analyzed using a novel mathematical model, which, comparing to thefundamental harmonic approximation method, can not only acquire a more accurate result of steady-state character-istic, but also calculate an accurate set of initial values for the passive components, which is crucial to determine theproper dead-time and phase-shift. Based on the new model, the boundaries of dead-time and phase-shift are discussedin detail. Finally, a prototype is built, and experiments are conducted to verify the principles of the proposed scheme.

Keywords: CLLC resonant converter, phase shift, synchronous rectification, high-step-down

1. Introduction

Resonant full-bridge converter is a popular choice for high-step-down dc-dc conversion applications, due to its simplicityto achieve high conversion ratio and zero voltage switching(ZVS). Comparing to the common LLC converters, CLLCconverter, as shown in Fig. 1(a), has a symmetrical featuredesirable for bi-directional operations (1)–(4), and is hence pre-ferred in various applications, especially the emerging energystorage and dc distribution industries (5)–(8).

In the conventional control scheme of CLLC resonant con-verters, the output rectifier switches are turned off and theanti-parallel diodes are utilized (1) (9) (10). In this scheme, how-ever, the bi-directional power transition speed is inevitablyslow due to the transition of the drive signals. Moreover,in many cases, the diodes produce high conduction loss dueto forward voltage drop and hence limit the converter effi-ciency. Synchronous rectification (SR) is an effective wayto solve these issues, which has been widely applied in LLCresonant converters (11)–(17). In literature (11), a synchronous rec-tification method is proposed to make the on/off behavior ofMOSFETs the same as the diode rectifier. In literature (12),the synchronous rectification is used to deal with problemscaused by parasitic parameters of the half bridge. In litera-ture (13), cutting down the cost of the synchronous rectificationis the main target. In literature (14), the synchronous rectifica-tion is realized by sending the same PWM signals to the pri-mary and the secondary side. In literature (15), a synchronousrectification method is proposed where PWM signals of the

a) Correspondence to: Kai Sun. E-mail: [email protected]∗ State Key Lab of Power Systems, Tsinghua University

3-310, West Main Building, Tsinghua University, Haidian,Beijing 100084, China

(a) basic topology

(b) normalized equivalent circuit

Fig. 1. Circuit of full-bridge CLLC resonant converter

secondary side lags behind that of the primary side. In lit-erature (16), only the dead time of one of the two half bridgesin secondary H bridge is extended. In literature (17), PWMsignals of the secondary side lags behind that of the primaryside and the dead time of secondary side is larger. But stillrelevant discussions on the CLLC converters are limited.

Furthermore, the magnetizing current in the transformermust be kept at a certain amplitude for achieving ZVS in res-onant converters (18). But in a high-step-down design, as thetransformer turns ratio is large, the magnetizing current willbe significantly higher if the transformer is magnetized bythe low voltage side than by the high voltage side, leading toincreased copper loss and conduction loss.

This paper proposes a new SR scheme that has a promis-ing capability of fast bi-directional power transition as wellas ensuring the high voltage supply provides the magnetiz-ing current. The target application is the two-stage energystorage system, where The CLLC converter is mainly used to

c© 2020 The Institute of Electrical Engineers of Japan. 515

Bi-Directional CLLC Resonant Converter（Kai Sun et al.）

(a) conventional scheme (b) proposed scheme

Fig. 2. Conventional and proposed SR schemes forCLLC converter

guarantee the high efficiency power conversation. Comparingto the traditional SR scheme, which shows inconsistency inthe switching transient process of bi-directional operations,the proposed scheme utilizes the switching transient process.Specifically, the proposed scheme introduces a small phase-shift between the two full-bridges, as shown in Fig. 2. Theword “small” refers to the condition that the phase-shift tp isless than the dead-time td. To guarantee the magnetizing cur-rent provided by the high voltage side in a high-step-downdesign, the drives on the low-voltage side are always leading.

This paper is an extension of (19), where the simula-tion and experimental results show disagreement with thefirst harmonics analysis-based results, and consequently thephase-shift and dead-time determination is not accurateenough. In addition, a similar idea to introduce phase-shiftin the synchronous rectification for the CLLC converter isintroduced in (20), but it is generally for half-bridge topol-ogy, and again, the gain analysis is based on first harmonicsanalysis method. In this paper, the principle of the switchingtransient under the proposed SR scheme is further analyzed.Then, a time domain-based analysis method for steady-statecharacteristics of the converter is introduced. Based on theimproved model, the limitations of phase-shift and dead timeare discussed. Furthermore, a 1 kW prototype is built, andthe theoretical results are verified through experiments.

2. Principle of Switching Transient

The normalized equivalent circuit of a CLLC converter isillustrated in Fig. 1(b), where Lr, Cr1, Cr2 compose a reso-nant tank with a resonant frequency of f r, and Lm is usuallymore than three times larger than Lr. For the analysis of theswitching transient, the following assumptions are made:

i. As Lm is significant than Lr, the voltage on Lm is closeto a square wave, and therefore, im is regarded as a triangularwave in a switching period, and is constant during switchingtransient;

ii. As the resonant period is far longer than the switch-ing transient, the voltage variation of Cr1, Cr2 are neglectedduring the switching transient;

iii. Before the switching transients, the changing rates ofi1 and i′2 are generally low, and their influence is ignored inthe switching transient analysis.

The switching transient when u1, u′2 change from negativeto positive is taken here as an example. According to theinitial direction of i′2, two circumstances are discussed sep-arately. The key waveforms are presented in Fig. 3, and thecorresponding circuit diagrams are demonstrated in Fig. 4.2.1 i′2 < 0 before Switching Transient Right be-

fore time t0, the following conditions will be true: u1 = −udc1,u′2 = −u′dc2, im < 0, uL is close to zero, and S2, S3, S6 and S7

are conducting.

(a) i′2 < 0 before switching transient

(b) i′2 > 0 before switching transient

Fig. 3. Key waveforms of switching transient

Stage 1 [t0, t1]: At time t0, S6 & S7 are turned off. Withthe presence of Lm and Lr, i′2 cannot have a step change andis hence negative, so it begins to charge the parasitic capaci-tance of S6 & S7 and discharge that of S5 & S8.

Stage 3 [t2, t3]: At time t2, i′2 reaches zero, so D5 & D8 areturned off, allowing C′s2 and Lr to resonate. In this interval, i′2will continue rising, and u′2 starts to decrease.

Stage 2 [t1, t2]: At time t1, u′2 = u′dc2, and then diodes D5

& D8 are turned on. During this time period, i′2 increasesat a high and constant rate, which is mainly decided by thevoltage drop on Ls:

di′2dt=

udcl + udc′

Lr· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (1)

Stage 3 [t2, t3]: At time t2, i′2 reaches zero, so D5 & D8 areturned off, allowing C′s2 and Lr to resonate. In this interval, i′2will continue rising, and u′2 starts to decrease.

Stage 4 [t3, t4]: At time t3, u′2 = −u′dc2, so uL becomes smallagain, and i1, i′2 will only change at a very slow rate. More-over, as im < 0 and i′2 > 0, there should be i1 < 0, meaningthat S2 & S3 are conducting.

Stage 5 [t4, t5]: At time t4, S2 & S3 are turned off by thecontroller. Consequently, i1 begins to charge/discharge theparasitic capacitance Cs1 of S1-S4.

Stage 6 [t5, t6]: At time t5, u1 = udc1, diodes D1 & D4 areturned on. According to the high and constant voltage added

516 IEEJ Journal IA, Vol.9, No.5, 2020


(a) circuit before switching transient

(b) during t0–t2

(c) during t2–t4

(d) during t4–t6

(e) during t6–t8

(f) circuit after t9 when all transistors are turned on

Fig. 4. Key current paths and circuit diagrams during aswitching transient for initial value of i′2 is negative. Di-rections of currents are marked by red arrows, and direc-tions of voltage drops are marked by blue arrow

Fig. 5. Key current paths and circuit diagrams during aswitching transient during t0–t4 for initial value of i′2 ispositive

on Lr, i1 will decrease and i′2 will increase at a high and con-stant rate, at a value opposite to that of (1).

Stage 7 [t6, t7]: At time t6, i′2 reaches zero, so D6 & D7

are turned off and, after another charging process, D5 & D8

are turned on. The resonant process of C′s2 and Ls decides thefinal current:

i′2 = −2udd

√C′s2/Lr · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (2)

Stage 8 [t7, t8]: During this stage, i1, i′2 will be changing ata very slow rate, and ideally i′2 will still be negative at the endof this period.

Stage 9 [t8, t9]: At time t8, since D5 & D8 are on right be-fore time t8, S5 & S8 can be turned on under ZVS condition.

Stage 10: At time t9, ZVS turning-on can be achieved forS1 & S4.2.2 i′2 > 0 before Switching Transient If i′2 > 0,

then at time t0 the current will switch from S6 & S7 to D6

& D7, and u′2 will not change. Before S2 & S3 turn off, thestatus is the same to that of Stage 4 in part A, as shown inFig. 5. Then, the system will respond as [t4, t9] described inthe previous part.

In summary, for both cases, the switching transient ends attime t7, when i′2 equals to the value specified in (2), which canusually be considered as a very small value. Therefore, whenthe converter is modulated at a switching frequency f s closeto f r, which means the current waveforms of the inverter andthe rectifier are approximately sinusoidal, the switching tran-sient analyzed above will guarantee that the ac current of thelow voltage side is in phase with the corresponding ac volt-age. Consequently, the low voltage side will provide almostzero reactive power, and the transformer is fully magnetizedby the high voltage side.

3. Steady-State Characteristic

In previous work on resonant converters, the currents in theresonant tank are approximated as simply sinusoidal wavesat the resonant frequency, and a fundamental frequency sim-plification is applied to the analysis of steady-state charac-teristic (19). However, it is very common that Lm is less thanten times larger than Lr, which will also result in a visible,lower-frequency sinusoidal term in the currents. In fact, whenthe switching frequency is significantly different to the reso-nant frequency, the solution acquired in (19) shows that therewould be a notable phase-shift between the two ac voltagesudc1 and udc2, which is incorrect since the phase-shift in thesynchronous rectification scheme is very small.

It is desired to develop an improved analytical model for



⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣uCr1(t)u′Cr2(t)iLm(t)i′2(t)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦ = A(t)

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

udc1(0)udc2(0)udc3(0)udc4(0)udc5(0)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦+

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣a11(t) a12(t) a13(t) a14(t) a15(t) a16(t)a21(t) a22(t) a23(t) a24(t) a25(t) a26(t)a31(t) a32(t) a33(t) a34(t) a35(t) a36(t)a41(t) a42(t) a43(t) a44(t) a45(t) a46(t)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

udcl(0)

udc2(0)

uCr1(0)

uCr2(0)

iLm(0)

i′2(0)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (6)

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣uCrI(0)

u′Cr2(0)iLm(0)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦ = −⎡⎢⎢⎢⎢⎢⎢⎢⎣uCrl(T/2)u′Cr2(T/2)iLm(T/2)

⎤⎥⎥⎥⎥⎥⎥⎥⎦ = −⎡⎢⎢⎢⎢⎢⎢⎢⎣a12(T/2) a14(T/2) a15(T/2)a22(T/2) a24(T/2) a25(T/2)a32(T/2) a34(T/2) a35(T/2)

⎤⎥⎥⎥⎥⎥⎥⎥⎦⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣udc2(0)

u′Cr2(0)iLm(0)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦ −⎡⎢⎢⎢⎢⎢⎢⎢⎣a11(T/2) a13(T/2) a16(T/2)a21(T/2) a23(T/2) a26(T/2)a31(T/2) a33(T/2) a36(T/2)

⎤⎥⎥⎥⎥⎥⎥⎥⎦⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣u′dcl(0)uCr1(0)

i′2(0)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦ · · · · · · (8)

the proposed SR scheme, not only for a more accurate steady-state characteristics, but also for an accurate set of initial val-ues for the passive components, which is crucial to determinethe proper dead-time and phase-shift.

Therefore, in this study, a more accurate model based onthe Laplace domain is proposed, where all the harmonics areincluded in the analytical result. In half of the switching pe-riod, S1, S4, S5 and S8 are constantly turned on, and the cir-cuit becomes a simple network of impedances and capaci-tances. In this system, there are four state variables iLm, iLr,uCr1, u′Cr2, as well as two constant inputs udc1 and u′dc2. Thecharacteristic equation of this circuit is(

s2 − ω21

)·(s2 − ω2

2

)= 0 · · · · · · · · · · · · · · · · · · · · · · · · · (3)

where

ω1, ω2 =

[C′r2Lm +Crl (Lm + Lr)

2

±√(

C′12Lm +Cr1 (Lm + Lr)

2

)−Cr1C′r2LmLr]0.5

· · · · · · · · · · · · · · · · · · · · (4)

The characteristic equation indicates that the step responser of any input u (either input udc1, u′dc2 or the initial valueof iLm, iLr, uCr1, u′Cr2) has only a dc term and two sinusoidalterms with a frequency of ω1 and ω2, which could be writtenas

r(t) = [a1 sin(ω1t + ϕ1) + a2 sin(ω2t + ϕ2) + a3]u(t)

· · · · · · · · · · · · · · · · · · · · (5)

where a1, a2, a3, φ1 and φ2 can be determined either analyt-ically, or numerically by simulation and curve fitting. In thisparticular problem, the time domain equation can be writtenas

where

A(t) = A1 sin(ω1t) + A2 cos(ω1t) + A3 sin(ω2t)

+ A4 cos(ω2t) + A5 · · · · · · · · · · · · · · · · · · · · · · · (7)

Then, by performing an analysis on the half switching pe-riod when u1 and u′2 are constants and positive, the steady-state output voltage u′dc2 characteristic can be acquired.Specifically, a set of linear equations about the initial valuesiLm,0, iLr,0, uCr1,0, u′Cr2,0 as well as u′dc2 can be listed based onthe following conditions:

Fig. 6. Output voltage characteristic of the prototypeconverter

a. The final values (when t = Ts/2) of iLm, uCr1, u′Cr2 areexactly opposite to their initial values;

b. iLr(0) = iLm(0) − i′2(0), where i′2(0) is specified in (2);The integral of iLr times udc1 in the half switching period

equals to the input energy, which is 0.5Pf s.c. The integral of iLr times udc1 in the half switching pe-

riod equals to the input energy, which is 0.5Pf s.In other words, the initial values of udc2(0), u′Cr2(0) and iLm(0)

are acquired by solving the following equation:where

udcl(0) = Udcl · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (9)

uCr1(0) =PUdc1

2 fSCr1· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (10)

i′2(0) = −2udc

√C′s2/Lr · · · · · · · · · · · · · · · · · · · · · · · · · · (11)

To demonstrate the relationship between the output volt-age characteristic and circuit parameters, the following vari-ables are introduced: λ is the ratio of the magnetizing induc-tance to the resonant inductance, i.e., λ = Lm/Lr, and kc isdefined as kc = Cr1/(Cr1+Cr2/n2), which is ratio of the twocapacitor impedances. Based on the full harmonic model, thefrequency-gain curves of some sample circumstances are ac-quired, as demonstrated in Fig. 6, where λ is set to 4 in allcases and f N is the normalized frequency. f N can be calcu-lated as f s/f r. f s is the switching frequency and f r is the res-onant frequency. The result is generally showing agreementwith the fundamental harmonics analysis in (19). However,it can also be observed that the output voltage characteris-tic is more consistent regarding to power when kc is high,



Table 1. Parameters of CLLC Converter Prototype

Fig. 7. Output voltage characteristic of the prototypeconverter

whereas it is highly dependent to load when kc is low. More-over, at low kc it would be impossible to regulate the voltageunder bi-directional power conditions, because the maximumvoltage at P = +1.0 pu is equal to the minimum voltage at P= −1.0 pu. Therefore, it would be desired to keep kc rela-tively large, so the output voltage regulation capability willbe ensured. Furthermore, a CLLC converter with parame-ters given in Table 1 is taken as an example. The calculatedoutput voltage u′dc2 versus f s at several given P is plotted inFig. 7, which shows that for both power directions, the outputvoltage characteristics are generally close, and udc2 decreasesas f s increases.

4. Phase-Shift and Dead-Time Restrictions

A major feature of the proposed SR scheme is that theclaimed benefit of having magnetizing current provided fromthe high voltage side can be achieved automatically, whichdoes not require any high-accuracy sampling nor any com-plicated calculation. Still, there are certain restriction bound-aries for the phase-shift and dead-time to ensure the proposedSR scheme works properly. According to the principle of op-eration discussed in Section II, the following two conditionsmust be satisfied:

a. i′2 must cross over zero during a switching transient,otherwise the reactive current will be supplied by the lowvoltage side.

b. i′2 must be negative right before S5 and S8 turn on toachieve ZVS.

To clearly demonstrate the restriction conditions, the fol-lowing variables are defined as shown in Fig. 2: td is the deadtime, tp is the phase-shift time, and to = td − tp is the overlaptime. Then, based on the above two requirements, the timeintervals of the switching transient must satisfy the followingrules:

a. If the initial value of i′2 is negative, then [t0, t2] shouldbe sufficiently long to make i′2 reach zero. In the calculation,the time interval [t0, t1] is neglected, and assume the cur-rent changes linearly during [t1, t2], then the minimum tp issolved:

tp,min = −Lr · i′2(T/2)

udcl + u′dc2

, for i′2(T/2) < 0 · · · · · · · · · · · (12)

b. [t4, t6] should be sufficiently long to make i′2 reachzero. Here, since the current at the beginning of t4 is low,the interval [t4, t5] cannot be neglected, so firstly this intervalneeds to be calculated. By assuming the current charging anddischarging the parasitic capacitance is equal to the magne-tizing current, the time length and the variation of the currentis acquired:

t45 = t5 − t4 = −Cs1

(udcl + u′dc2

)iLm(0)

· · · · · · · · · · · · · · · (13)

Δi′2,45 = −t45

(udc1 + u′dc2

)Lr

· · · · · · · · · · · · · · · · · · · · · · (14)

Then, according to the sign of i′2(T/2), the minimum value ofto is acquired:

t0,min = t45 −Lr

(i′2(T/2) + Δi′2,45

)udcl + u′dc2

, i′2(T/2) > 0

· · · · · · · · · · · · · · · · · · · (15)

t0,min = t45 −Lr

[(uc1 + u′dc2

) √C′s2/Lr + Δi′2,45]

udcl + u′dc2

,

for i′2(T/2) < 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (16)

c. If P < 0, [t7, t8] should be short enough so at t = t8

there still has i′2 < 0. In other words, the maximum value ofto is limited by:

t0,max =π

2

√Cs2Lx +

(udc1 + u′dc2

) √Cs2/Lr

di′2(T/2)/dt,

fordi′2(T/2)

dt> 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · (17)

Furthermore, rules d-e are preferred to be satisfied:d. [t3, t4] should be as short as possible to shorten the

transient process.e. The times tp and to should be close to rule a and b, e.g.,

in 100 ns, otherwise the lossy diodes will be conducting for along time.

By applying rules a-e, the feasible boundaries of dead-timeand phase-shift can be determined. As an example, the rangeof tp and to versus f s for the prototype converter (Table 1)at full power conditions are calculated, and the results areplotted in Fig. 8. The feasible range of tp and to is highlydependent to f s and P, but still it is possible to introduce asegmented function to determine a proper set of tp and to.



5. Experiment Verification

A CLLC converter prototype is built, as shown in Fig. 9,with parameters given in Table 1. The experimental wave-forms of u1, u2 and i2 are shown in Fig. 10, which clearlyshow that under the proposed SR scheme, the low-voltageside current i2 is reset to zero after every switching transient,and consequently the reactive part of the current is signif-icantly suppressed. The typical switching transient wave-forms are provided in Fig. 11, where tp and to are equal. Theresult shows consistency to the theoretical analysis in sectionII and the key waveforms in Fig. 3.

Furthermore, a set of constant-load, variable-f s experi-ments under constant udc1 = 520 V condition were imple-mented, where udc2 was measured, as plotted in Fig. 12. Theresult generally is observed in the experimental result, which

(a) P = +1 kW

(b) P = −1 kW

Fig. 8. Feasible phase-shift time tp and overlap time toof the prototype converter. Solid color area: preferredrange; shaded area: acceptable range; dotted line: one ofthe feasible tp and to versus fs segmented functions

Fig. 9. Prototype of CLLC resonant converter

is mainly caused by the voltage drop on MOSFETs and theinductor resistance. Moreover, there is a significant andimportant difference of the output-voltage characteristic be-tween the two SR schemes: under the traditional scheme, udc2

can hardly reach the nominal 70 V value in all cases. Thereason is that the source of im differs under f s > f r and f s <

(a) proposed SR, P = +1 kW, f s = 50 kHz

(b) conventional SR, P = +1 kW, f s = 50 kHz

(c) proposed SR, P = −1 kW, f s = 60 kHz

(d) conventional SR, P = −1 kW, f s = 60 kHz

Fig. 10. Experimental waveforms of conventional andproposed SR scheme. Cyan line: u1; blue line: u2; ma-genta line: i2

Fig. 11. Detail of the switching transient



Fig. 12. Experiment result of output voltage udc2 versusswitching frequency f s

Fig. 13. Experiment result of efficiency versus switch-ing frequency

f r conditions, leading to different f s-udc2 characteristic with alimit of udc2 reached near f s = f r. The proposed scheme, how-ever, has a unified f s-udc2 characteristic due to the constantsource of magnetizing current, and consequently achievingan extended range of udc2, so the nominal output voltage canbe achieved in all cases.

The measured efficiency versus switching frequency isplotted in Fig. 13. Furthermore, the efficiency-output voltageplot is presented in Fig. 14. In practical experimental imple-mentation, we use different constant resistors as the load. Thevariation of “Approx. Power” is within 50 W which is rela-tively small and should not have big influence on efficiencycomparison. For the measurement in Fig. 13 and Fig. 14, weuse a multimeter to measure the voltage and current. Theaccuracy of the multimeter is 0.01 V and 0.01A. For the ex-perimental prototype, the value of the input and output ca-pacitors are large enough. So that the ripple of both currentand voltage is small and should not have a big influence onefficiency. As a result, We just measure the DC componentof the voltage and current and then calculate the efficiency.The figures indicate that at the same switching frequency andpower, the proposed SR scheme achieves higher efficiencydue to the reduced reactive current on the low voltage side.Consequently, given the same output voltage and power, theproposed SR scheme can generally achieve higher efficiency

Fig. 14. Experiment result of efficiency versus outputvoltage

than the traditional SR scheme.

6. Conclusion

This paper has proposed a new SR scheme for bi-directional high-step-down CLLC converters. Utilizing thetransient of a small phase shift between the full-bridges,this scheme successfully keeps the magnetizing current be-ing constantly provided from the high voltage side and thusreduces conduction loss of the low voltage side. The principleof the switching transient has been analyzed and further veri-fied by experiments. The steady-state voltage gain of the con-verter is generally consistent under different load and powerdirection, and thus it is possible to tune the output voltage tonominal value under bi-directional conditions. Still, the out-put voltage range is narrower than CLLC converters withoutSR, and the transient process is highly dependent to the cir-cuit parameters, including the non-linear output capacitanceof MOSFETs, bringing complexity to the selection of dead-time and phase shift.

AcknowledgmentThis work was supported in part by the National Natural

Science Foundation of China under Grants 51877117, and inpart by State Key Lab of Power Systems, Tsinghua Univer-sity (SKLD18M06).

References

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Kai Sun (Non-member) received the B.E., M.E., and Ph.D. degrees inelectrical engineering from Tsinghua University, Bei-jing, China, in 2000, 2002, and 2006, respectively.He joined the faculty of Electrical Engineering, Ts-inghua University, in 2006, where he is currently anAssociate Professor. From Sep 2009 to Aug 2010,he was a Visiting Scholar at Department of EnergyTechnology, Aalborg University, Aalborg, Denmark.From Jan to Aug 2017, he was a Visiting Professor atDepartment of Electrical and Computer Engineering,

University of Alberta, Edmonton, Canada. His current research interests in-clude power electronics for renewable generation systems, microgrids, andenergy internet. Dr. Sun serves as the Chair of IEEE Power Electronics Soci-ety (PELS) Beijing Chapter, and leads the IEEE PELS DC Microgrids Tech-nical Thrust. Dr. Sun serves as an Associate Editor for IEEE Transactionson Power Electronics, IEEE Journal of Emerging and Selected Topics inPower Electronics, and Journal of Power Electronics. Dr. Sun served as theTPC Vice Chair of IEEE ECCE2017 and IEEE ECCE-Asia2017. He alsoserved as the General Co-Chair of 2018 International Future Energy Chal-lenge (IFEC2018). He was a recipient of Delta Young Scholar Award in2013, and Youth Award of China Power Supply Society (CPSS) in 2017.

Yucheng Gao (Non-member) received the B.E. and M.S. degrees inelectrical engineering from Tsinghua University, Bei-jing, China, in 2014 and 2016, respectively. He iscurrently pursuing the Ph.D. degree in University ofColorado Boulder, Boulder, CO, USA. His current re-search interests include automotive power electron-ics, rectifier systems, and magnetic optimization.

Huan Chen (Non-member) received the B.E., M.E. degree in elec-trical engineering from Tsinghua University, Beijing,China, in 2018. He is now a Ph.D. student of Elec-trical Engineering, Tsinghua University. His researchinterest is isolated bidirectional DC/DC converter.


bi-directional high-conversion-ratio cllc resonant

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