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Copyright © 2003 Altera Corporation
SOPC arkkitehtuuritja suunnitteluvuo
SOPC arkkitehtuuritja suunnitteluvuo
2Copyright © 2003 Altera Corporation
HighlightsHighlightsFounded in 1983$839 Million in 2001 Sales1,875 Employees14,000+ Customers Worldwide
3Copyright © 2003 Altera Corporation
The Programmable Solutions CompanyThe Programmable Solutions Company
High-Density CMOSProgrammable Logic
Devices
Intellectual Property Development Software
4Copyright © 2003 Altera Corporation
Altera Product PositioningAltera Product Positioning
LowCost
CPLDs GeneralPurpose
FPGAs withEmbedded
Transceivers
FPGAs withEmbeddedProcessors
5Copyright © 2003 Altera Corporation
Altera OfficesAltera Offices
6Copyright © 2003 Altera Corporation
All New Product Portfolio (0.13-um)All New Product Portfolio (0.13-um)
Up to Twenty 3.125-Gbps Transceivers per Device
Second-Generation FPGA Family with Embedded Transceivers
Based on the Stratix™ Architecture
Dynamic Phase Alignment Implemented in Dedicated Silicon
Highest Density FPGA in Production Today
Up to 10 Mbits of TriMatrix™ Memory
DSP: High-Speed Digital SignalProcessing Blocks
PLL: Advanced Clock Management Circuitry
DDR: External Memory Interface Circuitry
Industry’s Lowest Cost FPGA Family
Designed for Low Cost from the Ground Up
4X the Density of Previous Low-Cost Architectures
Designed Based on Customer Requirements
7Copyright © 2003 Altera Corporation
EP2A40
EP1M350EP1M120
EP2A25EP2A15EP20K100CEP20K600CEP20K400CEP20K200C
Status0.15-um Copper
EP1SGX25EP1C12EP1C20EP1C6EP1S80EP1S40EP1S30EP1S25EP1S20EP1S10EP2A70
Status0.13-um Copper
All-Layer Copper ExperienceAll-Layer Copper Experience
Engineering Sample Availability
Production Availability
8Copyright © 2003 Altera Corporation
Fixed Costs for SoC / ASICFixed Costs for SoC / ASIC
NRE CostsNRE Costs
50100150200250300350400450500
$K
1998 1999 2000 2001
NRE Cost− $500K+
Fab Write Off− $2Bn+ over 3 years
9Copyright © 2003 Altera Corporation
Wafer Foundry ExampleWafer Foundry Example
E F G H I
CustomerA
CustomerB
CustomerC
CustomerD
®
PLD Model
One mask set serves 1,000s of customers in 1,000s of applicationsNo separate mask charges (NRE)No minimum order quantity
CustomerA
CustomerB
CustomerC
CustomerD
ASICModel
Unique mask set neededper customer per designHigh mask chargesHigh minimum order quantities
Copyright © 2003 Altera Corporation
Managing Time-to-Market Is Critical
22--Year Year Product Life CycleProduct Life Cycle
Volume
Time
Price
Copyright © 2003 Altera Corporation
Managing Time-to-Market Is Critical
3-Month Delay-34%
Potential Revenue
Life-CycleRevenue
Two year lifeTwo year life--cycle products lose 34% of potential cycle products lose 34% of potential revenue and 50% of profit if they are 3 months laterevenue and 50% of profit if they are 3 months late
Source: McKinseySource: McKinsey
12Copyright © 2003 Altera Corporation
Design Flows Are Simple Now…
BehavioralSimulation
Performance Analysis
Bit-Stream
VHDLVerilog
HardwareTiming
Design Flows Are Simple Now…
Synthesis, Place & Route
TestBench
13Copyright © 2003 Altera Corporation
…But Not for Long
BehavioralSimulation
TestBench
Hardware & Software
Linker
Software Timing
HardwareTiming
Performance Analysis
Bit-Stream
…But Not for LongSystem Construction
Physical Synthesis,
Place & RouteVHDL
Verilog
Software IP
Object Code
RTOS Support C/C++
Compile & Link
DSP Tools
System Synthesis Architecture
System Level
Design Language
Hardware IP
14Copyright © 2003 Altera Corporation
PLD = Programmable Logic DeviceCPLD = Complex Programmable Logic DeviceFPGA = Field Programmable Gate ArraySOPC = System On Programmable ChipLE = Logic ElementLUT = Look-Up TableHard Core = Embedded CPU on siliconSoft Core = Embedded CPU implemented with
FPGA.
TermsTerms
Copyright © 2003 Altera Corporation
SOPC solutionsSOPC solutions
16Copyright © 2003 Altera Corporation
Complexity – Transistors over TimeComplexity – Transistors over Time
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1984 1986 1988 1990 1992 1994 1996 1998 2000 2002Year
No.
of T
rans
isto
rs
Intel Altera
1985: PLD transistor count one order of magnitude behind leading microprocessor
2002: PLD (EP1S80)~5x transistor count of latest
Pentium 4
17Copyright © 2003 Altera Corporation
Price TrendPrice Trend
0.354
0.578
0.901
1
0.261
0.0860.1320.1440.17
0
0.2
0.4
0.6
0.8
1
1.2
1993 1994
Price
per
LE
Sold
(Nor
mali
zed
to Q
1 199
3)
Price per Logic Element (LE)Driven Lower Each Year
0.069 0.055 0.046 0.042 0.0190.037 0.031 0.0230.029
20021995 1996 1997 1998 1999 2000 2001
18Copyright © 2003 Altera Corporation
PLD EvolutionPLD Evolution1996:
100k-gate 0.5µm EPF10K100 is the PLD state-of-the-artAn 8-bit 8051 core fills it and runs at 5 MHz
$200 per processor MHz
2001:1.5M-gate 0.18µm EP20K1500E in volume productionA 32-bit Nios processor takes 2% of its capacity and runs at 50MHz
$0.33 per processor MHz
19Copyright © 2003 Altera Corporation
Excalibur Approach to SOPCExcalibur Approach to SOPCRISC processors targeted for programmable logic− Hard & soft
System configuration tools to automate SOPC designStandard, off-the-shelf devicesAffordable & widely accessible
EmbeddedProcessor Memory
Logic
20Copyright © 2003 Altera Corporation
Embedded Processor SolutionsEmbedded Processor Solutions
Embedded Processors Provide Flexibility& Horsepower for Broad Market Coverage
ARM®
CoreARM®
Core
Performance(MIPS)
20
50
100
200
®®
0 Soft Core Hard Core
Copyright © 2003 Altera Corporation
SOPC Excalibur ARMSOPC Excalibur ARM
22Copyright © 2003 Altera Corporation
ARM-Based Excalibur DeviceARM-Based Excalibur DeviceProcessor
Support LogicDebugging
LogicARM922T Stripe− Hard Logic
200 MHz 210 DMIPS
Programmable Logic− 100K Gates to 1M Gates
Three Devices inFamily
All Available
Today
All Available
Today
ARM922TProcessor
Core
Dual-PortRAM
Single-PortRAM
23Copyright © 2003 Altera Corporation
The Altera Excalibur ApproachThe Altera Excalibur ApproachIndustry’s First Embedded Processor PLD Solutions
PLD
PLD
PLD
128 KbytesDPRAM
256 KbytesSRAM
EPXA1038,400 LEs (1,000,000 Gates)327 Kbits RAM
16,640 LEs (400,000 Gates)212 Kbits RAM
EPXA4
64 KbytesDPRAM
128 KbytesSRAMProcessor Subsystem
Interfaces & Debug LogicDPRAM
SRAM
ProcessorStripe
16 KbytesDPRAM
32 KbytesSRAM
4,160 LEs (100,000 Gates)53 Kbits RAM
EPXA1
24Copyright © 2003 Altera Corporation
Excalibur ARM ConfigurationExcalibur ARM ConfigurationSDRAM Flash ROM SRAM
WatchdogTimer
Phase-Locked
Loop (PLL)
AHB 1-2Bridge
Dual-Port SRAM
SDRAMController
Single--Port SRAM
ARM922T Processor
Interrupt Controller
AHB1
AHB2
ConfigurationLogic Master
Reset Module Timer
UARTExpansion Bus Interface (EBI)
Excalibur Hard Processor
External Devices
IP
PLD-to-StripeBridge
Programmable Logic Master
Peripheral
ProgrammableLogic SlavePeripheral
Stripe-to-PLDBridge
ProgrammableLogic SlavePeripheral
Programmable Logic Module
Programmable Logic
Module
FPGA Logic
ET
M9
ConfigurationRegister
AHB AHB
AHB: AMBA™ High-Performance Bus
25Copyright © 2003 Altera Corporation
Excalibur Work FlowExcalibur Work FlowPeripheral Pool
C Header Files
Peripheral Drivers
Configure System
Generate
User Peripherals
Verilog / VHDL Files
SOPC Builder
Native Core / Gnu Developer Suite
User Design
Other IP
User Code
Libraries
RTOS
Software
Quartus™ Software
ExcaliburSolution
Debugger &Trace Analyzer
ExecutableConfiguration
Trace JTAG
Hardware
26Copyright © 2003 Altera Corporation
EPXA1 Development KitEPXA1 Development KitExcalibur EPXA1 development board Smart LCD module Power supply Connection cables SOPC Builder GNUPro Toolkit Documentation Quartus® II Web Edition design softwareSoftware, drivers, and application examples on CD-ROM
27Copyright © 2003 Altera Corporation
EPXA10 DDR Development KitEPXA10 DDR Development KitEPXA10 DDR development board Quartus® II Kit Edition (a time-limited version of the Quartus II software) with SOPC Builder and GNUProToolkit Software, drivers, and application examples on CD-ROMPower supply Connection cables Documentation
Copyright © 2003 Altera Corporation
SOPC Excalibur NiosSOPC Excalibur Nios
29Copyright © 2003 Altera Corporation
Nios Embedded ProcessorNios Embedded ProcessorConfigurable Soft-Core Embedded ProcessorOptimized for Altera®
FPGA Architecture16-Bit Instruction Set RISC Architecture− 16- & 32-Bit Data Path
License & Royalty Free− ASIC License Available
Industry’s Most Popular Soft-Core Processor
30Copyright © 2003 Altera Corporation
CMP 2002 Embedded Brand StudyCMP 2002 Embedded Brand StudyNios Processor Makes It onto Embedded Map in 2002− Nios Is the Only Configurable CPU on the List
Planned Usage Grows 4x for 2003Motorola 16-Bit Microcontrollers
Embedded x86 (16 Bit)
Infineon (Siemens) C16x
Microchip PIC
Hitachi H8 Series
ARM Thumb Family
TI MSP 430
Altera Nios (16 Bit*)
28%23%
25%18%
8%9%
6%11%
5%6%
4%4%
3%9%
1%4%
Current Usage
Planned Usage
31Copyright © 2003 Altera Corporation
Standard RISC ComponentsOptimized for Size & Performance in PLDs Fully Synchronous Interface
Nios Processor Block DiagramNios Processor Block Diagram
OperandFetch &Store
InstructionFetch &Decode
ProgramCounter
General-PurposeRegister File
InterruptControl
MUX
ClockEnable
6
ALU
Read/WriteByte EnableData OutInstruction
Address
IRQ: Interrupt RequestALU: Arithmetic Logic Unit
16Instruction
inData Address
Data InClock
IRQWait
IRQ NumberReset
32Copyright © 2003 Altera Corporation
Custom InstructionCustom InstructionOptional FIFO, Memory, Other Logic
Dramatic Boost in Processing Performance− No Increase in fMAX
Extends Nios Instruction Set− Up to Five Instructions
SOPC Builder Development Tool− Automatically Adds User
Logic to Nios ALU
− Assigns Op-Code
− Generates C & Assembly Macros
Nios Processor
YourCustomLogic
33Copyright © 2003 Altera Corporation
Nios Processor SystemsNios Processor SystemsComplete Microprocessor Subsystem− Processor Core
− Memory Interfaces
− Peripherals
− Custom Logic
− JTAG-Based On-Chip Debug Logic
Avalon™ Switch Fabric − Connects All Components
Multiprocessor SystemsPossible
CustomLogic
NiosYour DesignHere
Ava
lon
Switc
h Fa
bric
UART
PIO
Timer
SPI
SDRAMController
On-ChipROM
On-ChipRAM
PIO: Parallel I/OSPI: Serial Peripheral Interface
Nios
Nios
NiosCPUDebug
Cac
he
34Copyright © 2003 Altera Corporation
Peripheral ComponentsPeripheral ComponentsMemory Interface− On-Chip
RAM, ROM
− Off-ChipSDRAM ControllerSSRAMSRAMFlash, ROM
− On-Chip Instruction & Data Cache
DMA Controller− Memory-Peripheral− Memory-Memory− Peripheral-Peripheral
Bridges− AHB to Avalon Bridge
Parallel I/O (PIO) Registers − General-Purpose I/O Registers (PIO)
InputOutputBidirectional
− User-Defined Interface
Serial Interface − UART− SPI
Timer− Simple Timer− Pulse Generator− Watchdog Timer
Included in Nios Development Kit!
35Copyright © 2003 Altera Corporation
Design Example: Size & SpeedDesign Example: Size & Speed
382,119313,042ACEX® 1K
442,151433,035APEX 20KE
542,124533,022APEX 20KC
592,144553,046APEX II
1101,9801042,574Cyclone
1162,2421112,941Stratix
ffMAXMAX (MHz)(MHz)LEsLEsffMAXMAX (MHz)(MHz)LEsLEs
Standard 16Standard 16--Bit Bit Reference DesignReference Design
Standard 32Standard 32--Bit Bit Reference DesignReference Design
Device FamilyDevice Family
Copyright © 2003 Altera Corporation
SOPC BuilderSOPC Builder
37Copyright © 2003 Altera Corporation
SOPC Builder FlowSOPC Builder FlowSOPC Builder GUI
Connect Blocks
Processor Library Custom Instructions
Peripheral Library Select & Configure Peripherals, IP
IP Modules
Configure Processor
C Header files
Custom Library
Peripheral Drivers
C/C++ Compiler
Software Development
User Code
Libraries
RTOS
Generate
EDIF Netlist
HDL Source Files
Testbench
Synthesis &Fitter
User Design
Other IP Blocks
Hardware Development
Quartus II
On-ChipDebug
Software TraceHard Breakpoints
SignalTap II
AlteraPLD
JTAG,Serial, orEthernet
ExecutableCode
HardwareConfiguration
File Verification& Debug
38Copyright © 2003 Altera Corporation
Pool of “SOPC Builder Ready” Components − Communications− DSP− Bus Interfaces− Bridges− Processors
Nios & ARM ProcessorsWeb-Based IP Deployment
Customization - Just What You NeedCustomization - Just What You Need
39Copyright © 2003 Altera Corporation
Table of Active ComponentsConfigure Each Component− Interrupt
Request (IRQ)− Base Address− Hardware
Parameters− Software
ParametersWizard-Based Configuration
Customization - The Way You Want ItCustomization - The Way You Want It
40Copyright © 2003 Altera Corporation
IntegrationIntegrationBus Connection Patch PanelAvalon Switch Fabric− Slave-Side
Arbitration− Optimized for
ThroughputBus Bridging− AMBA™ Advanced
High-Performance Bus (AHB)
− PCI− More to Follow . . .
41Copyright © 2003 Altera Corporation
SOPC Builder Ready ComponentsSOPC Builder Ready Components
NiosProcessor
ARM922TProcessor
ARM-to-Nios Bridge (AMBA AHB-to-Avalon)
On-Chip ROMOn-Chip RAM
16550S UARTWatchdog10/100 Ethernet
FLASHCAN 2.0TimerInterface to User Logic
SRAMSPIGPIO
SSRAMUSB 2.0PCI
SDRAMUSB 1.1DMA
33 IP Cores Now . . .The List Keeps Growing
42Copyright © 2003 Altera Corporation
Nios OS / RTOS / Software SupportNios OS / RTOS / Software Support
Small-Footprint, Royalty-Free, POSIX-Compliant RTOS
KROSShugyo Design
Generates C/C++ Code from Graphical State Machine Model
visualSTATEIAR Systems
µITRON 4.0-Compatible Real-Time KernelNORTiMiSPO Co., Ltd.
Royalty-Free, Preemptive RTOSµC/OS-IIMicriµm
Open-Source OSµClinuxMicrotronix
Royalty-Free, Source-Available RTOSNucleus PlusAccelerated Technology
DescriptionDescriptionProductProductProviderProvider
43Copyright © 2003 Altera Corporation
Nios Development Board,Cyclone EditionNios Development Board,Cyclone Edition
44Copyright © 2003 Altera Corporation
Linux Development KitLinux Development Kit
Nios LinuxDevelopment Kit$2,495Available Now
Visit Microtronixwww.microtronix.com
Open-Source Linux Operating System− µCLinux Kernel v2.4.x & Source− Embedded Libraries & Source
SOPC Builder Operating System Component − GUI-Based Linux Kernel Configuration− Builds Custom a Kernel Based on Nios
CPU Configuration in SOPC BuilderComplete Hardware & Software for Embedded Linux Development− µClinux Source Code− Daughter Cards for Linux Development
OS Support Daughter BoardSDRAM/Flash Memory ModuleEthernet Development Kit
− Reference DesignsVarious Linux Kits & Services Available− Evaluation Kit Starting at $495
For Use with Nios Development Kit, APEX Edition (EXCALIBUR-NIOS)
Copyright © 2003 Altera Corporation
Thank You!Thank You!For More Details Please Visit the
www.altera.com/literature/lit-nio.htmlwww.altera.com/literature/lit-exc.htmlwww.altera.com/products/devkitswww.altera.com/ipmegastore