DATASHEET

ALLEGRO PACKAGE DESIGNER 610/620

Cadence® Allegro® Package Designer 610 and Allegro Package Designer 620—600

series products within the Allegro system interconnect design platform take IC

package and IC package co-design to the next level. They combine new chip-level

co-design capabilities for I/O feasibility planning with industry-leading IC package

design tools to deliver a co-design methodology for Cadence First Encounter®.

An embedded 3D field solver also enables full package-level simulation models

that can help PCB designer design-in new devices faster and more accurately.

The Allegro system interconnect design platform

IC packagedesign

PCB design

I/O bufferdesign IC design

Packagedesign-in kit

Silicondesign-in kit

On-target, on-timesystem interconnectInterconnect

models

I/O bufferIP

Virtual systeminterconnect

model

Verify

Build

Correlate

Specify

Explore

Design

Implement

THE ALLEGRO SYSTEMINTERCONNECT DESIGNPLATFORMThe Cadence Allegro systeminterconnect design platformenables collaborative design of high-performance interconnect across IC,package, and PCB domains. Theplatform’s unique co-designmethodology optimizes systeminterconnect—between I/O buffersand across ICs, packages, and PCBs—to eliminate hardware re-spins,decrease costs, and reduce designcycles. The Allegro constraint-drivenflow offers advanced capabilities fordesign capture, signal integrity, andphysical implementation. With silicondesign-in kits, IC companies shortennew device adoption time and systemscompanies accelerate PCB design cyclesfor rapid time to profit. Supported bythe Cadence Encounter™ and Virtuoso®

platforms, the Allegro co-designmethodology ensures effective designchain collaboration.

2

SEAMLESS CO-DESIGN FLOWBETWEEN IC AND PACKAGE The existing serial design methodologybetween IC and package design canno longer meet the cost, performanceand time-to-market pressures oftoday’s complex, leading-edge devices.Electrical and physical feasibilitystudies and chip/package design trade-offs must take place early in thedesign phase, before implementationdecisions are made and optionsbecome limited. During this stageit is crucial to consider the impactof physical design choices on theelectrical performance of the IC, andvice versa. Once the chip design hasprogressed to the point at whichdriver optimization can no longertake place, the burden falls on thepackage designer to meet therequirements, which may not alwaysbe possible. Enabling a true co-designmethodology, through the use andexchange of IC abstracts, allowsdesigners to make simultaneousphysical and electrical design trade-offs to ensure that the IC meets itsperformance and cost objectives inthe shortest time possible.

ALLEGRO PACKAGEDESIGNER 610Allegro Package Designer 610 —a 600 series product within the Allegrosystem interconnect design platform—provides a unique IC packagingdesign environment. Allegro PackageDesigner 610 is a complete constraint-driven physical design solution targetedat single fixed/static die designs.It supports all packaging methods,including PGA, BGA, micro-BGA,chip scale using both flip-chip andwirebond die attach methods. Itsimplifies and speeds the designprocess-from direct data entry fromIC tools to full documentation withautomatic design features.

COMPREHENSIVE, CONSTRAINT-DRIVEN PHYSICAL LAYOUT

Allegro Package Designer 610 includesall the functionality and featuresyou need to design today’s advancedpackages. It supports all packagingmethods, including PGA, BGA, micro-BGA, chip scale, as well as flip-chipand wirebond attach methods. Fullonline design-rule checking supportsthe complex, unique requirements ofall combinations of laminate, ceramic,and deposited substrate technologies.Multiple cavities, complex shapes,and interactive and automaticwirebonding are all supported. Theeasy-to-use Design Wizard withinAllegro Package Designer 610 walksyou through each task and automatesthe process of creating the buildingblocks of an IC/package, such as thecreation of die, package, plating bars,and power/ground rings. The die andBGA wizards automate definition ofthese library elements with yourchoice of text file standard formats(such as D.I.E., Excel, and AIF2), or aform-driven user interface, such asthe BGA Wizard.

SOPHISTICATED SUBSTRATEMODELING AND RULE CHECKING

A key advantage of Allegro PackageDesigner 610 is its ability to verifydesign accuracy against a complete setof physical and electrical design rules(constraints). Physical constraints arephysical design guidelines, establishedin a user-defined technology file, thatensure manufacturability. Electricalconstraints are signal delay anddistortion specifications for criticalnets. Allegro Package Designer 610dynamically checks the design againstthese constraints throughout thedesign process to ensure the design ismeeting manufacturing and electricalspecifications, and it providesimmediate feedback to the designerby way of DRC markers.

DESIGN REUSE FOR INCREASEDEFFICIENCIES

Allegro Package Designer 610 capturesboth substrate stack-up and constraintinformation in a technology file,which can then be reused for otherdesigns of similar structure, further

reducing cycle time on future designs.Substrate suppliers can providetechfiles that will typically containcritical design rules to help drive acorrect design methodology. Multipletechfiles can be used from differentsuppliers to assure manufacturabilityat secondary suppliers.

TOOL FLEXIBILITY FOR WIREBONDFINGER AND FLIP-CHIP ESCAPEPATTERNS

If the design uses wirebondinterconnects, the bond fingerpatterns will vary from in-line or inlineradial to multi-tiered, arc-basedpatterns, depending on packagetechnology and density of chip I/Os.Stacked-die configurations mayrequire the interweaving of bondfingers, resulting in extremely complexpatterns. Allegro Package Designer610 can automatically create theappropriate pattern based on specific,user-defined constraints. These mayinclude:

• Bond finger dimension

• Bond finger, wire, and route spacing

• Minimum and maximum wire lengthand crossing rules

• Maximum bond wire angle (onlyfor radial)

• Number of rows in stagger or shelves,if applicable

New wirebonding capability delivers arobust set of wirebond rules and enhancedfeatures to address the unique requirementsfor stacked die

3

Alternatively, Allegro PackageDesigner 610 can automaticallycalculate the best pattern based onmore general design criteria. Oncecreated, design requirements maydictate that these patterns bemodified. For this, Allegro PackageDesigner 610 provides you with apowerful wirebond editingenvironment that offers greatflexibility in modifying the patternswhile still adhering to the establisheddesign rules. For flip-chip technology,Allegro Package Designer 610 providesa robust set of tools to assist the userin creating the complex routing escapepatterns found in today’s high-densityinterconnect (HDI) designs. HDI ormicro-via technology dictate thatthese complex via escape patternsbe specifically constructed to meetmanufacturing requirements. AllegroPackage Designer 610 includes bothautomatic and semi-automatic tools tohelp speed up this process. Theautomatic tools quickly create allcombinations of blind and buried viapatterns that are then available in alibrary. A semi-automatic complex viastructure tool provides a mechanismfor creating the intricate via and routeescape patterns often found in HDIdesigns, and quickly propagates themaround the die.

AUTO AND MANUAL OPTIMIZATIONOF CHIP-TO-PACKAGE INTERCONNECTSPROVIDE FLEXIBILITY READINGNETLISTS IN MULTIPLE FORMATS

The “netlist-less” design philosophyavailable in Allegro Package Designer610 lets you optimize the chip-to-package interconnect without apredefined netlist. If routabilityand delay drive chip-to-packageconnectivity, use automatic andinteractive assignment utilities toachieve optimal results. The interactiveassignment utility allows you to createnew nets, assign specific pins, deletepins, or delete nets. If a plating barexists, you can also build the packageI/O to plating bar connectivity. If anetlist does exist, you don’t have toworry about its format. The netlistText Wizard reads virtually any ASCIIfile. Allegro Package Designer 610

can import AIF2 or LEF/DEF files aswell. If you need to distribute powerand ground through “rings,” usethe power/ground Ring Wizard togenerate the conductor shapeautomatically. If you’ve created yourdie flag in another tool such asAutoCAD, then you can use the DXFinterface to import the geometry.Once in Allegro Package Designer 610,you can then assign the propervoltage to the die flag.

Spideroute offers 45-degree or trueany-angle routing and routabilityanalysis that is ideal for wirebondattach substrates.

ALLEGRO PCB ROUTER 610 ANDSPIDERROUTE FOR INTERACTIVE ORAUTOMATIC RULES-BASED ROUTING

The most important and timeconsuming step in any design isrouting. By their very nature, complexIC packages are a routing challenge.Whether it’s an all-angle, single-layer,wirebonded design with a plating bar,or a flipchip on a multilayer build-upsubstrate, each technology presents itsown unique set of challenges. AllegroPackage Designer 610 overcomes thisproblem by providing the designerwith a toolbox of routing functionality—from interactive to automatic. Fordynamic interactive routing, AllegroPackage Designer 610 has the mostpowerful set of interactive routingtools available today. Allegro PackageDesigner 610 enables fast and accuraterouting of any type of IC packagedesign—from all-anglewirebonded toorthogonal flip-chip. Any electrically

constrained nets, such as those withcontrolled impedance and matcheddelay, are easily routed to thoseconstraints with dynamic feedbackwhen rule violations occur. Two newfeatures in Allegro Package Designer610 are tandem differential pair routingand the ability to dynamically plow/healthrough power and ground planes.In addition to the interactive tools,Allegro Package Designer 610 alsoprovides automatic routing capabilityand includes two routers: AllegroPCB Router 610 and SpiderRoute.Depending on the interconnecttechnology of your design—wirebondor flip-chip-you can choose whichrouter is more appropriate. Formultilayer flip-chip designs, whichtypically have a large amount ofelectrically constrained nets, AllegroPCB Router 610 is a powerful shapebased router that can manage thesecomplex design challenges. For all-angle, wirebonded designs, whichcan be extremely dense and require adifferent set of routing algorithms,SpiderRoute is the right choice.SpiderRoute is a schedule-based routerthat evaluates available routingchannels and optimizes routing basedon spacing rules. SpiderRouteautomatically creates and sendsorthogonal routes out to theplating bar.

Complex HDI breakout via patternscan be defined, stored and re-used asarray patterns.

Spideroute offers 45-degree or true any-angle routing and routability analysis thatis ideal for wirebond attach substrates.

Complex HDI breakout via patterns can bedefined, stored and re-used as array patterns

4

REAL-TIME ANALYSIS ENSURESELECTRICAL INTEGRITY

Beyond innovative packaging androuting facilities, what really setsAllegro Package Designer 610 apart isits ability to ensure electrical integrityby performing real-time analysis. Youcan do this in two ways:

• Dynamic RLC displays line parasiticdata in real time as you enter traces,reflecting resistance, inductance, andcapacitance

• Check the design against electricaldesign constraints for crosstalkthresholds, delay, and line impedance

EXTENSIVE MANUFACTURINGOUTPUT CAPABILITIESThis total solution’s philosophydemands as much attention to outputsas to internal capabilities. Allegro

Package Designer 610 can generate allthe types of manufacturing data likelyto be required—from documentationto tooling. You can easily create bonddiagrams, dimension documents,format drawings, and various outputfiles containing critical package data.Manufacturing output supportsGerber 4X00 and 6X00 series, 274X,Barco, DXF, AIF2, and GDSII.

Many of today’s foundries alreadyuse Allegro Package Designer 610.This means you can send an Allegrodesign database to the foundrydirectly as manufacturing input, greatlycompressing throughput times andpreempting potential inaccuracies.The foundry can use the database toenhance manufacturing yields andimplement any last-minute changes tothe package without inadvertentlycompromising the originalspecifications. (Contact your foundryto confirm their specific capabilities.)

PCB SYSTEM-LEVEL HAND-OFF

Allegro Package Designer 610 not onlybridges the gap between silicon andpackage design but also links packageand circuit board design, automaticallygenerating all data required for PCB-level floorplanning and layout:

• Physical footprint

• Schematic symbol

• Device models in SPICE, IBIS, orAllegro PCB SI format

These capabilities compress set-uptime and increase data accuracy forsystems designers.

ADDITIONAL FEATURES

Allegro Package Designer 610 is trulya total packaging solution, addressingthe full design flow from end-to-end.Additional features include:

• Integration with silicon design

• Full UNIX/Windows interoperability

• Free web-downloadable viewer

• Special routing for “dog-bone” fanoutvias, with or without tangent fillet, forboth chip and package

• “Auto smoothing” of traces to anyangle, diagonal, or arc

• Dynamic pad filleting

• Online, dynamic RLC parasiticcalculation

• Design reuse features for utilizingprior designs with new ICs

• GDSII, DXF, Gerber, and IDFbi-directional data transfer

• Full database compatibility withAllegro Package Designer 620 andAllegro Package SI 620

ALLEGRO PACKAGEDESIGNER 620Allegro Package Designer 620 buildson the solid fixed-die substrate designfoundation established by AllegroPackage Designer 610 and extendspackage design to include IC/Packageco-design. The 620 product also comeswith an embedded 3D modelgeneration engine that allows

designers to extract a full packagemodel that can then be used forpost-layout verification in theAllegro Package SI 620 simulationenvironment.

Allegro Package Designer 620 providesnew chip-level I/O planning capabilities,it contains functionalities targeted atstreamlining the ECO flow between ICand package design. Based on theLEF/DEF or OpenAccess 2.2 protocols—the standard formats for IC dataexchange—Allegro Package Designer620 includes a robust set of import/export capabilities, enabling IC andpackage designers to send die abstractchanges back and forth robustly inorder to reduce design time and realizean optimized IC die pad-ring/bumpmatrix and package substrate.

BENEFITS• Die abstract and package substrate

co-design reduces package complexityand optimizes substrate performanceand cost

• Robust bi-directional die-abstract ECOexchange with Encounter platform viaLEF/DEF and OA2.2

• Allows users to determine bestpackage and substrate technologyearly in the IC design cycle

IC die abstracts can be imported into theI/O Feasibility Planner for substrate-leveloptimization of the bump matrix, orcreated from scratch and handed off tothe IC design team

5

• Enables users to create accurate 3Dpackage models for system levelsimulation

• Supports a full package-driven designflow, from design capture throughmanufacturing output, with all theindustry standards

FEATURES

NEW DIE ABSTRACT EDITOR

• Main package substrate editor spawnsDIE Abstract I/O Feasibility Plannerwhen a co-design die needs to beedited, imported or created.

• I/O Feasibility Planner providesIC/Package co-design through itsability to create or import & edit ICdie abstracts (as LEF/DEF or OA2.2)that contain IO padring definition,die bump matrix and IO to bumpconnectivity assignment.

• Allows the user to establish variablebump matrices tied to unique gridsacross the die surface—designers cancreate unique grids, including pitch-free grids, for areas such as corepower/ground and mixed signal

• Provides a set of bump matrix editingcapabilities that enable designers toadd, move, swap, delete, and modifybumps to achieve an optimized bumppattern.This is especially helpful formeeting timing requirements orescape routing

• Offers a completely new set of pinnumbering schemes and controls thatcan cover virtually any numbering

scheme designers want to use,including user-defined prefixes orJEDEC labeling

• Supports new tiling features

• Spreadsheet-based I/O placementand sequencing environment providesan easy methodology for themanipulation of I/O sequencing toenable chip/package trade-offs duringthe package feasibility stage

• Connectivity assignment between thedie abstract and package can bedisplayed in the spreadsheet for analternate view of the data with theability to sort/view/manipulate cellssimilar to other spreadsheets

• The import/export capability enableseasy transfer of data between existingexternal spreadsheets and theimbedded spreadsheet

• An automatic driver-to-bumpassignment capability finds the nearestroutable match, which can be sentback to the IC tools for final routing

• Die-level redistribution layer (RDL)route feasibility offers a first-ordervalidation of drive-bump assignmentviability

• Hierarchical re-usable bump matrixtiling allows the designer to create alibrary of pre-defined bump patterns

• Customized tiles can contain user-specified signal/reference patterns

• Tiles can contain package routingescape patterns from under the die

EMBEDDED ELECTRICAL CIRCUITMODEL GENERATOR

• Includes a proven easy-to-use 3D fieldsolver for full package model creation

• Allows 3D models to be used for post-layout system interconnect verificationwith Allegro Package SI 620 or AllegroPCB SI 630

DIE EDITOR

• Quickly generates die and packagefor feasibility studies

• Utilizes both silicon and packagetechnology files to create accuratedie and packages

• Eliminates the need for packagingexpertise during initial feasibilitystudies

Spreadsheet driven I/O sequencing/placement provides rapid feasibilityoptimization

Embedded 3D field solver quickly generatesaccurate full package simulation models

6

AUTOMATIC BUMP-TO-PACKAGE PINASSIGNMENT

• Utilizes router-based algorithms thatdetermine best routable assignmentbased on existing design rules

• Identifies differential pair-definedbumps and assigns adjacent packagepins accordingly

OTHER FEATURES

• The robust bi-directional LEF/DEFinterface includes a new LEF librarymanager

• Die-level abstractcomparison/verification to ensure thatpackage and IC tools are synchronized

• Substrate-level footprintcomparison/verification to ensurethat package and foundry designsare synchronized

• Net delay reports, which calculatethe delay on a net-by-net basisand generate a report of the entirepackage, can be invoked at thefeasibility phase for a rough estimateor after design completion forverification

OPERATING SYSTEMSUPPORT

• Red Hat Linux 7.3, 8.0, RHEL 3.0

• Windows 2000 with Service Pack 4, XPProfessional

• Sun Solaris 8, 9

• HP-UX 11.0, 11.11i

• IBM AIX 5.1

CADENCE SERVICES ANDSUPPORT

• Cadence application engineers can answeryour technical questions by telephone,email, or Internet—they can also providetechnical assistance and custom training

• Cadence certified instructors teach over70 courses and bring their real-worldexperience into the classroom

• Over 25 Internet Learning Series (iLS)online courses allow you the flexibility oftraining at your own computer via theInternet

• SourceLink® online customer support givesyou answers to your technical questions—24 hours a day, 7 days a week—includingthe latest in quarterly software rollups,product change release information,technical documentation, solutions,software updates, and more

FOR MORE INFORMATIONContact Cadence sales at 1.800.746.6223or visit www.cadence.com for additionalinformation. To locate a Cadence salesoffice or value-added reseller (VAR) in yourarea, visit www.cadence.com/contact_us.

Wizard driven die editor provides rapidcreation of bump matrices and substrate ballmatrices for fast what-if feasibility studies

7

610 620

ALLEGRO PACKAGE SUBSTRATE EDITOR FEATURESNetlist / Crossplace / Crossprobe with Allegro Design Entry (HDL or CIS) X XPadstack & Symbol Editor X XCustomizable / Automated Drill Legend X XMultiple Via Sizes, Blind / Buried Via Support X XDefine, store and re-use complex via structures X XAutoplacement / Quickplace Floorplanner X XDynamic Shapes with Real-Time Plowing & Healing for Copper Areas X XAutomatic Line Smoothing X X2-D Drafting and Dimensioning X XGerber 274X, 274D, GDSII Artwork Output Generation X XMultiple UNDO / REDO X XValor ODB++, ODB++(X) File Output & Universal Viewer X XHTML-based Custom Reports X XStroke Editor X XIntelliUSE Interactive Trace Editing X XAutomatic Silkscreen Generation X XSplit Plane Support X XSKILL Runtime, Macro, and Script Support X XAgilent EEsof™ Integration X XCAD Interfaces - DXF (Ver. 14), IDF (Ver. 2 & 3) X XEDA Interfaces - PADS® (Ver. 4 & 6), PowerPCB® (Ver. 5), P-CAD® (Ver. 8) X XAIF import/export for die & package shell X XLength, Parallelism, and Differential Pairs Rule Support X XPin-pair Multi/Matched Nested Group Support X XReal-Time DRC and Routing of Differential Pairs & Length Rules X XInteractive Delay Tuning X XComplex Physical Design Rule Checking (No Electrical) X XGroup Routing X XMeasure Parasitic X XAdvanced Trace Glossing X XDatabase-driven Design Reuse Modules X XTechnology Files X XDesign For Assembly Rule Checking X XTestPrep for Testability Access X XReal-Time DRC of Delay and Crosstalk Rules X XConstraint Areas and Technology File Support X XAutomatic Line Width Adjustment for Impedance Rules X XeXtended Net Support (x-nets) X XLayer Set Rules & Routing Support X XDelay, Crosstalk, and Impedance Routing Support X XAllegro Constraint Manager (Routing, SI & Timing Constraints & DRC Worksheets) X XZ-Axis Delay Support X XExtended Timing Path Support X XGroup Routing (Space Control) X XDifferential Pair (Dynamic Phase Control) X XAdvanced automatic wirebonding (creation & editing) X XAuto create, assign and derive nets X XAuto assign pin use properties X XDie generator X XDie text-in wizard X XBGA generator X XBGA text-in wizard X XLEF library manager X XOffset via generator X XNetlist-in wizard X XDEF bump matrix import X XSubstrate-level reusable tile generator XCreate plating bars X XCreate bondpad soldermask X XCreate wirebond power and ground rings X X

ALLEGRO PACKAGE DESIGNER 600 SERIES COMPARISON GRID (SPB 15.5)

8

610 620

IO FEASIBILITY PLANNER FEATURE SUMMARY FOR PACKAGE DESIGNER 600 SERIESSeparate IO Feasibility Planner editor for co-design XImport die abstract as DEF or OA2.2 from FE XExport die abstract as DEF or OA2.2 to FE XIO cell placement spreadsheet XRDL trial router XLEF layer mapping XIC die level reusable tile generator X

610 620

ALLEGRO PACKAGE ROUTER FEATURE SUMMARY FOR PACKAGE DESIGNER 600 SERIES256 Signal Layer Limit Router Auto/Interactive X XShape-based or grid Autorouting X XSMD Fanout to Vias X XTrace Width by Net and Net Classes X XStaggered Pin Support X X45-degree ECO Routing X XMemory Pattern Routing (SMD or Through-hole) X XInteractive Via Search X XInteractive Routing with Shoving and Plowing X XInteractive Floorplanning X XAutoplacement X XOnline Design Rule Checking X XFlip, Rotate, Align, Push, and Move Components X XPlacement Density Analysis X XLayer Set Rules & Routing Support X XSignals on Specific Layers X XWidth and Clearance Rules by Layer X XVia Rules by Net and / or Net Class X XNet and / or Net Class Rules by Layer X XCrosstalk Violation Report X XTrace Length Violation Report X XBlind and Buried Via Support X XVia Under SMD Pad Checking X XAutomatic Wire Bonding X XPlural Vias Router X XStacked Vias X XEnhanced Via Fanout X XAutomatic Trace Spreading X XAutomatic Via Reduction X XAutomatic Miter 90 to 45 X XAutomatic Test Point Generation X XTest Point Specific Clearance Rules X XMinimum, Maximum, and Matched Length Rules X XCrosstalk Controls on Same and Adjacent Layers X XVirtual Pins, Which can be Moved During Autorouting X XParallelism Controlled by Length and Gap X XDifferential Pair Routing X XAutomatic Net Shielding X XDesign Rules by Area X XOnline Display of Length Tolerance X XGlobal Violation Indicator X XDynamic Display of Available Length X XAutomatic Single Net Routing X XMultiple Net / Bus Routing X XRelative Delay Rules X XZ-Axis Delay Support (Package Editor Integration Only) X XExtended Timing Path Support (PCB Editor Integration Only) PCB Performance x X XPin-pair Multi/Matched Nested Group Support (Package Editor Integration Only) X X

ALLEGRO PACKAGE DESIGNER 600 SERIES COMPARISON GRID (SPB 15.5)

© 2005 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, NC-Verilog, OrCAD, SourceLink,Verilog, and Virtuoso are registered trademarks, and Encounter is a trademark of Cadence Design Systems, Inc. All others areproperties of their respective holders.

4430E 06/05