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Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8

Cadence SPB: What’s New in 16.6 QIR 8 (HotFix 38)

This document describes the new features and enhancements in Cadence® SPB products in 16.6 Quarterly Incremental Release (QIR) 8- HotFix38. The products covered are:

■ Allegro PCB Editor

■ Cadence SiP Layout and Allegro Package Designer (APD)

■ Allegro Design Entry HDL

■ Allegro FPGA System Planner

■ OrCAD Capture

■ Cadence PSpice

© 2014 Cadence, Allegro, OrCAD, and PSpice are registered trademarks of Cadence Design Systems, Inc. in the United States and/or other jurisdictions.

October 2012 17 Product Version 16.6

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Allegro PCB Editor

Allegro PCB Editor

This document describes the new features and enhancements in Allegro® PCB Editor16.6 QIR 8.

■ Route Interconnect Optimization on page 19

■ Productivity Enhancements on page 35

■ Add Arc Prototype on page 42

■ RF PCB Enhancements on page 44



Route Interconnect Optimization

A major effort targeted at improving the productivity and efficiency aspects of the interactive routing environment continues throughout the 16.6 Incremental releases. The suite of commands below require enabling of the Design Planning product option.

■ Auto Connect on page 20

■ Create Flow on page 23

■ Trim to Breakout, Delete Breakout, and Compress Route on page 27



Auto Connect

New “Out of the box” auto-interactive technology is designed to accelerate the routing process with the user in full control. Simply select a group of rats, then make layer setting adjustments. High quality results that compare to “hand-routed” efforts are produced in a fraction of time it takes to route the same signals interactively.

Steps

1. Invoke Auto Connect from the Route – Unsupported Prototypes menu



2. Review the layer settings in the Options Panel and decide whether to use the Ripup Existing etch option.

3. Select one or a group of rat lines (may also select clines or bundles)



4. High Quality results produced by underlying auto-routing engine.



Create Flow

Create Flow is a new command that easily allows you to draw a guided route path (similar to drawing etch) and automatically route the connections using AiBT or Auto Connect. A persistent bundle is created for the rats using the layering and path from Create Flow. Create Flow can be used on rats, clines, or existing bundles. This feature allows you to easily re-flow and auto-route an existing bus.

Steps

1. Make sure you are in the Flow Planning application mode

2. Select a group of rats, right-click, and choose Create Flow from the pop-up menu.



3. Set the options correctly as shown

a. Select layer(s)

b. Consider selecting Auto-blank other rats to improve efficiency

c. Select Auto Connect

d. Consider selecting Compress option to pack clines if routing groups/lanes



e. Manually draw a route flow path from source to destination.



4. Right-click and choose Done to invoke the Auto Connect command. The connections will be auto-routed and compressed to the min DRC gap.



Trim to Breakout, Delete Breakout, and Compress Route

The new Trim to Breakout, Delete Breakout, and Compress commands provide additional capabilities to deliver a complete environment for multi-stage routing. This collection of features gives you the ability to manipulate, change, or re-route the individual breakout or trunk of existing bus routing. These features are exposed through bundle based commands. These new capabilities and use models provide an efficiency gain for you over tradition manual routing methods.

■ Commands available for multi-stage routing

❑ Existing commands from QIR7: Auto-I Breakout Both Ends, Auto-I Breakout Closest End, Auto-I Trunk Route

❑ New Prototypes in QIR8 (all commands are currently bundle based)

❍ Trim to Breakout – New command that removes the trunk routing of a bus; also trims or extends existing dangling breakout etch.

❍ Delete Breakout – New command to remove breakout routing from one side of existing bus routing.

❍ Compress Route – New command to compress existing trunk routing of a bus to min DRC gap

The ends (gather points) of a bundle defines where the Breakout and Trunk routing are separated. When moving a gather point of a bundle, a dynamic line is drawn that shows where the breakout and trunk separation occurs.

Trim to Breakout




2. Select an existing bundle on a fully routed bus, right-click, and choose Auto-I Trim to Breakout from the pop-up menu.



The ‘trunk’ routing will now be deleted. This allows you to quickly modify the remaining breakout routing sections, move a component, or change the path of the bundle and invoke Auto-I Trunk Route to auto route following the new path.



Trim to Breakout may also be used to extend or trim existing breakout routing. Below is a picture where one bundle has been moved closer to the component and the breakout was trimmed, and the other bundle was moved farther from the component and the breakout routing was extended.



Delete Breakout


2. Select an existing bundle on a fully routed bus, right-click, and choose Auto-I Delete Breakout from the pop-up menu.

The breakout routing from the closest end of the bus will be deleted (relative to where the command was invoked). Removing the breakout allows you to easily generate an



alternate breakout solution or to move the component and then reconnect the bus using Auto-interactive routing commands.



Compress Route


2. Select an existing bundle on a fully routed bus, right-click, and choose Auto-I Compress Route from the pop-up menu.

Note: If the bus was originally routed by hand, quickly create a bundle for the existing routing to allow invoking the Compress Route command.



The routing will be compressed to min Spacing DRC value. The routing will be compress towards the center of the existing clines selected.



Productivity Enhancements

Min AirGap

The Min AirGap command is available from the Display – Unsupported Prototype menu. It currently exists in the SiP product and based on its popularity, it has been made available to PCB customers. Use Min AirGap to check for minimum gap across the entire path of two adjacent clines.



New Drafting Commands

New drafting commands are now available within all Allegro PCB Editor products from the Manufacture menu. They are also available in General Edit application mode when hovering over the applicable objects and right-clicking.

Extend Segments

This command allows you to extend line and arc segments to a projected intersection point. When invoked from the menu, you are prompted to Select object to extend. After an object is selected, you are prompted to specify another object with which the first object should



intersect. Once the second object is selected, the two objects are temporarily extended and highlighted to show the possible intersection points.

Trim Segments

This command allows you to remove portions of line and arc segments that extend beyond specified intersection points. When invoked from the menu, you are prompted to Select object to trim. After an object is selected, you are prompted to select another object intersecting the first. At this point, you are prompted to Select side of segment(s) to trim, after which one or both objects can be trimmed by making successive picks on either object to one or the other side of the intersection point.

Delete by Line

This command allows you to remove the portion of lines, arcs, and segments lying on one side of a user-specified cut line. When invoked from the menu, you are prompted to Select object(s) to cut, after which you are prompted to Specify start point of cut line, and subsequently, after a start point is selected, Specify end point of cut line. Once you specify two points on the canvas, you are again prompted to Select the side to remove. When you next specify a point on the canvas, all of the selected objects on the same side of the cut line as that point are removed.



Note: Note that if a segment is selected, the cut extends only to the end of that segment. If a line/cline is selected, the cut extends across segments to the end of the line.

Delete by Rectangle

This command allows you to remove the portion of lines, arcs, segments, and vias lying within a user-specified cut rectangle. When invoked from the menu, you are prompted to Select object(s) to cut, after which you are prompted to Specify start point of cut rectangle, and subsequently, after a start point is selected, Specify end point of cut rectangle. Once you specify two points on the canvas, the portions of the preselected objects lying within the cut rectangle are removed.

Offset Copy

This command allows you to make multiple copies of a variety of objects offset from the original(s) by a specific X and/or Y value. When invoked from the menu, the Options pane is updated to provide fields for entering X and Y offset values, the number of repetitions to perform, and width/font values that can be applied to any line objects created, and you are



prompted to Select the element(s) to copy. Once you select objects, copies are created offset from the original location by the values presently specified in the Options pane.

Offset Move

This command allows you to move a variety of objects by a specific X and/or Y offset. When invoked from the menu, the Options pane is updated to provide fields for entering X and Y offset values, and you are prompted to Select element(s) to move. Once you select objects they are moved from their current location by the offset presently specified in the Options pane.

Add Perpendicular Line

This command allows you to add a line perpendicular to another line already in the design. When invoked from the menu, you are prompted to Specify reference object of start point. After a pick is made, a rubber band line appears, with the reference object or start point as its first end point, and you are prompted to specify either the end point or reference object. Once another pick is made, a line is added perpendicular to the reference object and extending from that object to the start/end point.

Add Parallel Line

This command facilitates the creation of lines parallel to existing lines. When invoked from the menu, you are prompted to Select object(s) to add parallel line(s). After one or more objects are selected, you are prompted to specify a side of the selected line(s) to guide where



new lines are to be created. The offset of the new line(s) from the original is determined by the Offset field in the Options pane, and the number of copies to be created is controlled by the Repetitions field in the same form. Once a side is chosen, one or more lines are created parallel to the reference object. At this point the command can continue by adding more lines or finish on choosing Done/Cancel from the pop-up menu.

Add Tangent Line

This command allows you to add one or more lines tangent to existing circles or arcs. When invoked from the menu, you are prompted to Select first tangent object. After a pick is made, you are prompted to Select *the+ second tangent object. Once this second object is picked, temporary lines are inserted representing all possible tangent lines between the two objects and you are prompted to Select tangent line(s). At this point you can click on one or more of the possible tangents, thus selecting those lines for insertion in to the database. When satisfied, finish by choosing Done/Cancel from the pop-up menu.

Relative Copy

This command allows you to make copies of a variety of objects mirrored from the original(s) relative to a line. When invoked from the menu, the Options pane in the mini-status area is updated to provide a Relative Mode field that controls the line around which the copies should be mirrored, and you are prompted to Select object(s) to copy. Horizontal Line or Vertical Line indicates that the mirror line will be fixed as such, whereas Odd Line provides for mirror lines at other angles.

Once objects are selected, you are prompted for an origin point. Once this is provided, the potential object copies become dynamically visible in the canvas, and you are asked to make one further pick to establish the actual point for the new objects, at which time the copies are created. At this point the command can continue by copying more objects or finish on choosing Done/Cancel from the pop-up menu.

The Odd Line option operates in one of two modes providing rotation options analogous to the spin command, with the rotation angle field controlling what angles are permissible. (0 implies any angle, whereas other values imply rotations only in multiples of that value.) When the rotation type is incremental, spinning the mirror line updates the rotation applied to the target objects, whereas absolute means that only the actual value in the rotation angle field will be applied relative to the mirror line.

Relative Move

This command allows you to move a variety of objects mirrored from the original location relative to a line. When invoked from the menu, the Options pane in the mini-status area is updated to provide a Relative Mode field that controls the line around which the objects



should be moved, and you are prompted to Select object(s) to move. Horizontal Line or Vertical Line indicates that the relative line will be fixed as such, whereas Odd Line provides for relative lines at other angles.

Once objects are selected, you are prompted for an origin point. Once this is provided, the potential object copies become dynamically visible in the canvas, and you are asked to make one further pick to establish the actual point for the new location. At this point the command can continue by moving more objects or finish on choosing Done/Cancel from the pop-up menu.

The Odd Line option operates in one of two modes providing rotation options analogous to the spin command, with the rotation angle field controlling what angles are permissible. (0 implies any angle, whereas other values imply rotations only in multiples of that value.) When the rotation type is incremental, spinning the mirror line updates the rotation applied to the target objects, whereas absolute means that only the actual value in the rotation angle field will be applied relative to the mirror line.

Connection Lines

This command facilitates the creation of lines to connect existing lines. When invoked from the menu, you are prompted to Select first object to connect. After a pick is made, you are prompted to Select the second object to connect. Once this second object is picked, temporary lines are inserted representing all possible connect lines between the two objects and you are prompted to Select connect line. At this point, you can click on the possible line, thus selecting it for insertion in to the database. When satisfied, you can finish by choosing Done/Cancel from the po-up menu.



Add Arc Prototype

An enhanced add arc command prototype is now available within all Allegro PCB Editor products, as long as Hide All Unsupported Prototypes in Setup – User Preferences is not checked. The command appears under Add – Unsupported Prototypes. When the command is invoked, the Options pane of the mini-status area offers the user a variety of ways to specify the parameters of the arc being created. In each case, you make a series of three picks on the graphics canvas which describe the characteristics of the arc. In several cases, dynamics are employed to the effect of possible picks.

■ Start, Center, End - Pick 1 identifies the start of the arc, pick 2 the center, and pick 3 the end.

■ Start, Center, Angle - Pick 1 identifies the start of the arc, pick 2 the center, and pick 3 the angle between the start-to-center and center-to-end line segments.

■ Start, Center, Length - Pick 1 identifies the start of the arc, pick 2 the center, and pick 3 the length of the arc.

■ Start, End, Angle -Pick 1 identifies the start of the arc, pick 2 the end, and pick 3 the angle between the start-to-center and center-to-end line segments.

■ Start, End, Direction - Pick 1 identifies the start of the arc, pick 2 the end. In addition, pick 2 is also interpreted as the start point, and pick 3 as the end point of a line tangent to the arc being created.

■ Start, End, Radius - Pick 1 identifies the start of the arc, pick 2 the end, and pick 3 the radius if the arc being created.



■ Center, Start, End - Pick 1 identifies the center of the arc, pick 2 the start, and pick 3 the end.

■ Center, Start, Angle - Pick 1 identifies the center of the arc, pick 2 the start, and pick 3 the angle between the start-to-center and center-to-end line segments.

■ Center, Start, Length - Pick 1 identifies the center of the arc, pick 2 the start, and pick 3 the length of the arc.

For angle options, the Lock angle field provides the opportunity explicitly to specify particular angle values, while the Lock length field provides the same capability for lengths. Width and font characteristics of the new arc can also be controlled by Line width and Line font fields, which operate in the same manner in numerous other Allegro commands. Active class and subclass controls are also provided, again in accordance with general Allegro practice.



RF PCB Enhancements

In this release, following enhancements have been made in autoplace command in RF PCB:

Autoplace Enhancements

■ Canvas Selection Support for Net Exclusion

■ Interactive Repackaging Support

■ New Icon to Indicate Out-of-Sync Symbol

Canvas Selection Support for Net Exclusion

A new RMB menu Set Net Exception has been added to pick nets from the design canvas for exclusion in autoplace process.



Interactive Repackaging Support

In QIR 8, autoplace command has enhanced to support snapping to pad edge during interactive repackage process. Snapping to pad edge is enabled if Enable snap to pad edge is checked.

For more information, see Interactive Repackaging or Autoplacement with Snap to Pad Edge in Allegro User Guide: Working with RF PCB.

New Icon to Indicate Out-of-Sync Symbol

For the components and groups that have inconsistent parameters and are out-of-sync with their placed symbols the icon is now displayed in blue color.


../rfpcbug/chap2.html#save_settings

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Cadence SiP Layout and Allegro Package Designer (APD)

Cadence SiP Layout and Allegro Package Designer (APD)

This section describes the new features and enhancements in Cadence® SiP Layout and Allegro® Package Designer (APD) 16.6 QIR 8.

■ Ignoring Same Net Objects While Voiding on page 47

■ Generating Clines with Rounded Outside Corners on page 48

■ Checking Solder Mask on Fingers with No Wire on page 49

■ New Advanced Package Router Tutorial and Video on page 49

Note: The new features listed for Allegro PCB Editor on page 18 are also available from Cadence SiP Layout and Allegro Package Designer (APD).



Ignoring Same Net Objects While Voiding

The void adjacent layer shapes command generates manual voids around objects of all kinds in shapes on specified layers; for example, to ensure that a high-speed signal has no interference from nearby power nets, or you might want to reserve space in that shape for future routing.

By default, voids are created in any shape within the specified distance of the selected objects. Use the new Create voids in shapes on same net option to specify that voids should not be created in the shape if it is on the same net as the selected item. This option is selected by default.



Generating Clines with Rounded Outside Corners

You can now select the Round outside corners at vertices option in the Stream Out dialog box (Manufacture – Stream Out) to ensure rounded outside corners of bends in the clines to match the display and DRC checking done in the main layout.

This option is available only if Output all clines as boundaries is selected. Not selected by default.



Checking Solder Mask on Fingers with No Wire

You can now check bond fingers opening in solder mask with no wire bonds attached to them. Set the ADRC_SM_UNWIRED_FGRS environment variable and run the rule Wire Substrate End On Finger To Solder Mask Edge Gap.

Note that the Wire Substrate End On Finger To Solder Mask Edge Gap rule itself has not changed. With the variable set, the rule will check if a finger with no wire is fully exposed in solder mask. If the finger is fully or partially covered, DRC marker will be created. The marker will show a constraint Minimum Bond Wire Substrate End on Bondfinger To Merged Soldermask Spacing on the marker, but the constraint value will be 0.

New Advanced Package Router Tutorial and Video

A new tutorial, Advanced Package Router Tutorial, is now available that uses a flip-chip, single die design to walk you through the various steps to route a design using Advanced Package Router. The tutorial has a design database that you can use to try out the routing steps. The tutorial also contains a multimedia demonstration or video that shows the various steps performed in the tutorial.

This tutorial can work as quick reference for the routing steps and pre-configuration of constraints as well as to understand the interfaces.

Note: You can open the tutorial from Cadence Help or look it up in Cadence Online Support.


http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=aprTut/aprTut16.6/aprTutTOC.html

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Allegro Design Entry HDL

Allegro Design Entry HDL

This section describes the new features and enhancements in Allegro® Design Entry HDL 16.6 QIR 8.

■ Port Groups on page 50

■ Variant Operations in Design Entry HDL on page 50

■ Replace Component Validation in Variant Editor on page 51

Port Groups

Starting with this release, Design Entry HDL provides support for port groups. A port group is an interface port on a hierarchical symbol that corresponds to a net group used in the lower-level schematic. Using port groups, connections to net group members can be created at a higher level of the hierarchy, thus further speeding up the task of capturing connectivity.

For more details, see the Cadence document Working With Net Groups and Port Groups.

Variant Operations in Design Entry HDL

Variant-related tasks such as creating, editing, and deleting variants, marking components to variants, replacing components in a variant can now be performed in Design Entry HDL itself. In the schematic canvas, using the Variants menu and toolbar, you can switch from the base schematic view to the variant view. When you select a variant, only variant-specific information is displayed on the schematic canvas.

The Variants menu command, corresponding to the Variant tool bar, which was earlier under the View menu in the schematic canvas is now a main menu named Variants.

For more information, see the Managing Variants in Design Entry HDL section in Allegro Design Entry HDL User Guide.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Allegro Design Entry HDL

Replace Component Validation in Variant Editor

When you now replace a component in Variant Editor or in the schematic variant view, Variant Editor checks whether the two components—the component that is being replaced and the component that will replace the selected component—have the same or compatible footprints, that is, JEDEC_TYPE properties. If the footprints are not compatible, a warning message is displayed. For more information, see the Replacing Components section in Design Variance User Guide.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Allegro FPGA System Planner

Allegro FPGA System Planner

This section describes the new features and enhancements in Allegro® FPGA System Planner16.6 QIR 8.

■ New Device Support on page 53

■ Archiving FSP Project on page 53

■ Adding Text (Notes) on page 54

■ Enabling and Disabling Symbol Generation Process on page 54

■ Interleaving Bus Allocation on page 54

■ Support for Hierarchical Split Symbols on page 56

■ Enhanced Import Allegro Wizard on page 56

■ Additional Enhancements on page 56



New Device Support

This section describes new devices that are added in the current release.

Archiving FSP Project

You can now save a project (.fsp) and all the related files (design, library, and output files) in a different directory and also create a archive file of the directory. You can either use the ArchiveProject TCL command or choose File – Archive Project to archive a project.

Name Description

Stratix V GS

5SGSMD5K3F40I3N

5SGSED6K3F40I3N

-

Virtex UltraScale Virtex® UltraScale FPGAs provide the highest system capacity, bandwidth, and performance.

UltraScale devices offer both High-performance (HP) and high-range (HR) IO banks. The HP IO banks supports high-speed memory with voltages up to 1.8 v, while the HR IO banks supports a wider range of I/O standards with voltages up to 3.3v. UltraScale devices also manage simple clocking requirements with dedicated global clocks distributed on clock routing.

Note: The Virtex UltraScale parts are early release parts and are partially qualified.



Adding Text (Notes)

In the current release, you can now add text (notes) to the Canvas by using Add Design Notes from the Canvas toolbar.

Enabling and Disabling Symbol Generation Process

In the current release, you can customize the usage of symbols. You can either restrict to use the symbols from central library or use the FSP generated symbols. To restrict the symbol usage, you can enable or disable the DE-HDL symbol generation process. To hide all the symbol generation options, add the is_allow_symbol_generation variable in the config.ini file.

Interleaving Bus Allocation

In the current release, a new bus allocation, interleaving is introduced to support interleaving bus connection at the die level.

The following example demonstrates how the interleaving allocation works.



Consider you select the buses, read[0:4] and write[0:4] for interleaving allocation. When you run the design, FSP allocates the bus signals as shown in the following figure.



Support for Hierarchical Split Symbols

In the current release, when doing Engineering Change order (ECO), you can retain splits of FSP or FPGA hierarchical blocks that were created using the hierarchical split symbols (HSS) feature in DE-HDL. Open the FSP generated schematic in DE-HDL and split the blocks using HSS. After splitting, it is recommended that you do not instantiate the split blocks in DE-HDL. To retain the split blocks, close DE-HDL and regenerate schematics with the Preserve Schematic option unchecked in FSP. Open DE-HDL and note that the split blocks are instantiated.

Enhanced Import Allegro Wizard

In the current release, the Import Allegro Wizard is enhanced to support connectivity import from a board. When you import components, you can use the existing rules or symbol files to specify the mapping information for the extracted component. In case you do not specify or have rules or a mapping file, the wizard creates a dummy rules file based on the component symbol and DRA file.

For detailed information about the columns, fields, and options of Import Allegro Wizard, click Help. When you click Help, a pane appears at the right side of the page.

Additional Enhancements

Significant enhancements have been made in the following sections:

■ Various fonts are appended to the list of the Font Settings section in Preferences.

■ A new shortcut toolbar is introduced in the Design Connectivity Window. Use this toolbar to work faster and perform certain operations that are relevant to the selected rows, such as device row, bank row, interface row, group row, or pin row in the Design Connectivity window. You can access this toolbar by clicking the rows. The toolbar buttons may vary based on the rows you select in the Design Connectivity window.

■ You can now see the available and total I/Os of a device instance in number and percentage (<Available I /O pins/Total I/O Pins>) in the Properties window.

■ You can now hide a column in the Design Connectivity Window. Right-click on the header of a column and select Hide Column.

■ You can now edit an interface part (RTF file), even if the part is not linked to the symbol and DRA files. Right-click and choose Rules – Edit Rules to edit the interface part.



■ In the current release, updating hierarchical pages of FPGA using the Update FPGA Hierarchical Page option is no longer supported. It is recommended to generate complete schematics.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8OrCAD Capture

OrCAD Capture

This section describes the new features and enhancements in OrCAD® Capture 16.6 QIR 8.

■ New Book in Learning PSpice on page 59

■ Enhancements in PSpice Component Menu on page 61

■ Setting Character Limit Across Projects on page 63

■ Option to Disable Autobackup on page 64



New Book in Learning PSpice

A new book, Analyses Using PSpice, has been added in Learning PSpice. This book contains the following chapters:

■ Introduction

■ Transient Analysis

■ AC Analysis

Introduction

This chapter covers the basic steps of PSpice simulation with a simple example.



Transient Analysis

This chapter covers transient analysis of a simple RC circuit and plots the voltage and the current across a capacitor using PSpice.

AC Analysis

This chapter covers AC analysis of a simple RC circuit to determine the nodal voltage and the current across a capacitor. It also covers the following:

■ AC sweep of an RC circuit

■ Bode Plot function of the Plot Window Templates to determine the gain and phase

■ Noise analysis to determine total voltage spectral density.

Note: You can access Learning PSpice only in the Capture-PSpice flow. To access Learning PSpice, choose Help — Learning PSpice in Capture.



Enhancements in PSpice Component Menu

Light-Emitting Diode (LED)

A new option, LED, is now available from the PSpice Component menu. Using LED, you can model the light-emitting diode (LED) forward characteristics at ambient temperature. Model a LED using this application using typical forward characteristics as input, some of which are following:

■ reverse leakage current

■ breakdown voltage

■ maximum power dissipation

■ forward current



Noise Sources

A new type of Independent Sources, Noise Sources, is now available in the Independent Sources window. You can calculate the following type of noises using Noise Independent Sources:

■ Voltage and Current Noise Sources

❑ DC Noise

❑ Sine Noise

❑ Pulse Noise

❑ Exponential Noise

❑ Random Noise



Note: To access LED, choose Place — PSpice Component — Modeling Application — LED. To access Noise source in Independent Sources, choose Place — PSpice Component — Source — Independent Sources.

Setting Character Limit Across Projects

A new option has been added in the Extended Preferences Setup window to save the character limit in the INI file instead of a project. The new option is listed under Netlist groups and can be accessed from Accessories — Cadence Tcl/Tk Utilities — Utilities — Tcl/Tk Applications Dashboard — Extended Preferences.

Alternatively, you can use the following TCL command to save the character limit in the INI file:

SetOptionString "AllegroCharLimitInINI" "TRUE"



Option to Disable Autobackup

You can now disable the Autobackup INI option using the following TCL command:

SetOptionString "DisableAutobackup" "TRUE"


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Cadence PSpice

Cadence PSpice

This section describes the new features and enhancements in Cadence® PSpice® 16.6 QIR 8.

■ Enhancements in Learning PSpice on page 66

■ New Keyword for Iteration Count in Transient Analysis on page 66


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 8Cadence PSpice

Enhancements in Learning PSpice

A new book, Analyses Using PSpice, has been added in Learning PSpice. This book contains the following chapters:

■ Introduction

■ Transient Analysis

■ AC Analysis

Note: You can access Learning PSpice in the Capture - PSpice flow only. To access Learning PSpice, choose Help — Learning PSpice in Capture.

New Keyword for Iteration Count in Transient Analysis

A new keyword, that is , ITERCOUNT, has been added in PSpice. ITERCOUNT is the iteration count for each time step in the transient analysis. For example, you can add the iteration count as a trace in the probe data file using the following command:

.probe P(ITERCOUNT)


cadence spb: what’s new in 16.6 qir 8 (hotfix 38) · cadence spb: what's new in 16.6...

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