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Cadence SPB: What's New in 16.6-2015

Cadence SPB: What’s New in 16.6-2015 (HotFix 51)

This document describes the new features and enhancements in Cadence® SPB/OrCAD® products in 16.6-2015 (Hotfix 51). The products covered are:

■ Release-Level Changes

■ Allegro PCB Editor

■ Cadence SiP Layout and Allegro Package Designer (APD)

■ Allegro Constraint Manager

■ Virtuoso SiP Architect

■ Allegro Design Entry HDL

■ Allegro Part Developer

■ Allegro FPGA System Planner

■ OrCAD Capture

■ PSpice

■ Allegro Sigrity SI and PI

© 2015 Cadence, Allegro, Virtuoso, OrCAD, and PSpice are registered trademarks of Cadence Design Systems, Inc. in the United States and/or other jurisdictions.

June 2015 1 Product Version 16.6-2015

Cadence SPB: What's New in 16.6-2015Release-Level Changes

Release-Level Changes

This section describes the enhancements and new features in Cadence® SPB/OrCAD® Release 16.6-2015.

■ OrCAD Sigrity ERC

OrCAD Sigrity ERC

OrCAD® Sigrity™ ERC is a new product (PO3420) for electrical verification of OrCAD® PCB designs. It features a rich set of SI related Electrical and Simulated Rule Checks (ERCs and SRCs) based on proven Sigrity™ technology. Other core components include a layout editor for floorplanning and editing and Constraint Manager. The ERC – SRC module can be launched directly within the layout editor and simulation results can be identified and rectified in a side-by-side configuration with synchronized displays. Designs can be screened using any combination of geometry-based DRCs, SI-based ERCs, and SRCs without the need for device models. This allows for non-SI Engineers to reduce the need for SI simulation.


Cadence SPB: What's New in 16.6-2015Allegro PCB Editor

Allegro PCB Editor

This document describes the new features and enhancements in Allegro® PCB Editor Release 16.6-2015.

■ High Speed Interconnect Enhancements on page 4

■ Productivity Enhancements on page 11

■ Allegro Relational Rules Checker Starter Kit on page 22

■ Allegro PCB Designer Product Update on page 26

■ OrCAD PCB Designer Update on page 34

■ OrCAD Menu Restructuring on page 35

■ RF PCB Enhancements on page 38



High Speed Interconnect Enhancements

Differential Pair Return Path Vias (High Speed Product Option)

Return Path Vias, also referred to as Ground Reference Vias or Stitching Vias provide a current return path to minimize signal degradation in PCB and packaging interconnects during via transitions. Currents must always return to their source, so when a signal transfers from one layer to another using a via, the return current will return to source along the path of the least impedance.

Release 16.6-2015 includes support for return path vias when routing differential pair signals. Using the standard Add Connect command, a suite of six templates are available from the right-click pop-up menu. Once instantiated into the design, the combination of the signal and return vias are treated as a group, which implies that you can slide the group as a single entity. If action is needed at the via instance level, enable the single trace mode by toggling the Return Path Vias Group option.



Fiber Weave Effect – Zig-Zag Routing (High Speed Product Option)

The Add Zigzag Pattern feature provides interactive capability that converts orthogonal parallel traces to zigzag (off-angle) routes. This minimizes the effect of PCB fiberglass weave on the routing of high speed signals by forcing the traces to be out of alignment with the fiber weave. This feature supports both routed differential pair and single ended nets. You can now specify the required zigzag angle and maximum segment length, as well as the option to convert full segments or define start and end points.

Note: Access the Add Zig-Zag Pattern feature from the Route – Unsupported Prototype – Fiber Weave Effect menu.



Auto-Interactive Adjust Spacing (Design Planning Product Option)

Routing groups of signals can be trial and error when considering the impact of high-speed constraints imposed on the signal group. You often route at min line to line DRC to minimize real estate or at a more conservative gap to account for delay tuning or even to improve cross talk conditions. The existing manual methods to customize the line to line spacing of a signal group can be time consuming and experimental. In this release, a new method to quickly compress or expand line to line spacing is introduced.

The methodology for adjusting the line to line spacing of a signal group requires the presence of a flow bundle. Hover the mouse pointer over a bundle and right-click to access the Auto-I. Adjust Spacing command.

Enter a line to line gap value or select constraint to compress the routes to the min line to line DRC value. If unsatisfied with the results, hover over the bundle once more then enter a different gap value.



Strict Flow Adherence (Design Planning Product Option)

Planning your design with flow bundles allows you to work at a hierarchical level. In recent releases, several routing improvements have been made based on the flow bundle concept ranging from intelligent breakout, trunk routing, auto connect and route compression. In this release, the routing algorithm is tuned to strictly adhere to the path of the flow bundle.



Snake Router Update

The Snake Router is now integrated into the Add Connect command. As a result of this integration you no longer need to enter line width and gap as the command reads the native constraint data. Additional enhancements include:

■ Snake routing can resume from partially routed path

■ Natural line angle transition when routing into open space

■ Single line centering option

Auto-Interactive Swap Pins (Design Planning Product Option)

The Auto-interactive Swap Pins Closest End command provides the ability to automatically swap eligible bundle member pins to resolve or minimize crossing sequenced rat rakes, it provides a more optimized breakout routing solution on the closest end of cursor pick. You can only select sequenced bundle(s). The command is available as a right-click pop-up menu command when a bundle is selected.

To swap a bundle member, do the following:

■ Enter the Design Planning Application mode.

■ Generate a sequence on the bundle end that will drive the order of sequence for the opposite end with swappable pins. To generate the sequence, hover the mouse pointer over the bundle, position the cursor nearest to the bundle end that will be the sequence driver, right- click and choose Flow Edit – Sequence – Generate.



■ Hover the mouse pointer over the bundle and position the cursor near the bundle end with swappable pins. Right-click to access the applicable Auto-interactive routing options.

■ Choose the Auto-I. Swap Pins Closest End command to run.

Auto-Interactive Phase Tune/Delay Tune Update (High Speed Product Option)

Both AiPT and AiDT now support ARC based tuning bumps. To enable this behavior, select the Corner Type option Full Arc.



Timing Vision Update (High Speed Product Option)

Timing Vision now provides support to highlight differential pairs with dynamic phases issues. Use the Smart Phase option to stipple violating clines.



Productivity Enhancements

Shape Edit Application Mode

The Shape Edit Application mode is a tuned editing environment primarily designed to increase efficiency with shape boundary editing. It is available in all back-end PCB and Packaging products. This object-action environment simplifies the actions of sliding a shape edge, adding a notch or chamfering/rounding the corners. Note the similarities with existing application modes but also the new function that allows customization of single pick and drag operations.

Context Sensitive Pop-Up on Right-Click

Hovering the mouse pointer over a shape segment (edge) produces the following pop-up menu on right-click.

Toggle between elements

Use the TAB key to cycle between elements on your cursor. In the following example, hovering over the shape edge (left graphic) provides datatip information about the line segment. Press



the TAB key to cycle to the shape element (right graphic). Context-sensitive menus will vary based on the highlighted element.



Best Practices for Shape Editing

You can customize settings in the Options panel for mouse click, drag, and vertex operations. Based on the following settings, there is no need to access the main toolbar or top-level menus for basic shape boundary editing.



■ Two picks on a shape segment will result in the creation of an inward or outward notch based on your cursor movement.

■ Clicking while hovering over a shape segment invokes a slide operation.

■ Clicking while hovering over a vertex location performs a two segment move operation.

2 picks to add notch choose inward or outward direction



■ A single click on a vertex location results in a chamfered corner trimmed to10 mils (actual segment length = 14.14 mils)

■ To chamfer all corners, hover over a shape segment and then right-click to access the Trim corners command.

■ To convert a corner back to orthogonal, change the click setting to Remove/Extend, and then select the chamfered segment.



■ Alternatively, you can hover over the chamfered edge and from the right-click context menu choose the Remove/Extend command.

■ To round a corner, change the Corners setting to Round then select the vertex location.



■ To adjust a corner by mouse movement, enable the Set trim size by cursor option, and then move your mouse to control the chamfer or round size.

■ To slide a shape segment and its chamfered or rounded corners, enable the Extend Selection option, and then click or drag to perform the 3 element slide operation. (Similar use model is used with the etch edit slide function)



■ To join the edges of a multi-edge shape, enable the Auto-Join option then slide one of the segments.

■ To move and maintain the integrity of the multi-edge side of the shape, press the CONTROL key, then select the three vertical segments. Hover the mouse pointer over any one of the highlighted segments, then use the Move Segments command.

❑ Move segments is not linear; consider using the ix command to set a distance. For example, type ix 100 in the command window to move segments 100 mils to the right.

Refresh Symbol Update

Refresh symbol now offers an option to preserve the padstack names associated with pins in the design from being updated. When using the refresh_symbol batch program, you can



enable it with the –K option. This option is relevant if you routinely update padstacks for Backdrill requirements.

Persistent Snap and Selection

You can now maintain a specified snap and selection type throughout a PCB Editor session by enabling the – persistent – toggle option available in the context-sensitive menu on right-click of the respective commands.

Snap Pick to – Enable the Persistent snap option and then choose an element type. A check box will appear once the element is selected.



Selection Type – Select the Persistent snap menu option then select a selection type such as lasso or polygon.

Island Permanent Highlight

The Delete islands function, now includes a button in the Options panel to permanently highlight all shapes with no connections (island shapes), using the color set as Assign Color. It includes the ability to show island shapes so that you can connect them using methods, such as adding vias or connect lines. With dynamic shapes, this highlighting is removed if the shapes are updated.

Lower Shape Priority

This release has the ability to control voiding priority when shapes overlap. Earlier, voiding control was limited to ‘raise priority’ only. The following example shows lowering the priority



on the highlighted shape that results in the GND shape controlling the voiding around its boundary.

Clipboard Update

The Clipboard function now supports copying of dynamic shape instance overrides.

Default Gerber Zero Line Width

Undefined line width in the Artwork Control Form can now be seeded with values instead of zeros. Use the variable artwork_undef_line_width, which can be located under Manufacture – Artwork folder in the User Preferences Editor.



Allegro Relational Rules Checker Starter Kit

The Allegro 16.6-2015 release now has an option to include a list of limited DFM checks that take advantage of the Cadence RAVEL capabilities. The Relational Rules Starter kit requires the license: MSW43U: Cadence® Relational DRC PCB User.

General Starter Rules Kit categories includes:

■ Component to Component Pin Spacing

❑ Same Component

❑ Adjacent Component

■ Outline checks

❑ Cutout to Outline

❑ Pad to Outline

❑ Etch Trace to Outline

❑ Test Point to Outline

❑ Soldermask to Outline

■ Single Net Pins

■ SMD Pad Entry

■ SilkScreen Checks

❑ Line to Pad

❑ Text To Pad

❑ Min Length

❑ To Test Point

■ Max Blind Via Depth

■ Soldermask Checks

❑ Test Point Pad

❑ SMD Pad

❑ Through Hole Pin Pad

❑ Via Pad.



To start the Allegro Relational Rules Checker Kit, choose Manufacture – Setup RAVEL Rules in CM to open the DFM Ravel Rules GUI form.

The DFM RAVEL Rules GUI form will display the rules provided in the kit. The rules are displayed in a tree structure in the form, divided into multiple categories. Each branch contains sub-categories of rules. When one of the rules is selected, the constraint name and value are located in the lower right corner of the form. The value for the rule may be changed



in this form. For each rule, there is a brief description and image that assist in describing the rule.

The rules to be applied in running the DFM check must have the check-box next to that rule enabled. Once the rules values are defined, and the rule to be applied are selected, click the Apply button. This begins the DRC process with a progress display window open. When errors are found, they are imported into the Allegro Constraint Manager’s DRC – External



worksheet. The errors can be selected in the Allegro Constraint Manager, and the PCB Editor graphics will zoom to that location for review and editing.

For more information on the installation and rules, refer to the Ravel DFM Rules Release Notes, and the DFM Rulekit Guide.



Allegro PCB Designer Product Update

The following list of features transition from the High-speed and Miniaturization product options to the Allegro PCB Editor base product:

■ Backdrill

■ Xnets now getting dynamically updated when Signal Model change (i.e. import logic) can make xnets out of date.

■ Differential Pair Dynamic Phase DRC

■ Highlight Segment over Voids

■ Spread Lines between Voids

■ Tangent Via Line Fattening

■ Contour Routing

Backdrill

Today’s high-speed serial I/O technology presents new challenges for hardware engineers. Passing high frequency signals over a backplane requires minimizing the effect of plated through hole (PTH) stubs. This can be done by using the full length of the barrel for signal layer transitions thus keeping stubs to a minimum, the use of buried or blind vias, or through a board fabrication process called Backdrilling.

Backdrilling in Allegro PCB Editor is a flow application. Nets targeted for potential backdrilling require the property backdrill_max_pth_stub. The value of this property, which can be applied at the schematic level or inside the PCB Editor, is the maximum allowable vertical stub in units of length.

A setup and analysis GUI provides the controls for pass setup and analysis results. Pass setup can be system or user defined and includes:

❑ Side of PCB (top, bottom, both)

❑ Object type (pin, vias, both)

❑ User-Defined Layer Configurations



❑ System-calculated Drill Depth

Graphic feedback in the form of code flags assist in the identification of violations such as testpoint conflicts or remaining stub violations. A detailed log file provides general analysis information about pass setup, drilling and remaining violations. Manufacturing output is enabled by a new option in both the NC Drill and Legend Parameter forms. Each backdrill pass is represented by a unique drill legend and nc drill file.



Note: For more information on backdrilling, refer to the Best Practices paper on the Cadence online support web site (COS).

Differential Pair Dynamic Phase Control

Differential Pair technology has evolved where more stringent checking is required in the area of phase control. This is evident on higher data rates associated with parallel buses such as QPI, SMI, PCI Gen 2, DDR, QDR and Infiniband. In the simplest of terms, Differential Pair technology is sending opposite and equal signals down a pair of traces. Keeping these opposite signals in phase is essential in assuring that they function as intended. As the current Static Phase is limited to a one time check across the entire Driver-Receiver path, a new Dynamic Phase check is introduced that performs phase checks at bend point intervals across the Differential Pair. The check is designed to meet the guidelines suggesting the path lengths of the true and complement signals within the differential pair must differ by no more than “x mils” along the entire path of the net. If at any point on the net, the skew between true and complement exceeds “x mils”, this mismatch needs to be compensated within “y mils”. Representative values for x and y might be x = 20 and y = 600.



Setting the Dynamic Phase DRC

The constraint set associated with differential pairs supports both Static and Dynamic Phase. The margins of each constraint can be set independently using length or time. The Max Length (running skew) constraint is limited to length only.

Terminology

■ Static Phase Tolerance – a one time check from Driver to Receiver comparing lengths or delay of each member. If a Driver cannot be determined, the check is performed across the longest path of the pair. (No change in behavior in 16.3)

■ Dynamic Phase – Etch length of each member is compared at each bend point interval across the Driver-Receiver path of the Differential Pair. Etch length is always measured back to the driver pins.

■ Dynamic Phase Max Length – otherwise called “running skew”. When specified, the Differential Pair is permitted to exceed the phase tolerance constraint for a contiguous etch length of less than or equal to the value of Max Dynamic Phase Violation Length.

Dynamic Phase DRC Graphics

Similar to how uncoupling is reported, a pseudo segment highlights the path of the Differential Pair that is out of phase. The highlighted segment is placed between the members. A DRC marker (D-Y) is located at the point where the Differential Pair first goes out of phase and with respect to driver pin location. In other words, the marker is closer in proximity to the driver, not the receiver pins. Only one DRC marker will be located on the Diff Pair, even if there are multiple instances of phase violations. Cross hair figures are placed at bend intervals and are



located on the longer of the two members. Hover the mouse pointer over the cross hair to view phase mismatch feedback in the form of a audiotape.

Driver Pin Display

Differential Pair Driver pins can be identified by enabling the setting Diffpair Driver Pins. This setting is located in Setup – Design Parameters – Display section. A pin must have its pin use code set to OUT for a Driver symbol to appear.

Note: A pin use code of OUT is not necessary for the Phase DRC to work. The DRC code randomly determines a driver source in an ambiguous situation.

Adding Phase Compensation

One method used to address the phase mismatch involves adding small bumps to the shorter member. This can be accomplished using the Delay Tune command. When the command is invoked, adjust the tuning options to the style you prefer; select the Differential Pair route then right-click and choose Single Trace mode to tune the shorter member.



The second method to address phase mismatch would involve creating opposite bends as part of the route path. This method keeps the pair coupled in a more natural manner and keeps uncoupling to a minimum.

Display of Cline Segments crossing Plane Voids

In order to ensure a continuous loop of return path current, signal traces must reside over an uninterrupted copper plane. Even traces overlapping pin voids can cause disruption of current. Violations are traditionally detected by visually scanning the design, layer by layer, as a post route process.

The Display Segments over Voids command detects cline segments crossing adjacent plane layer voids. These voids can be antipads, split plane gaps, or manually created voids. All segments in violation become permanently highlighted along with the respective void based objects. A descriptive report sorts each violation by layer and differentiates segments crossing voids from ones with partial plane coverage.

A user preference variable, sov_spacing, provides global behavior for the spacing criteria used. A negative value allows segments to overlap voids by that distance. This may be necessary to suppress violations in sub 1MM pitch BGAs. A positive value is the minimum allowable spacing to edge of the void. The command is located in the Display menu and operates on all layers and logical nets by default; DC nets are not processed. To operate on just the active layer, set the variable sov_active_only. To operate just on selective nets, apply the property sov_check to those respective nets. The user preference controls are located in the SOV category of the User Preferences Editor form.

Plane Aware Cline Spreading

The Spread between Voids command provides a semi-automatic solution to spread channel based clines with respect to adjacent plane layer voids. Used in combination with the new Display Segments over Voids command, Spread between Voids requires the selection of two pin or via objects that comprise a channel. If the channel consists of a single



cline, the result will be the centering of the cline between the pin or via based objects. If two or more clines make up a channel, the clines will be spread evenly away from the adjacent layer plane voids.

The Spread between Voids command is located in the Route – Resize/Respace menu. The application works on the active layer and comes with one parameter option, void clearance.

Via-Via Line Fattening

A post route task associated with HDI Design involves increasing the line width between two tangent vias. This is done to remove the acute angle formation at the junction. A batch utility Line Fattening located in the Route – Resize/Resize menu is available to increase line width between vias based on a user-defined edge to edge clearance. The algorithm determines the line width based on the smaller of the two vias. Options are available to ‘waive’ impedance or max line width DRCs that may result.

Note: It is recommended to run this utility near the end of the design process as it’s not possible to perform a reset of line width.

Contour Routing

Routing a bus across the Flex section of a Rigid-Flex design in most cases involves the use of curved corners. Aligning the angle of the route to the corner radius is not always intuitive especially on non 90 degree bends. Ideally one would like to simply guide the route following the contour of the outline or perhaps an existing Connect Line. Available in both single and multi-routing modes, contour hugging locks the current route to either the route keep-in or an adjacent cline. When in the Add Connect command, right-click to access the Contour

Before Spread After Spread



options. An optional Extra Gap field is provided to increase the clearance to either contour element. Close the form and select the highlighted element and then guide your cursor along the contour element path. Click to release the contour hug and resume normal routing.



OrCAD PCB Designer Update

The following list of features transition from Allegro® PCB Editor to OrCAD® PCB Designer Professional and Standard products. Additional information on these features can be found at www.orcad.com. You can also view short videos by clicking following hyperlinks.

Feature Professional Standard

Net Scheduling and DRC Yes No

Relative Delay DRC Yes No

Propagation Delay DRC Yes No

Impedance DRC Yes No

Diff Pair Static Phase DRC Yes No

Heads-Up Display Feedback Yes No

Via Arrays Yes No

Contour Routing Yes No

Group Routing Yes No

Scribble Routing Yes Yes

Skill Extension Language Yes Yes

Menu Restructure Yes Yes


http://www.orcad.com/resources/library/net-schedule-tpoint-orcad-166-2015

http://www.orcad.com/resources/library/constraint-driven-routing-orcad-166-2015




http://www.orcad.com/resources/library/arrays-orcad-166-2015

http://www.orcad.com/resources/library/contour-routing-orcad-166-2015

http://www.orcad.com/resources/library/group-routing-orcad-166-2015-release

http://www.orcad.com/resources/library/scribble-routing-orcad-166-2015-release

http://www.orcad.com/resources/library/orcad-menu-optimization

http://www.orcad.com


OrCAD Menu Restructuring

With the 16.6-2015 release, OrCAD introduces a vastly improved menu structure based on Channel Partner input, customer requests, and with the mandate of making your design experience faster and more intuitive.

Replicating a physical design flow, the menu structure has been re-arranged so that it works in both a horizontal as well as vertical axis. The more common menus such as Import & Export have been exposed to the main canvas while infrequently used menus are relegated further down the tree. Mouse clicks have been minimized by adopting a “two-deep” menu philosophy.

Although this change may be initially disruptive to existing OrCAD users, the long term benefits will be beneficial to all designers. However, you can revert back to the legacy menu, using a new User Preference setting. This setting can be changed with the Menu – Display



– Use Legacy Menu command or it can be changed in the User Preference Editor under UI – General as shown in the screenshots below.



RF PCB Enhancements

This release includes the following enhancements in RF PCB:

■ Allegro Discrete Library to ADS Translator Enhancements on page 39

■ IFF Import and Export Enhancements on page 41

■ Manual Placement Command on page 44

■ Miscellaneous Enhancements on page 46



Allegro Discrete Library to ADS Translator Enhancements

This release includes several enhancements in Allegro Discrete Library to ADS translator. The following image illustrates the latest UI of the tool:

Support for Schematic Symbol Version

You can now define versions for a schematic symbols in the CSV file. On loading a CSV file, a new column is added to the Selected Parts grid. Only those symbols for which a version is defined are translated.



Filter Support for Searching a Library or Part

A filter field is added to search for library part(s).

Associate Selection of Part with Selected Parts Grid

For the parts displayed in the Selected Parts grid, the corresponding libraries are enabled in the tree view.

Support to Select/Unselect All Parts

When the Select/Unselect all check box is selected, all the library parts are added for translation and displayed in the Selected Parts grid. Similarly, disabling this checkbox clears all the selected libraries from the Selected Parts grid.

Performance Improvement

The response time of translator GUI is reduced. The translator no longer parses all the libraries to display the GUI, and improves the performance as a result.

Non-Graphical Mode for Batch Translator

The batch command is enhanced to run the translator in a non-graphical mode using a new option, -auto. This option suppress all graphical user interfaces including the splash window, translator main dialog, and progress window.



Preserve Casing of a Layer Name in the Mapping Process

The mapping process of the translator now preserves the casing of the layer name in ADS and also displays the layer name in the Edit Layer Map dialog.

IFF Import and Export Enhancements

The RF IFF Import and RF IFF Export commands are enhanced to support the editing of layer map files. You can edit the current layer mapping settings using a text editor and save them in a text file.



RF IFF Import

New options are provided in the RF IFF Import to export and import layer mapping settings.

For more information, see Allegro PCB Editor to ADS (Export IFF) in Allegro User Guide: Working with RF PCB.



RF IFF Export

In RF IFF Export interface, the layer mapping settings can be edited by enabling a new option, Layer map new mode in the More Options dialog. The RF IFF Layer Map dialog presents options for importing, editing, and restoring the current layer mappings.

For more information, see ADS to Allegro PCB Editor (Import IFF) in Allegro User Guide: Working with RF PCB.



Manual Placement Command

In 16.6-2015, a new rf_manualplace command is added to support the functions of placing components that are not available with the existing autoplace command.

Using the Manualplace command you can interactively place revised or unplaced components in the design. You can also select multiple components and place or update them sequentially. This command lets you easily check the schematic changes after the netlist is re-imported. On selecting a component, the cursor dynamics changes and show the



outline of the component. Before placing the component you can select a pin to fix for the autoshoving.

While placing or updating a component, you can perform the following actions:

■ rotate the component

■ skip the current component and select next component from the list

■ select start pin

■ snap to the pad edge of etch object or any other component

■ create clearance assembly or merge into existing assembly of surrounding objects

■ auto-shove of placed objects that are connected to the component



Miscellaneous Enhancements

Cross-probing between DE-HDL and PCB Editor

When you edit an RF design and select an RF component or its pins in Design Entry HDL, the corresponding pins of the component are selected in PCB Editor.

The cross-probing between Design Entry HDL and PCB Editor works only if they are launched from Project Manager.

On cross-probing an RF component or its pin, rf_manualplace command becomes active in PCB Editor and lets you place or update the component.

Support for Rotation-Pick Mode in Placement Commands

In this release, the component placement commands support a new rotation-pick mode. In this mode, you can rotate the component before picking a destination.This mode is available for the following commands:

■ rf_autoplace

■ rf_manualplace

■ rf_add_component

You can start the rotation-pick flow using the new right-click pop-up menu, Rotate.



The following figure shows the updated right-click menu for rf_autoplace, rf_manualplace, and rf_add_component commands, respectively.


Cadence SPB: What's New in 16.6-2015Cadence SiP Layout and Allegro Package Designer (APD)

Cadence SiP Layout and Allegro Package Designer (APD)

This section describes the new features and enhancements in Cadence® SiP Layout and Allegro® Package Designer (APD) Release 16.6-2015.

■ Co-Design Die Editing in Symbol Edit Application Mode on page 49

■ Defining Variants on page 50

■ Replacing Via with Via Structure on page 51

■ Changing Symbol Owner on page 51

■ Exporting Netlists on page 52

■ Degassing Enhancement of Void Clearance for Adjacent Layer Shapes on page 52



Co-Design Die Editing in Symbol Edit Application Mode

The Symbol Edit Application Mode has been expanded to operate on co-design dies as well. A co-design die is one that was created by the loading of a die abstract. Using the Symbol Edit Application mode, you can refresh a co-design die symbol and also view and edit die bumps and I/O drivers.

Using the new options, you can easily balance the ideal bump pattern with respect to both the drivers and top level metal in the IC and the pin escape pattern on the package substrate, or bond wire pattern for a bonded die; for example, you can optimize the bump pattern with respect to both the drivers and the package pins or optimize net assignments.

Use the Refresh co-design die option to refresh a die in the database from the disk file or to make a library change.

After displaying the I/O drivers of a co-design die using Show IC Details, you can perform the following operations on the selected drivers:

■ Move

■ Align

■ Respace

■ Swap

■ Change Driver Placement Status



Defining Variants

You can now define subsets of components and cross-section layers in a master design so that each subset is a single variant of that package design (Manufacture – Define Variants). For example, you might define two variations of a memory stacked design, where each variant has memory chips from a different set of vendors. Using the variants feature, you can create a master design that contains the dies for the different variants, and then define a variant for each set of dies which will be assembled together in a final, packaged substrate.

This feature saves design time by allowing you to design once, and then analyze and manufacture many times; you manage all physical connections in a master design and then generate variant designs that are ready for SI and PI analyses, 3D DRCs, and documentation generation.

By using the variants feature, you ensure that when the package substrate is updated, all the variants are updated; decreasing the chances of synchronization and manufacturing or



assembly errors. For example, when pushing and shoving a bond finger in the master drawing, all bond wires connecting from any of the variants’ dies are updated at the same time. Similarly, if a new finger is added such as a blank bonding target in some variants, the finger label of all variants are updated and geometries exposed through soldermask openings are kept in sync. The overall impact is a greatly reduced probability of errors during manufacturing or assembly of any of the final packaged components.

Replacing Via with Via Structure

You can now create as detailed a via pattern as necessary in an efficient, quicker way while performing interactive routing. Use the new replace via with via structure command to replace selected or all vias that use a specific padstack definition with instances of an existing via structure definition. For example, use a large via, which reserves the space needed for a more complex via structure pattern, during initial routing. When routing is complete, replace the placeholder via with the via structure to create the final, detailed routing.

You can also use this command to replace instances of a via structure with a via in order to restore the design to its original state with the original vias.

Changing Symbol Owner

You can now interactively add static shapes as children of a symbol instance. For example, you can add texts, fiducial vias, alignment lines, or reference outlines or shapes. Any operation, such as move or delete, performed on the parent symbol instance will also occur on the children.

Note: If you refresh a symbol from library, any instance items will be deleted. If you want the instance items to be preserved, disassociate the instance items first and then reattach them after refresh.

Use the change sym owner command either to add database objects as children of a specified symbol instance or to remove current children from their owning parent symbol instance.



Exporting Netlists

You can use the netlist spreadsheet command to export a spreadsheet style netlist to be used for documentation purposes. The spreadsheet is organized as a set of columns for each component: any BGA components, followed by die components, and, finally, discrete components. The cells are colored according to the color of the nets in the design. The spreadsheet contains columns for Net name, RefDes, Pin Number, and Pin Name.

Degassing Enhancement of Void Clearance for Adjacent Layer Shapes

You can now specify the behavior of degassing void creation depending on overlap with adjacent layer shapes using the new Adj. layer void clearance option. Earlier, shapes on adjacent layers were ignored by degassing. Now, in addition to the default behavior that ignores adjacent layers, you can also specify the following behavior by selecting the appropriate option:

■ Inside Shape: Degassing voids will only be created if the void is entirely inside an adjacent layer plane shape.

■ No Void Overlap: Degassing voids will not be created if there is an overlap with a void in another shape.


Cadence SPB: What's New in 16.6-2015Allegro Constraint Manager

Allegro Constraint Manager

This section describes the new features and enhancements in Allegro® Constraint Manager Release 16.6-2015.

■ Tag-based ECSet Mapping on page 54

■ Single-Step Method for Creating Class-Class Relationships on page 57

■ PCSets and SCSets Difference Reports on page 57



Tag-based ECSet Mapping

The process of applying an ECSet to target nets involves mapping the pins in the ECSet to the component pins in design for those nets. This process looks at many factors including signal_model assignments, pinuse, and RefDes to make a match. Difficulties can arise when the mapping is forced to rely solely on RefDes information and there is no one-to-one correlation between the RefDes information in the ECSet and the design. Take for example the following topology:

The mapping process has no way to distinguish between U2, U3, U4, and U5 except by RefDes. To address these issues, ECSet nodes now support tags (pin parameter) which can be used to uniquely identify a pin and remove any ambiguity. This can be used to lock the mapping between the ECSet and associated nets and will not be impacted by placement or RefDes changes.

Tags can be defined in a design prior to ECSet extraction or ECSet application and can also be defined in SigXplorer.



Tags Driven from SigXplorer

When the Update Constraint Manager command is executed, the following dialog is displayed:

Tags can be added in SigXplorer to the specified nodes using the Parameters pane.



When the ECSet is applied to target nets, an interactive dialog is displayed where you assign the tags in the ECSet to the appropriate pins in the design.

This dialog shows the original log file at the bottom with new messages for cases where the ECSet has mapping tags but the design does not. The top portion contains pulldowns in the (X)Net section to use the Pin column or the Tag column to map the appropriate tags to the proper pins, and then update all the applicable objects which reference the same ECSet.

Tags Driven from Design

Tags can be added to pins in a design prior to extracting a topology into SigXplorer. The tags can be used to schedule a topology and when the topology is applied back to the design.

ECSet mapping tags are also supported in the Front-to-Back flow between Design Entry HDL and Allegro PCB Editor.

For more information see, Mapping ECSets to Nets using Tags in Allegro Constraint Manager User Guide.



Single-Step Method for Creating Class-Class Relationships

This release includes, a usability enhancement to ease the process of creating and updating class-class relationships between Net Classes and Region Classes in the Spacing and Same Net Spacing domains.

When you select the Constraint Set References command for a design, or a Region, a dialog displays a matrix of Net Classes. By clicking a cell, you can create Class-Class relationship between two Net/Region Classes and also apply an SCSet available from the drop-down list.

This solution works only if spacing CSets, Net Classes, and Region Classes are already in the design.

For more information see, Objects – Constraint Set References in Allegro Constraint Manager Reference Guide.

PCSets and SCSets Difference Reports

In this release, Constraint Manager is enhanced to provide support for comparing physical or spacing constraint sets. When a constraint set is selected, a new option Compare appears



in the pop-up menu. On selecting a single constraint set, a Select Object dialog is displayed where you can select a constraint set to compare.



On comparing two CSets, an XML-based report is generated that opens in the in-built browser.


Cadence SPB: What's New in 16.6-2015Virtuoso SiP Architect

Virtuoso SiP Architect

This section describes the new features and enhancements in Virtuoso® SiP Architect Release 16.6-2015.

■ Compatibility with IC Releases on page 60

■ Import Model Enhancement on page 60

■ New Die Abstract File Name Extension on page 61

Compatibility with IC Releases

HotFix 51 of SPB 16.6-2015 (16.60.051) is compatible with CIC releases IC6.1.6.500.11 and ICADV12.1.500.13.

Note: Going forward, all the hotfixes of Virtuoso SiP Architect will support these CIC releases.

Import Model Enhancement

In SPB 16.6-2015, the model import feature is enhanced to support the Sigrity™ Broadband Spice model file. Following figure shows a sample model file header for the newly supported file format (*.ckt).

**NETLIST DCOP_N_50, DCOP_P_50, FB* Port 1 = C10-1 DCOP_P_50* Port 2 = R32-2 DCOP_N_50* Port 3 = R32-1 FB* Port 4 = R35-1 DCOP_N_50


Cadence SPB: What's New in 16.6-2015Virtuoso SiP Architect

New Die Abstract File Name Extension

In SPB 16.6-2015, a new file-name extension, .xda is introduced for the die abstract file. From this release, the die data will be saved in the die abstract (.xda) file.


Cadence SPB: What's New in 16.6-2015Allegro Design Entry HDL

Allegro Design Entry HDL

This section describes the new features and enhancements in Allegro® Design Entry HDL Release 16.6-2015.

■ Enhancements in Design Entry HDL on page 63

■ Component Browser - ADW Mode on page 63

■ Tag-based ECSet Mapping on page 63



Enhancements in Design Entry HDL

Hierarchical Variants

Design Entry HDL supports hierarchical variant tasks in the schematic canvas. Variants defined in lower-level hierarchical blocks can be applied on block instances in higher level blocks. With the inclusion of hierarchical variants in the Design Entry HDL schematic, you can now also generate hierarchical variant BOM reports.

For more information, refer to the Enabling Hierarchical Variants section in Allegro Design Entry HDL User Guide and the Creating Hierarchical Variant BOM Reports section in Allegro Design Entry HDL Utilities User Guide.

Read-only Sheet Import

In Design Entry HDL, the sheet import command now supports the import of schematic sheets in read-only mode. For details, see the Importing Designs section in Allegro Design Entry HDL User Guide.

Component Browser - ADW Mode

You can now access the Component Browser in two modes—the standard mode and the Allegro Design Workbench (ADW) mode. The ADW mode allows you access to a larger, and accessible-from-anywhere dataset, of components.

The ADW mode (also referred to as the online mode in the documentation), enables faster, free-text searches, provides life cycle functionality, preferred parts lists, alternate manufacture lists, and provides a shopping cart that allows you to search for parts that are selected or added to a design.

For more information, refer to the Using Component Browser section in Allegro Design Entry HDL User Guide.

Tag-based ECSet Mapping

User-defined tags in ECSets can be added to pins or components in a design prior to extracting a topology in SigXplorer. These tags can be used to schedule a topology and are used when the topology is applied back to the design.



ECSet mapping tags are also supported in the front-to-back flow between Design Entry HDL and PCB Editor.

For more information, refer to the Working with ECSet Tags section in Allegro Design Entry HDL – Constraint Manager User Guide.


Cadence SPB: What's New in 16.6-2015Allegro Part Developer

Allegro Part Developer

This section describes an enhancement in Allegro® Part Developer Release 16.6-2015.

■ Pin Numbers Display in Rename Pin Dialog

Pin Numbers Display in Rename Pin Dialog

The Rename Pin dialog in Part Developer now has a column, Pin Number, which displays a comma-separated list of pin numbers corresponding to the logical pin names across all slots and packages.


Cadence SPB: What's New in 16.6-2015Allegro FPGA System Planner

Allegro FPGA System Planner

This section describes the new features and enhancements in Allegro® FPGA System Planner Release 16.6-2015.

■ New Device Support on page 67

■ Managing Design Block Symbol on page 67

■ Generating ASA Design on page 67

■ Enhanced Multi-Device Connections (Daisy Chain Connectivity) on page 67

■ Termination Reference Designator Support (OrCAD) on page 68

■ Miscellaneous Enhancements on page 68



New Device Support

This section lists new device families that are added in the current release:

■ Arria II GZ

■ MAX 10

Managing Design Block Symbol

In the current release, the following features are introduced:

■ The Design Block Split Symbol Editor

■ The Design Block Monolithic Symbol Editor

The Design Block Split Symbol Editor provides a solution to manage large design block symbol by splitting them into multiple symbols. Instead of generating one large symbol, you can split the ports of design block across multiple symbols. This support reduces the size of the design block symbol.

The Design Block Monolithic Symbol Editor lets you manage the symbol graphics of a design block monolithic symbol.

Note: These features are available for DE-HDL design.

Generating ASA Design

In the current release, FSP lets you generate ASA design. You can then open the exported design files using ASA and continue the design process.

Enhanced Multi-Device Connections (Daisy Chain Connectivity)

Starting this release, the connections between the DUT component and other components such as connectors is enhanced. Now, FSP provides you the ability to create a daisy chain connectivity between these components. In daisy chain connectivity, you can request for optimal pinout, if the DUT pin needs to choose a pin from the specified set of connectors. You need to define target sets that will combine multiple connectors to achieve optimized connectivity across connectors.



Termination Reference Designator Support (OrCAD)

Starting this release, FSP handle reference designators in DE-HDL and OrCAD environments in the same manner.

When you initially generate schematic, FSP does not assign or pass reference designators for termination components; however, when you assign reference designators in DE-HDL or Allegro PCB Editor and import the board file in FSP, the reference designators are imported in the FSP design.

Miscellaneous Enhancements

Significant enhancements have been made in the following sections:

■ Starting this release, the Find and Filter features appear as panes in all the spreadsheet editors instead of dialog boxes.

■ Starting this release, you can select FSP’s FPGA parts using Component Browser. You can also skip this step (selecting FPGA part manually) by adding FSP_FPGA PTF key in the PTF file of the respective parts. If no PTF key specified, you will be prompt to select the FPGA part manually.

■ When you hover the mouse pointer over the net or pin, you can now see the net name and pin name in the main status bar.

■ Following items are appended to the Generate menu:

❑ Open: Lets you access the other Cadence tools.

❑ Edit Design Block Symbol: Lets you access the design block split symbol editors.

■ Following item is appended to the Tool menu:

❑ Create Target Sets: Lets you access the Create Target Sets dialog box.


Cadence SPB: What's New in 16.6-2015OrCAD Capture

OrCAD Capture

This section describes the new features and enhancements in OrCAD® Capture Release 16.6-2015.

■ Capture Lite License String on page 70

■ Renaming of Licenses on page 70

■ Enhancement in Learning PSpice on page 72

■ New Licenses to Explore Signals from Capture on page 75

■ Enhancement in the Capture Start Page on page 76

■ New Simulation Macro Models for the Capture-PSpice Flow on page 77



Capture Lite License String

A new license string, OrCAD Lite - Capture CIS to launch OrCAD CIS Lite, is added to the Cadence Product Choices window. By selecting the OrCAD Lite - Capture CIS license string, you can launch Capture CIS in the Lite mode, even if you are a licensed user.

Note: You cannot switch between the Lite mode and the licensed version of Capture without restarting Capture.

Renaming of Licenses

The following four licenses used in the Capture – PSpice and Capture CIS – PSpice flows have been renamed:

Old License String New License String

OrCAD EE Designer OrCAD PSpice Designer

OrCAD EE Designer Plus OrCAD PSpice Designer Plus

OrCAD_Capture_CIS_option with OrCAD EE Designer

OrCAD_Capture_CIS_option with OrCAD PSpice Designer

OrCAD_Capture_CIS_option with OrCAD EE Designer Plus

OrCAD_Capture_CIS_option with OrCAD PSpice Designer Plus



Enhancement in Learning PSpice

In 16.6-2015, 20 new chapters have been added to the Learning PSpice application. The new chapters include:

■ Modeling Potentiometers and Variable Resistors

This chapter provides an overview of modeling potentiometers and variable resistors using OrCAD Capture. It also provides an overview of how to simulate example circuits using PSpice.

■ Filter Models Implemented with Analog Behavioral Modeling (ABM)

This chapter covers how the filter behavioral models are developed and implemented using the Laplace function of PSpice. Given the filter bandwidth and order, the models simulate lowpass, highpass, bandpass, and band-reject filters.

■ Modeling Voltage-Controlled Resistors and Capacitors in PSpice

This chapter illustrates how to control Q of a series RLC filter network and change the frequency of a Wien bridge oscillator using voltage controlled impedance.

■ Modeling Voltage-Controlled Oscillators

This chapter provides an overview of modeling Voltage-Controlled Oscillators (VCOs), such as, Dual Integrator VCO and Controlled Reactance VCO using PSpice.

■ Creating Impedances with Behavioral Modeling

This chapter illustrates the method of creating non-linear resistors using Analog Behavioral Modeling by creating the transfer function for a linear conductance.

■ Ferrite Bead Models to Analyze EMI Suppression

This chapter discusses the importance of ferrite beads for in Electromagnetic Interference (EMI) and using these Models in High Speed designs. It also provides guidelines on the selection of a Bead model.

■ Modeling Schottky Diodes

This chapter explains how the model parameters IS and N can be modified to set the forward voltage drop of a Schottky diode.

■ Modeling Quartz Crystals

This chapter explains how a Quartz Crystal can be modeled using a series RLC circuit and a parallel (package) capacitor.

■ Including Relays in PSpice Simulations



In this chapter, two approaches for modeling the relay are discussed, the mechanical model approach, and purely electrical (behavioral) models approach.

■ Radiation Effect Modeling

The information in this chapter provides a starting point for those interested in using PSpice for radiation effects analysis.

■ Using PSpice to Simulate the Discharge Behavior of Common Batteries

This chapter presents PSpice behavioral models for simulating following battery types: non-rechargeable Alkaline cells, rechargeable Nickel-Cadmium (NICD) cells, Nickel-Metal-Hydride (NIMH) cells, and sealed Lead-Acid cells.

■ Brushless DC Motor Model

Although PSpice is designed as an electronic circuit simulator, you can also use it to simulate mechanical or electromechanical systems. An example of an electromechanical system which can benefit from PSpice simulation is a Brushless DC motor. This chapter discusses the modeling and simulation of Brushless DC Motor.

■ Using the Inductor Coupling Symbols

This chapter covers different topics explaining the use of inductor coupling symbols in a Capture – PSpice project.

■ Improving Simulation Accuracy when using Passive Components

This chapter covers various examples to describe the effects of frequency and temperature on the behavior of selected common passive components.

■ Analyzing Amplifier Settling Time

In this chapter, the settling time of LF411 amplifier in unity gain configuration will be computed as a function of load capacitance by implementing relevant goal functions.

■ Obtaining Steady State of High-Q Circuits using Open Loop Response

This chapter explains how to simulate High-Q circuits.

■ Obtaining S-Parameter Data from the Probe Window

This chapter explains measuring S parameters in PSpice using probe measurements.

■ Digital Worst-Case Timing Simulation

This chapter explains the digital worst-case timing simulation feature as a function of component propagation delay tolerances, to evaluate the timing behavior of Digital and Mixed Analog/Digital designs.



■ Digital Frequency Comparator

This chapter illustrates how a hierarchical all-digital design with two implementation views, can be defined in OrCAD Capture, and subsequently simulated in PSpice. The example used in this chapter is basic Digital Comparator.

■ Creating Eye Displays using Probe

This chapter discusses the eye display creation using probe in PSpice.

Note: You can access Learning PSpice only in Capture-PSpice flow. To access Learning PSpice, choose Help — Learning PSpice in Capture.



New Licenses to Explore Signals from Capture

Before 16.6-2015, you could view or explore circuit topology in the Capture – SigXplorer flow, if you had one of these licenses: OrCAD PCB SI, Allegro PCB SI XL, and Allegro Sigrity SI.

In 16.6-2015, three new licenses are supported for the Capture – SigXplorer flow. These licenses are:

■ OrCAD Capture

■ OrCAD Capture CIS

■ OrCAD PSpice Designer



Enhancement in the Capture Start Page

The Capture start page in 16.6-2015 is given a new look and interface. You can access various:

■ Capture resources, such as, videos, webinar sessions, and white papers

■ Capture applications to help designers

■ Reference designs to help you start working on Capture

To access start page in Capture, select Help – Start Page.



New Simulation Macro Models for the Capture-PSpice Flow

A new library called ltspicedevices.olb has been added in the Capture library at <installation>\tools\capture\library\pspice. The library contains 19 new devices that can be used to migrate your design from LTSpice to the Capture – PSpice flow. The following devices are included in the ltspicedevices.olb library:

■ LT_AND

■ LT_AND3

■ LT_AND4

■ LT_AND5

■ LT_OR

■ LT_OR3

■ LT_OR4

■ LT_OR5

■ LT_BUF

■ LT_BUF1

■ LT_EX-OR

■ LT_INV

■ LT_Modulator

■ LT_OTA



■ LT_OTA_ASYM

■ LT_OTA_LINEAR

■ LT_PHASEDET

■ LT_RSLATCH

■ LT_SAMPLEHOLD


Cadence SPB: What's New in 16.6-2015PSpice

PSpice

This section describes the new features and enhancements in PSpice® Release 16.6-2015.

■ New Chapters in Learning PSpice on page 80

■ New Simulation Macro Models for the Capture-PSpice Flow on page 80

■ VBIC Support Added in PSpice on page 81

■ New Device Added in PSpice for the Device Model Interface Support on page 82

■ ADMS XML Filters for Verilog-A to PSpice DMI Models Translation on page 82

■ Documentation Enhancements on page 83

■ PSpice Lite License String Added for PSpice Lite Mode on page 83



New Chapters in Learning PSpice

In 16.6-2015, 20 new chapters have been added to the Learning PSpice application. To view a list of the new chapters with a brief description for each, see Enhancement in Learning PSpice on page 72.

You can access Learning PSpice in the Capture - PSpice flow only. To access Learning PSpice, choose Help — Learning PSpice in Capture.

New Simulation Macro Models for the Capture-PSpice Flow

A new library called ltspicedevices.olb has been added in the Capture library at <installation>\tools\capture\library\pspice. The library contains 19 new devices that can be used to migrate your design from LTSpice to the Capture – PSpice flow. The following devices are included in the ltspicedevices.olb library:

■ LT_AND

■ LT_AND3

■ LT_AND4

■ LT_AND5

■ LT_OR

■ LT_OR3

■ LT_OR4

■ LT_OR5

■ LT_BUF

■ LT_BUF1

■ LT_EX-OR

■ LT_INV

■ LT_Modulator

■ LT_OTA

■ LT_OTA_ASYM



■ LT_OTA_LINEAR

■ LT_PHASEDET

■ LT_RSLATCH

■ LT_SAMPLEHOLD

For more information on new simulation macro models, refer to PSpice A/D Reference Guide.

VBIC Support Added in PSpice

In case of Early effect, Quasi-saturation, temperature modeling, avalanche multiplication and so on, VBIC, a bipolar junction transistor (BJT) model, can be used instead of the SPICE Gummel-Poon (SGP) model as it better modeling than SGP.

From 16.6-2015, a new Q device, which is a npn-type BJT model, is added to Capture library for the Capture - PSpice flow and can be accessed from breakout.olb. The model definition and netlist instance of the QVBICN model are as follows:

Model Definition: .model QVBICN CMI VBIC npn=1

Netlist instance: Y_Q1 C B E S CMI orPSpiceDevices.dll QVIBICN

QVBICN is an example of Device Model Interface (DMI) support that is used to create specific devices from the model DLL files.



New Device Added in PSpice for the Device Model Interface Support

A new generic device, Y device, is added in PSpice for the DMI support. Using this generic device and DLL files, you can create various type of devices, such as, BJT, Voltage-controlled Voltage Source (VCVS), and Thin-film Transistor (TFT).

The DLL files are generated by compiling the C code. You can modify the C code to generate a device that can perform a specific function.

For more information on DMI models, refer the Device Model Interface section in PSpice A/D Reference Guide.

For more information on generating DLL files and compiling C code, refer to the following documents:

■ PSpice DMI API Reference Guide

■ PSpice Device and System Modeling with C/C++ and SystemC

ADMS XML Filters for Verilog-A to PSpice DMI Models Translation

From 16.6-2015, Verilog-A models can be simulated by PSpice when converted to PSpice DMI models. The Verilog-A models are converted to an equivalent-C code by Automatic Device Model Synthesizer (ADMS) using the PSpice DMI-compatible XML filters, which are located at <installation>\tools\pspice\api\adms\xmls. The generated C code can be compiled into PSpice DMI-compatible DLL files.

For more information on Verilog-A support in PSpice, refer the PSpice Device and System Modeling with C/C++ and SystemC document.

Note: Only the ADMS-supported Verilog- A models are converted to PSpice DMI models.



Documentation Enhancements

Two new documents have been added for DMI support in the <installation>\doc folder:

■ PSpice Device Modeling Interface API Reference Guide

Describes the APIs that can be used to generate and compile the PSpice DMI DLL files.

■ PSpice Device and System Modeling with C/C++ and SystemC

Provides step-by-step instructions for generating and compiling new SystemC DLL files.

PSpice Lite License String Added for PSpice Lite Mode

Before 16.6-2015, there was no option to launch PSpice in Lite mode if you had any valid license. Now you can use the new license string, OrCAD Lite - PSpice, to launch PSpice in the Lite mode, even if you have a valid license.

Note: You cannot switch between the Lite and the licensed version of PSPice in the same session. You have to restart PSpice and select the required option.


Cadence SPB: What's New in 16.6-2015Allegro Sigrity SI and PI

Allegro Sigrity SI and PI

This section describes the new features and enhancements in Allegro® Sigrity™ SI and PI Release 16.6-2015.

■ Report Enhancements on page 85

■ Waveform Option on page 87

■ Electrical and SI Metrics Checks on page 88

■ Displaying DC Violation Markers on page 89

■ Replicating Decap Placement on page 90

■ Displaying Power Pins and Effective Radius Post Placement on page 90

■ Pin-Based AMM Auto Setup Workflow in PowerDC on page 91

■ Additional Enhancements on page 92



Report Enhancements

The Analysis Report Generator now includes additional information including the name of any ECSet assigned to a net in the report.



Additional threshold information found on the net will be displayed alongside the analysis results and Pass / Fail based on those threshold settings will be clearly indicated.



Waveform Option

The default waveform viewer is 2D Curves. You can now change it to SigWave using the use_sigwave preference setting in the Signal_analysis category of User Preferences.



Electrical and SI Metrics Checks

The Analyze – Trace Impedance / Coupling Check command is renamed as Analyze – ERC- SRC command. It accesses Electrical Rule Checks and Simulation Rule Checks in PowerSI which are essentially the same trace checks and SI Metrics checks as earlier.



Displaying DC Violation Markers

The DC Violation Marker UI has been enhanced. When you navigate to a violation marker, the object is highlighted and some guideline information for the type of violations is available:



Replicating Decap Placement

The Decap Placement Replication command lets you apply the decap placement template to several instances of the same device.

For some designs, such as the DDR design, many ICs are exactly the same. In this case, only one PICset needs to be created which can then be applied to other components in Constraint Manager.

A decap template can be applied to several instances of the same device (IC), if there are at least two instances of the IC associated with the same PICSet, and all the decaps in the PICSet are placed for at least one instance. This instance is used as the template to replicate. An additional condition is that for at least one instance, none of the decaps should be placed.

For more information, see the Working with the Decap Flow chapter of Allegro Sigrity PI Flow Guide.

Displaying Power Pins and Effective Radius Post Placement

You can display and change the placement of decaps and power pins according to the effective radius of the placed decaps. This functionality is available from the right-click pop-up menu, which is activated when you choose the Analyze – Decap Place command.

For more information, see the Working with the Decap Flow chapter of Allegro Sigrity PI Flow Guide.



Pin-Based AMM Auto Setup Workflow in PowerDC

Pin-based Analysis Model Manager is now supported in PowerDC launched from Allegro Sigrity PI. You can perform auto assignment using AMM for DC settings.

After preparing the AMM data, select the Auto Assignment Using Analysis Model Manager link under the Initial Setup section in the workflow:



A wizard walks you through the auto assignment process. You can later validate the DC settings in PowerDC launched from Allegro Sigrity PI.

Additional Enhancements

Some additional enhancements in PowerDC launched from Allegro Sigrity PI include:

■ TCL support

■ Save spd file

■ 32-bit OS support


cadence spb: what’s new in 16.6-2015 (hotfix 51) · cadence spb: what's new in 16.6-2015...

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