accurate and efficient on chip spectral analysis

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Accurate and Efficient On-Chip Spectral Analysisfor Built-In Testing and Calibration Approaches

Hari Chauhan, Student Member, IEEE, Yongsuk Choi, Marvin Onabajo, Member, IEEE,In-Seok Jung, Student Member, IEEE, and Yong-Bin Kim, Senior Member, IEEE

Abstract— The fast Fourier transform (FFT) algorithm iswidely used as a standard tool to carry out spectral analysisbecause of its computational efficiency. However, the presence ofmultiple tones frequently requires a fine frequency resolutionto achieve sufficient accuracy, which imposes the use of alarge number of FFT points that results in large area andpower overheads. In this paper, an FFT method is proposedfor on-chip spectral analysis of multi-tone signals with partic-ular harmonic and intermodulation components. This accurateFFT analysis approach is based on coherent sampling, but itrequires a significantly smaller number of points to make theFFT realization more suitable for on-chip built-in testing andcalibration applications that require area and power efficiency.The technique was assessed by comparing the simulation resultsfrom the proposed method of single and multiple tones with thesimulation results obtained from the FFT of coherently sampledtones. The results indicate that the proper selection of testtone frequencies can avoid spectral leakage even with multiplenarrowly spaced tones. When low-frequency signals are capturedwith an analog-to-digital converter (ADC) for on-chip analysis,the overall accuracy is limited by the ADC’s resolution, linearity,noise, and bandwidth limitations. Post-layout simulations of a16-point FFT showed that third-order intermodulation (IM3)testing with two tones can be performed with 1.5-dB accuracy forIM3 levels of up to 50 dB below the fundamental tones that arequantized with a 10-bit resolution. In a 45-nm CMOS technology,the layout area of the 16-point FFT for on-chip built-in testingis 0.073 mm2, and its estimated power consumption is 6.47 mW.

Index Terms— Analog testing, built-in testing (BIT), coherentsampling, digitally assisted calibration, fast Fourier transform(FFT), on-chip distortion analysis, spectral testing.

I. INTRODUCTION

D IGITALLY assisted analog design [1] and integratedtransceiver calibration [2], [3] approaches are gaining

popularity in ensuring efficient and reliable mixed-signal sys-tems in nanoscale CMOS technologies. One design aspectis to equip analog blocks with performance-tuning featuresthat allow the recovery from process variations and faults.Examples of such tuning mechanisms include input impedancematching, gain and center frequency tuning for low-noiseamplifiers [3]–[5], second-order nonlinearity and mismatch

Manuscript received August 13, 2012; revised December 8, 2012; acceptedFebruary 24, 2013.

The authors are with the Electrical and Computer Engineer-ing Department, Northeastern University, Boston, MA 02115USA (e-mail: [email protected]; [email protected];[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2013.2251919

correction for mixers [6]–[8], as well as linearity enhance-ments for baseband filters [9]. The other aspect related todigitally assisted design is the extraction of performancemetrics on the chip to enable one-time or periodic calibrations.

Many performance characteristics can be observed based onthe output spectrum of a circuit under test (CUT) or a chainof analog blocks, which has led to on-chip spectrum analyzersthat emulate conventional off-chip instrumentation [10], [11].Alternatively, calibration methods have been proposed thatincorporate existing or dedicated analog-to-digital converter(ADC) and digital signal processing resources to directly quan-tize the output signals of analog circuits for the computationof the fast Fourier transform (FFT) and automatic tuning withdigital-to-analog converters (DACs) [12], [13]. Extraction ofcircuit linearity parameters with the latter approach calls forefficient FFT implementations, which is the focus of thispaper. The presented method leverages that the frequenciesfor two-tone tests can be selected by the designer of thebuilt-in test (BIT) or built-in calibration (BIC) scheme tocircumvent inaccuracies due to spectral leakage while usinga small number of FFT points. This capability to accuratelymeasure the power of the tones as well as their distortionand intermodulation products with an efficient on-chip FFTcan also find application in loopback testing techniques withspectral estimation such as in [14] and [15].

Fig. 1 visualizes the BIC approach that is the target applica-tion for the presented FFT realization. The calibration methodcould be applied to an individual analog block or a cascadeof blocks. In practice, the maximum test signal frequencydepends on the highest possible ADC sampling frequencyand clock frequency for the FFT computation. Thus, a down-conversion within the chain of blocks under calibration isassumed if it involves RF circuits. In such a case, an effectivecalibration might require sequential injection of test signalsat various locations along the analog signal chain throughthe use of switches as in [16]. Alternatively, it has beenshown that an envelope detector can be placed at the outputof an RF circuit to extract the signal characteristic at lowerfrequencies. For example, it is outlined in [17] how an inputsignal with two test tones ( f1, f2) allows to determine third-order linearity characteristics of the CUT by monitoring thespectral components at frequencies up to 3 · ( f2 − f1), whichcan be assured to be low by selecting appropriate test tonefrequencies with narrow spacing. This permits the use oflower sampling frequencies. The output signal is quantizedby the on-chip ADC in Fig. 1 prior to the FFT computation,

1063-8210/$31.00 © 2013 IEEE


2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 1. On-chip BIC approach with spectral testing.

which may be implemented with existing system resources orextra components. An adaptive biasing block (that typicallyincludes DACs) enables the digitally assisted performancetuning for the analog circuit(s) based on the digital extractionof gain, linearity, or frequency response parameters. Mostrelated circuit-level and system-level considerations in theabove-mentioned references are outside of the scope of thispaper, in which the main focus is on the realization of suitablearea- and power-efficient FFT implementations to supporton-chip BIT and BIC approaches. One way to characterizea nonlinear circuit is by applying a test tone at the input andmeasuring the harmonic distortion (HD) magnitudes in thespectrum at multiples of the input frequency. This approach isfeasible at low frequencies but less practical at RFs becauseof the difficulties associated with measuring high-frequencyharmonics. Furthermore, these harmonics typically fall outsidethe bandwidth of narrow-band RF amplifiers and other receiverblocks. For this reason, two-tone test methods have beendeveloped. For example, the characterization of the third-order linearity can be conducted by applying two closelyspaced input tones ( f1, f2) and measuring the third-orderintermodulation product at (2 · f2 − f1) or (2 · f1 − f2), whichcan be nearby frequencies within the CUT’s passband [18].

This paper is organized as follows. In Section II, thebasic FFT and application-related constraints are discussed.In Section III, the coherent sampling approach and itslimitations are reviewed. The proposed approach is presentedin Section IV, for which comparative simulation results areprovided in Section V. In Section VI, implementation detailsand post-layout simulation results are discussed. Conclusionis given in Section VII.

II. FFT FOR TESTING APPLICATIONS

Various on-chip FFT implementations have been developedfor communication systems such as those using orthogonalfrequency division multiplexing that requires a combination ofhigh throughput rate and accuracy [19], [21]. These require-ments typically translate into a large number of FFT points(e.g., 64–2048), resulting in area and power requirements

of >1 mm2 and >20 mW, respectively. The purpose of theproposed FFT utilization approach is to reduce the overheadsassociated with on-chip FFT implementations for built-intesting applications because mixed-signal systems-on-a-chipfrequently do not provide room for inclusion of such extensivedigital signal processing resources.

A. Basic FFT Algorithm

The basic FFT algorithm calculates the spectrum of theinput waveform only for certain discrete frequencies knownas FFT bins that are separated by the fundamental frequency(� f ) of the FFT. The � f strictly depends on the samplingfrequency ( fsamp) and the length of the FFT (NFFT) asfollows: � f ≡ fsamp/NFFT. Thus, to avoid spectral leakageand to accurately measure the frequency components of theinput waveform, its frequencies have to be exact integermultiples of � f . To achieve high-frequency resolution, eitherthe sampling frequency has to be decreased or the length of theFFT has to be increased. Since the sampling frequency shouldmeet the Nyquist criterion, the sampling frequency conditioncan typically not be relaxed when the goal is to performon-chip analysis of the highest possible signal frequency underthe constraints of a given CMOS technology. In contrast,increasing the length of the FFT to achieve better frequencyresolution results in an additional area overhead and therebyreduces the feasibility of an FFT implementation for on-chiptesting applications. Therefore, the simple FFT algorithm ismost useful for single-tone testing when the input waveformcontains a single frequency component and its higher orderharmonics. On the other hand, spectral leakage is difficult toavoid in multi-tone testing cases, where one or more of theinput tones might not be the integer multiple of � f .

A useful approach to alleviate the leakage effect is to choosea suitable window function that minimizes the energy spread-ing [22], [23]. However, the use of a windowing techniqueintroduces various other flaws into the spectrum such as fre-quency/amplitude imprecision, broadening of main lobe width,and creation of side lobes. Moreover, windowing operationsrequire additional computational resources.

III. CONVENTIONAL COHERENT SAMPLING

Coherent sampling is a useful and efficient technique forevaluating the spectral performance of analog/mixed signalcircuits [24]–[27], because it increases the FFT accuracy andeliminates the need for a window function if certain conditionsare met. Coherent sampling of a single tone assures that itspower in the spectrum is contained in exactly one frequencybin. The condition for coherent sampling is given by

fin/ fsamp = Ncycle/NFFT (1)

where fin is the input frequency, fsamp is the samplingfrequency, Ncycle is the integer number of cycles of the signalto be sampled, and NFFT is the length of the FFT engine.

To ensure coherent sampling, one can first determine thenumber (usually prime) of integer cycles (Ncycle) that fits intothe predefined sampling window, and use it to approximatethe input frequency to the near optimal frequency that exactly


CHAUHAN et al.: ACCURATE AND EFFICIENT ON-CHIP SPECTRAL ANALYSIS 3

matches with one of the discrete frequency bins in the spec-trum for the given FFT length [28], [29]. Under the conditionin (1), there will not be any leakage because the coherentsampling guarantees an exact integer number of input signalcycles.

Coherent sampling methods can be used for performingsingle-tone testing, because the nearby optimal input frequencycan be calculated for the single-frequency component. Whenseveral input tones are present, it is typically not guaranteedthat the tones are integer multiples of the FFTs fundamentalfrequency, and thus spectral leakage will occur in many multi-tone testing scenarios.

IV. PROPOSED APPROACH

An approach derived from the conventional coherent sam-pling technique is proposed in this paper for BIT applications.It follows the rules of coherent sampling, but instead ofdefining the near-optimal fundamental FFT frequency for asingle test tone, the coherent sampling frequency is calculatedbased on a fixed-frequency difference between the tones inmulti-tone test cases. Consequently, it circumvents spectralleakage problems associated with basic coherent samplingduring multi-tone testing. Both in the single-tone and multi-tone test cases, the method exploits the FFT engine that canbe codesigned with the requirements of a given built-in testapplication, which often leaves room to select test signalfrequencies in a way that the required on-chip FFT resourcesare minimized.

A. Single-Tone Testing

For single-tone test cases, the coherent sampling rule isrearranged and repeated to introduce the proposed approach

fsampCoh = fin · NFFT/Ncycle. (2)

The new sampling frequency, called coherent sampling fre-quency ( fsampCoh) here, is calculated for the desired input testtone ( fin) with predefined values of FFT length (NFFT) and achosen integer number of cycles of the input signal (Ncycle).

B. Multi-Tone Testing

For multi-tone test cases, the FFT fundamental frequency,defined as � f , can be used in lieu of fin in (2), which repre-sents the effective resolution for suitable test tone frequencies.In a two-tone intermodulation test scenario, for example, thismeans that the spacing between the test tones must be equalto � f or an integer multiple of � f . This frequency resolutionin the spectrum can be set to the desired value for a particularon-chip testing application. With this predefined value for� f , the corresponding value of fsampCoh can be determinedaccording to

fsampCoh = � f · NFFT/Ncycle. (3)

The choice of test tones should abide by the following rules.1) Test tone frequencies should be at least less than half

of the value of fsampCoh in order to meet the Nyquistcriterion.

2) Test tones should be separated by integer multiplesof � f .

This approach not only eliminates the spectral leakageproblem but it also offers the following benefits when usedeither for single-tone or multi-tone testing.

1) Accurate spectral characteristics can be determined for anumber of higher order harmonics of the input test tone.

2) Flexibility in choosing Ncycle and NFFT for the giveninput test tone fin. Any values for Ncycle and NFFTcan be used for spectral testing, provided that the ratioof NFFT and Ncycle is chosen such that the calculatedfsampCoh satisfies the Nyquist criteria for the given finand for the desired higher order harmonics of fin. Forexample, with Ncycle = 1, and NFFT = 16, fsampCohis 16 · fin; which means that the spectrum of fin andits harmonics until the seventh order can be preciselycalculated without aliasing and spectral leakage.

3) Accurate spectral characteristics are achievable evenwith short FFT length, for example, an FFT with16 points. Thus, the presented approach offers signif-icant savings in terms of area, power, and the requiredcomputational resources.

4) The noise levels with the discussed approach are gener-ally low, because spectral leakage is avoided based onthe coherent sampling characteristics.

In a production test environment, test signals with coherentinput frequencies can be generated arbitrarily with standardautomatic test equipment. Even though the proposed on-chipFFT engine could be utilized to reduce off-chip resourcerequirements and the number of required test outputs of thechip for test cost reduction, it is envisioned to be morevaluable during in-field testing and self-calibrations. On-chiptest signals can be generated by dedicated circuits for built-inself-test such as the 40-MHz generator in [30], or by sinusoidaloscillators with wide-frequency tuning range such as the 1- to25-MHz oscillator in [31]. Signal generation methods witha digital foundation are advantageous in ensuring coherencewith the proposed approach. For example, the 41-MHz signalgenerator in [32] contains a block that creates a stepwiseapproximation of a sine wave using a digital master clock( fclk) that is M = 16 times higher than the output frequency.This synthesized sine wave is subsequently processed by ananalog filter to generate a purer sinusoidal output with a67-dB spurious-free dynamic range. Since the signal gen-erator in [32] takes up only 0.1 mm2 in 0.35-μm CMOStechnology, it would be a good candidate for applications thatrequire the generation of coherent input signals on the chipat frequencies below 50 MHz. With such a signal generator,the master clock that produces fin(= fclk/M) in (2) can bedirectly derived from fsampCoh with a simple digital divider,or vice versa. Alternatively, the designer of the test mightdecide to use fsampCoh = fclk, which would be possiblewith NFFT = M = 16 and Ncycle = 1 in (2), for instance.

V. MATLAB SIMULATION RESULTS

In this section, we present the simulation results to comparethe conventional coherent sampling method with the proposedapproach. A single-tone test case and a two-tone test case arediscussed to highlight the differences.



Fig. 2. FFT with conventional coherent sampling (NFFT = 16). Spectrum ofthe input signal x(t) with a fundamental frequency component of 12.5 MHzand three harmonics.

A. Case 1: Single-Tone With High-Order Harmonics

Consider the following desired test input signal with afundamental frequency of fin and three harmonic components

x(t) = 105 · sin(2π · fin · t) + 103 · sin(2π · 2 fin · t)

+102 · sin(2π · 3 fin · t) + 10 · sin(2π · 4 fin · t). (4)

Let the above signal be sampled at a sampling rate of fsamp,and analyzed using a 16-point FFT.

1) Conventional Coherent Sampling Approach: Let fin =10 MHz, NFFT = 16, and fsamp = 200 MHz. Then � f =fsamp/NFFT = 12.5 MHz. Using (1), we find

Ncycle = fin · NFFT/ fsamp = 0.8 ∼= 1. (5)

Therefore, the nearest optimal input frequency ( finCoh) is

finCoh = Ncycle · fsamp/NFFT = 12.5 MHz. (6)

It should be noticed that the difference betweenfin and finCoh is 2.5 MHz. In traditional testing applications(e.g., testing of an ADC block with fixed sampling rate)it is normally feasible to generate a single test tone witha fundamental frequency of finCoh instead of fin. Fig. 2shows the spectrum of the coherent (12.5 MHz fundamental)input signal x(t) obtained using a 16-point FFT and theconventional coherent sampling technique. It can be observedthat the amplitudes at the signal’s fundamental and harmonicfrequencies are accurately represented by the magnitudes ofthe frequency bins at the corresponding multiples of finCoh.

2) Proposed Approach: With fin = 10 MHz, NFFT = 16,Ncycle = 1 from (5), and using (2) and (3), we get

fsampCoh = fin · NFFT/Ncycle = 160 MHz (7)

� f = fsampCoh · Ncycle/NFFT = 10 MHz. (8)

Notice that � f in this case is exactly 10 MHz, which allowsto calculate the spectrum precisely at the desired fundamentalinput frequency and its harmonics. This implies that the ADCsampling frequency and FFT rate must be selected accordingly,which exploits the design freedom in BIT and BIC scenarioswith dedicated ADC and FFT engine. The spectrum of x(t),calculated with the proposed approach, is displayed in Fig. 3,showing that the amplitudes of the fundamental and harmonic

Fig. 3. FFT with the proposed method (NFFT = 16). Spectrum of the inputsignal x(t) with a fundamental frequency component of 10 MHz and threeharmonics.

components are in exact agreement with those calculated usingconventional coherent sampling.

B. Case 2: Two-Tone Signal

1) Conventional Coherent Sampling Approach: Two-tonesignals are frequently used to characterize the intermodulationcomponents generated by second-order or third-order nonlin-earities of a CUT. The frequency separation between the twotest tones is typically much smaller than the frequency of eachtone. Hence, it is not feasible to satisfy coherent sampling bylocating the second test tone at a frequency that is a multipleof the first tone’s fundamental frequency. As demonstrated bysimulation in this section, the FFT spectrum will exhibit severeinaccuracies due to leakage when the input signal is comprisedof one tone that satisfies coherent sampling and another tonethat does not. Consider the input signal y(t) such that

y(t) = 105 · sin(2π · f1 · t) + 105 · sin(2π · f2 · t). (9)

Signal y(t) consists of two ideal test tones at frequenciesf1 and f2 without intermodulation components. After usingf1 = 12.5 MHz [i.e., equal to the coherent input frequency( finCoh) from (6)] and f2 = 13.5 MHz in the simulation,the spectrum in Fig. 4 was calculated with NFFT = 16 andfsamp = 200 MHz. From the signal contents at frequenciesother than f1 and f2, it is evident that spectral leakage occursbecause f2 does not satisfy the coherent sampling criterion.

It is not practical to increase NFFT due to the correspondingdie area requirement for the FFT implementation. Further-more, in the discussed example case, such an approach wouldrequire an approximately 10 times larger fsamp in order toobtain finCoh around 1 MHz based on (6), which would allowplacing the test tones at multiples of finCoh with a separationclose to 1 MHz. However, operating the on-chip ADC andFFT engine at 2 GHz would be impractical or consume toomuch power for many applications.

2) Proposed Approach: To avoid spectral leakage inmulti-tone BIT and BIC setups, the test tone frequencies canbe chosen such that they and their intermodulation products areinteger multiples of � f . A secondary consideration is the needto maintain a sampling rate low enough (e.g., < 200 MHz) foron-chip ADC and FFT engine implementations. The example



Fig. 4. Spectrum of the input signal y(t) with f1 = 12.5 MHz (coherent)and f2 = 13.5 MHz (not coherent).

in this section demonstrates the benefit of selecting the sam-pling frequency based on the required frequency resolution(� f ) between tones. Consider the input signal z(t) such that

z(t) = 105 · sin(2π · f1 · t) + 105 · sin(2π · f2 · t)

+10 · sin(2π · [2 f1 − f2] · t)

+10 · sin(2π · [2 f2 − f1] · t) (10)

which consists of test tones at f1 and f2 as well as their third-order intermodulation (IM3) products (e.g., as at the outputof a CUT) during standard two-tone testing of a nonlinearanalog circuit. If � f = 1 MHz, then evaluation of (3) withNFFT = 16 and Ncycle = 1 yields

fsampCoh = � f · NFFT/Ncycle = 16 MHz. (11)

With this approach, frequency components up to fsampCoh/2 =8 MHz can be accurately measured, while the test tones haveto be selected at integer multiples of � f = 1 MHz to avoidleakage. Compared to the approach with increased NFFT, thismethod also has the advantage that the sampling frequency isnot several orders of magnitude larger than the frequenciesof interest. Instead, the band of interest spans fsampCoh/2,which is 8 MHz in this example, to show an FFT realizationthat would be useful for the characterization of basebandcircuits in wireless receivers or other low-frequency analogcircuits. Fig. 5 displays the corresponding spectrum of z(t)for a case in which f1 = 3 MHz and f2 = 5 MHz. The resultdemonstrates that the two input test tones and their third-orderintermodulation components are captured with high accuracyand without any spectral leakage.

C. ADC Resolution Requirement

The amplitudes of harmonic distortion (HD) and inter-modulation (IM) distortion components are influenced by thenumber of ADC bits n. For a single-tone signal digitized byan n-bit ADC with a unit step size, the amplitude of the pthharmonic component is defined as [33]

A p = δp1 ·2n−1 +∞∑

m=1

2

m · πJp

(2 · m · π · 2n−1

), if p is odd

(12)

Fig. 5. Spectrum of input signal z(t) with two test tones, f1 = 3 MHz andf2 = 5 MHz, and their third-order intermodulation products at 1 and 7 MHz,calculated using a 16-point FFT.

where A p = 0 if p is even, δpq = 0 if p �= q , δpq = 1 ifp = q , and Jp is the Bessel function. Quantization of a two-tone signal with frequency components f1 and f2 producesIM distortion products with the following amplitudes (Apq)and frequencies (Fpq) [33]:

Apq = δp1 · δq0 · 2n−2 + δp0 · δq1 · 2n−2

+∞∑

m=1

2

m · π Jp

(2 · m · π · 2n−2

)

·Jq

(2 · m · π · 2n−2

)(13)

Fpq = p · f1 + q · f2 (14)

where p and q are integers with an odd and positive sum. From(12) and (14), it can be shown that increasing the resolutionof an ideal ADC by 1 bit reduces the third-order HD (HD3)component by 9 dB and IM3 components by 12 dB.

Another factor influencing the accuracy of the spectralanalysis is the length of the FFT (NFFT). The digitizedsamples at the output of ADC contain the applied input signalswith their distortion components, the generated quantizationnoise and distortions, as well as ADC device noises. The finitesize of the FFT engine puts an additional limitation on theaccuracy of the spectral measurement in the presence of dis-tortion components. To achieve high accuracy with an FFT thatis preceded by an ADC, a fine frequency resolution is desired,suggesting the use of a large number of FFT points [34].To avoid excessive area and power consumption due to a large-sized FFT engine, the selections of ADC resolution and FFTlength have to be made under the given accuracy requirementsand design constraints.

MATLAB simulations were performed to show the impactof finite ADC resolution and FFT length on HD and IMcomponents. The ADC was modeled with an n-bit quantizer,and the proposed approach described in Section IV wasused to calculate the power spectrum of the signal. Fig. 6shows the IM3 power in decibels relative to the carrier (i.e.,IM3 power magnitude in decibels below the fundamentalcomponents from a two-tone test) as the FFT length and theADC resolution are swept from 16 to 2048 points and from4 to 14 bits, respectively. The IM3 power is 57 dBc whena 10-bit ADC resolution is combined with a 16-point FFT,as annotated in Fig. 6. If necessary, higher accuracy can beachieved by increasing the FFT length. As shown in Fig. 6,



Fig. 6. IM3 versus FFT length (NFFT) and ADC resolution (n-bits) from atwo-tone test with f1 = 3 MHz and f2 = 5 MHz.

TABLE I

THEORETICAL AND SIMULATED IM3 (in dBc) FROM A TWO-TONE TEST

WITH f1 = 3 MHz, f2 = 5 MHz, AND fIM3 = 1 MHz

NFFTn-bit ADC

8 9 10 11 12 13 14

24 44.57 50.80 57.22 64.09 72.11 84.3 84.5

25 47.56 55.31 62.8 72.72 85.17 92.5 86.18

26 48.16 56.54 69.67 75.18 85.43 91.34 95.73

27 52.14 65.03 77.67 90.44 96.35 90.68 104.3

215 70.88 78.68 89.12 100.60 101.32 107.1 114.4

∞ 96.33 108.37 120.41 132.45 144.49 156.5 168.5

TABLE II

THEORETICAL AND SIMULATED HD3 (in dBc) FROM A SINGLE-TONE

TEST WITH f0 = 3 MHZ

NFFTn-bit ADC

8 9 10 11 12 13 14

24 56.38 64.67 72.24 78.17 83.31 86.42 92.91

215 71.67 80.71 89.26 98.92 106.99 113.49 120.4

∞ 72.24 81.27 90.30 99.34 108.37 117.40 126.4

the simulated power of the same IM3 component is 85 dBcwith 10-bit ADC resolution but with a 2048-point FFT.

To give additional insights into the tradeoffs of ADCresolution and FFT length, theoretical values (ADC distortiononly, NFFT = ∞) obtained from (12) and (14) were comparedwith simulated results using NFFT = 24, 25, 26, 27, and 215.Tables I and II summarize the IM3 and HD3 components(in decibels relative to the carrier) for the respective two-tone and single-tone test cases presented in Section V. Noticethat only the test tones were applied, such that the listedIM3 and HD3 levels represent the accuracy limit of theADC–FFT combination under the given conditions. For a10-bit ADC, HD3 levels down to 72 dB below the fundamentalcan be extracted with NFFT = 24. In contrast, the selectionof NFFT = 215 would allow to identify HD3 down to 89 dB,which is close to the 90 dBc theoretical HD3 generated by the10-bit ADC.

An important metric for ADC nonlinearity is differen-tial nonlinearity (DNL), which can be in the range of

TABLE III

SIMULATED IM3 (in dBc) WITH DNL ERROR (FROM A TWO-TONE TEST

WITH f1 = 3 MHZ, f2 = 5 MHZ, fIM3 = 1 MHZ, AND NFFT = 24)

DNL(LSB)

n-bits ADC

7 8 9 10 11 12 13 14

41.45 44.57 50.80 57.22 64.09 72.11 84.3 84.5

±0.3 (μ) 49.75 53.15 59.52 65.32 66.30 75.04 102.04 86.44

±0.3 (σ ) 4.64 4.92 5.29 4.86 0.90 1.92 22.95 1.79

±0.5 (μ) 48.70 52.90 58.10 70.40 70.98 75.59 93.98 87.69

±0.5 (σ ) 5.01 5.45 5.17 9.52 7.73 2.79 8.58 4.48

TABLE IV

SIMULATED IM3 (in dBc) WITH WIDEBAND NOISE (FROM A TWO-TONE

TEST WITH f1 = 3 MHZ, f2 = 5 MHZ, fIM3 = 1 MHZ, AND NFFT = 24)

n bits 9 10 11 12 13 14 15

ENOB 8 9 10 11 12 13 14

μ 57.76 62.30 71.23 75.34 83.95 90.77 94.64

σ 4.50 3.81 6.36 4.00 5.69 5.47 6.79

TABLE V

SIMULATED IM3 (in dBc) WITH WIDEBAND NOISE AND ±0.5-LSB DNL

ERROR (FROM A TWO-TONE TEST WITH f1 = 3 MHZ, f2 = 5 MHZ,

fIM3 = 1 MHZ, AND NFFT = 24)

n bits 9 10 11 12 13 14 15

ENOB 8 9 10 11 12 13 14

μ 60.72 63.40 75.54 75.61 81.61 89.10 96.82

σ 5.76 4.26 7.67 4.79 5.00 6.76 5.93

±0.09 to ±0.5 LSB, for example [35], [36]. To assess theimpact of the ADC’s static nonlinearity, simulations were per-formed with DNL errors of ±0.3 and ±0.5 LSB by generatingrandom offsets of each reference voltage level with a Gaussiandistribution such that the DNL value is equal to three timesthe standard deviation (σ ). Table III summarizes the mean(μ) and the standard deviation (σ ) of the IM3 componentsfrom 20 simulations for the two DNL cases with NFFT = 24.Assuming a 10-bit ADC with ±0.3-LSB DNL, a mean IM3of 65.32 dBc with 4.86-dB standard deviation is observed.This suggests that the inherent linearity of the ADC and FFTcombination would allow to measure IM3 values up to 50 dBc(3 · σ lower than the mean) in 99.8% of the cases.

To capture the effect of noise on the IM3 characterizationcapability, white noise was introduced at the ADC input inMATLAB simulations such that the ADC’s effective numberof bits (ENOB) reduces by 1 bit. The mean (μ) and thestandard deviation (σ ) of the measured IM3 component from20 simulations are listed in Table IV. The results indicate thatIM3 values up to 52 dBc (= μ − 3σ ) can be extracted with99.8% confidence using NFFT = 24 and an ADC having anENOB of 10 bits. As shown in Table V, in presence of bothDNL of ±0.5 LSB and wideband noise, IM3 values up to52.5 dBc (= μ − 3σ ) can be accurately determined with a16-point FFT and ENOB = 10 bit. The results suggest thatthe presence of DNL and noise causes distribution of powerover more frequency bins, which leads to increased variationof the IM3 measurement capability but with a higher mean.



DNL of the ADC causes distribution of power over frequencybins due to the generation of more intermodulation productsthat depend on the random DNL variations across the referencevoltages. Generally, nonzero DNL results in less power at theIM3 frequencies but higher power at other frequencies due tothe generation of different intermodulation products. However,the power levels in all frequency bins exhibit higher variationswith nonzero DNL.

To investigate the effect of ADC bandwidth limitation on theIM3 characterization capability, a third-order low-pass filter(LPF) with a cutoff frequency of 3.37 MHz was placed infront of an ideal behavioral model of a 10-bit ADC to modelfrequency limitation during Spectre simulations in Cadencewith a 16-MHz sampling frequency. The characteristics ofthe LPF are such that it has an ENOB of approximately10 and 6 bits for fin ≤ 3 MHz and for fin = 7 MHz,respectively. Furthermore, the ENOB with input frequenciesof 5 and 6 MHz is approximately the same (ENOB ≈ 7bits), which is why they were selected for a two-tone testsimulation. After taking a 16-point FFT of the ADC output,the IM3 components of 50.96 and 55.64 dBc were present atthe frequencies of 4 and 7 MHz, respectively. This estimatedtest accuracy at frequencies with an ENOB ≈ 7 bits deviatesby 1–7 dB from the IM3 limits for the 7-bit ADC cases withDNLs in Table III. Note that the test tones experience differentattenuations and phase shifts because the ADC bandwidthlimitation is modeled with a third-order LPF, which impactsthe IM3 limits. Nevertheless, the result indicates that the ADCENOB dictates the test accuracy as in the previously discussedexample with wideband noise.

For on-chip implementation, it is desirable to achieve smallarea and power with sufficient accuracy. The combinationof a 10-bit ADC and 16-point FFT was chosen for theimplementation example discussed in Section VI, becauseit provides appropriate accuracy for various BIT scenarios.Efficient ADCs can be designed with 10–80 MS/s for theanticipated applications. For example, a 10-bit ADC with40-MS/s sampling rate implemented in 65-nm CMOS tech-nology was reported in [37] with an active area of 0.06 mm2

and power dissipation of 1.21 mW.

D. Selection of NFFT and the ADC Resolution

Based on the analysis presented in Section V-C, the follow-ing procedure can be adopted to aid in selecting the appropriateADC resolution and the FFT length.

Step 1: Identify the required accuracy of the IM3 (HD3)measurement (in decibels relative to the carrier). For example,a transistor-level simulation of a CUT using test tones of aspecified amplitude will result in a certain output IM3 thatshould be lower than the IM3 limits in the tables.

Step 2: Based on Table I, select the appropriate ADCresolution and the FFT length (NFFT). If one of the twois too high for efficient on-chip implementation based onavailable resources, then the test tone amplitudes in step 1 canbe increased to obtain lower output IM3 (in decibels relativeto the carrier), relaxing the requirements for the on-chip testresources.

Fig. 7. Radix-2 16-point FFT processor (bold lines: buses with multiplebits).

Step 3: Define the desired frequency resolution (� f ) inthe output spectrum depending on the application-specificrequirements and available test tone generation circuitry.

Step 4: Using (2), determine the coherent sampling fre-quency ( fsampCoh). Note that fsampCoh should be chosensuch that the desired IM3 (or HD3) components fall withinfsampCoh/2.

Step 5: Choose the input test tone frequencies ( f1, f2) asan integer multiple of the frequency resolution (� f ).

VI. IMPLEMENTATION EXAMPLE

A radix-2 16-point FFT engine was implemented to deter-mine the spectral characteristics of the signal generated at theoutput of an ADC. The FFT engine is based on the standarddecimation-in-time algorithm. It is designed as a serialized,streaming I/O FFT block that accepts streaming complex inputand generates streaming complex output continuously withevery clock cycle after an initial latency of 34 clock cycles,where each output corresponds to a frequency bin. The inputand the output data streams are represented in 2s complementQ10.4 and Q13.4 format, respectively. The output of the10-bit ADC represents the integer portion of the input data,where four additional fractional bits are appended to achievea resolution of −84 dBc. The integer portion of the outputdata is comprised of 13 bits to capture the overflow that isgenerated during the FFT computation.

Fig. 7 shows the block diagram of the FFT engine, whereIin, Iout and Qin, Qout represent the real and the imaginaryparts of the input and the output data streams, respectively. Theinput data are passed to the FFT logic unit and the processeddata are carried to the butterfly unit for further arithmeticoperations or to the DualPort RAM unit for storage in theregisters. The functions of the FFT logic unit are to reorderthe output bins of the FFT engine, to calculate addressesfor the butterfly unit, and to count the delay for feedbackregisters. Its outputs are the twiddle indexes, addresses for theDualPort RAM, calculated real and imaginary parts of data,and FFT outputs (Iout, Qout). The twiddle indexes are passed



TABLE VI

RESULTS FROM A TWO-TONE TEST: CALCULATED FFT OF THE INPUT SIGNAL (65 536 POINTS) VERSUS

OUTPUT OF THE 16-POINT FFT ENGINE

Frequency(MHz)

20 · log10(| Magnitude |)ActualInput

(dBFS)

CalculatedInput

(dBFS)

Post-LayoutOutput(dBFS)

ActualIM3

(dBc)

CalculatedIM3

(dBc)

Post-LayoutOutput

IM3 (dBc)f1, f2 = 3, 5 −11.37 −11.38 −11.36 – – –

fIM3 = 1 −61.37 −61.31 −62.08 50.00 49.93 50.72

fIM3 = 7 −61.37 −61.36 −60.04 50.00 49.98 48.68

Fig. 8. Layout of the FFT engine (0.73 mm2 in 45-nm CMOS technology).

to the twiddle table unit, where the sine and cosine valuesare selected for the calculations inside the butterfly unit. Theoutputs of the butterfly unit and the DualPort RAM are twopairs of real and imaginary numbers that are calculated inparallel. To reduce hardware complexity, the DualPort RAMserves as feedback delay resistors, and a minimized butterflyunit is used.

The FFT engine was implemented in Verilog HDL and syn-thesized to the gate level netlist with Cadence RTL compilerusing the publicly available 45-nm PDK [38]. The generatedgate level netlist was ported to the Cadence Encounter toolto complete the physical layout of the FFT engine and toevaluate the overall area and power requirements The layoutis displayed in Fig. 8. It occupies a total chip area of around0.073 mm2 with 87% density in 45-nm CMOS technology.The total estimated power dissipation for 16 MHz 16-pointFFT computations at 1.1 V supply voltage is 6.47 mW.

From Table I, it should be noted that an ideal two-toneinput signal when quantized using a 10-bit ADC contains anIM3 component at 57.2 dBc in the output spectrum obtainedwith a 16-point FFT. Thus, to accurately determine the IM3components of an input signal from a CUT, the third-orderintermodulation components should be larger than the intrinsiclinearity limitation of the chosen combination of the ADCresolution and the number of FFT points, such that IM3< 57.3 dBc. As an example, a two-tone test signal representedby (10) but with a known IM3 component of 50 dBc was

Fig. 9. Output spectrum from post-layout simulation, showing the two testtones ( f1 = 3 MHz, f2 = 5 MHz) and their IM3 products at 1 and 7 MHz

applied during the post-layout simulation of the 16-point FFTengine implementation together with a 10-bit ADC (Verilogmodel). The extracted parasitic resistances and the capaci-tances were included in the post-layout simulation. The outputbit streams from the post-layout simulation were importedto MATLAB to plot the resulting output spectrum that isshown in Fig. 9. Table VI compares the post-layout simulationresults of the implemented FFT engine, with the FFT of theinput signal to the ADC obtained with the Cadence calculatorusing 65 536 points. The columns named Actual Input listthe differences (in decibels relative to the carrier) betweenthe input components specified for the signal sources at thefrequencies of interest relative to the full-scale input range ofthe ADC. As a reference for comparison to the post-layout16-point FFT results, the “Calculated Input” columns includethe corresponding frequency component values obtained forthe same input with an ideal 65 536-point FFT. An error of lessthan ±0.02 dB is observed for the fundamental components at3 and 5 MHz, whereas the applied 50-dBc IM3 components at1 and 7 MHz are captured with an error of 0.72 and 1.32 dB,respectively. The post-layout FFT engine simulation resultsindicate that the chosen combination of a 10-bit ADC and a16-point FFT in this example is suitable to accurately deter-mine the IM3 components of ≤ 50 dBc.

VII. CONCLUSION

An accurate FFT-based analysis approach was introducedfor on-chip spectral characterization of multi-tone signals. Theproposed approach was derived from the coherent samplingmethod. It was demonstrated that it allows the designer to



select the appropriate test signal frequencies, ADC resolution,and FFT length to achieve the desired frequency resolutionin the output spectrum without spectral leakage. The methodavoids the use of a large number of FFT points to minimize therequired on-chip FFT resources for area- and power-efficientbuilt-in testing applications. Post-layout simulation results ofan FFT implementation in standard 45-nm CMOS technologyshowed the feasibility of the approach. For a 16-MHz 16-pointFFT computation, the implemented FFT engine consumes anestimated power of 6.47 mW with 1.1 V supply and occupiesan area of 0.073 mm2. A methodology was presented todetermine the suitable ADC resolution and the FFT length toobtain a required accuracy. For example, when combined witha 10-bit ADC, the simulated error for IM3 extraction from theoutput spectrum of the 16-point FFT is within 1.5 dB for IM3components ≤ 50 dBc.

REFERENCES

[1] B. Murmann, “Digitally assisted analog circuits,” IEEE Micro, vol. 26,no. 2, pp. 38–47, Mar.–Apr. 2006.

[2] D. Kaczman, M. Shah, M. Alam, M. Rachedine, D. Cashen, L. Han,and A. Raghavan, “A single–chip 10-band WCDMA/HSDPA 4-bandGSM/EDGE SAW-less CMOS receiver with DigRF 3G interfaceand +90 dBm IIP2,” IEEE J. Solid-State Circuits, vol. 44, no. 3,pp. 718–739, Mar. 2009.

[3] J.-Y. Ryu, B. C. Kim, and I. Sylla, “A new low-cost RF built-in self-test measurement for system-on-chip transceivers,” IEEE Trans. Instrum.Meas., vol. 55, no. 2, pp. 381–388, Apr. 2006.

[4] C.-H. Liao and H.-R. Chuang, “A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver,”IEEE Microw. Wirel. Compon. Lett., vol. 13, no. 12, pp. 526–528,Dec. 2003.

[5] N. Ahsan, J. Dabrowski, and A. Ouacha, “A self-tuning technique foroptimization of dual band LNA,” in Proc. Eur. Conf. Wirel. Technol.,Oct. 2008, pp. 178–181.

[6] S. Rodriguez, A. Rusu, L.-R. Zheng, and M. Ismail, “CMOS RFmixer with digitally enhanced IIP2,” Electron. Lett., vol. 44, no. 2,pp. 121–122, Jan. 2008.

[7] H.-K. Cha, S.-S. Song, H.-T. Kim, and K. Lee, “A CMOS harmonicrejection mixer with mismatch calibration circuitry for digital TV tunerapplications,” IEEE Microw. Wirel. Compon. Lett., vol. 18, no. 9,pp. 617–619, Sep. 2008.

[8] S. Rodriguez, S. Tao, M. Ismail, and A. Rusu, “An IIP2 digital calibra-tion technique for passive CMOS down-converters,” in Proc. IEEE Int.Symp. Circuits Syst., Jun. 2010, pp. 825–828.

[9] M. Mobarak, M. Onabajo, J. Silva-Martinez, and E. Sánchez-Sinencio,“Attenuation-predistortion linearization of CMOS OTAs with digital cor-rection of process variations in OTA-C filter applications,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 351–367, Feb. 2010.

[10] A. P. Jose, K. A. Jenkins, and S. K. Reynolds, “On-chip spectrumanalyzer for analog built-in self test,” in Proc. IEEE VLSI Test Symp.,May 2005, pp. 131–136.

[11] A. Valdes-Garcia, F. A.-L. Hussien, J. Silva-Martinez, and E. Sánchez-Sinencio, “An integrated frequency response characterization systemwith a digital interface for analog testing,” IEEE J. Solid-State Circuits,vol. 41, no. 10, pp. 2301–2313, Oct. 2006.

[12] H.-M. Chang, M.-S. Lin, and K.-T. Cheng, “Digitally-assisted analog/RFtesting for mixed-signal SoCs,” in Proc. 17th IEEE Asian Test Symp.,Nov. 2008, pp. 43–48.

[13] D. Han, B. S. Kim, and A. Chatterjee, “DSP-driven self-tuning ofRF circuits for process-induced performance Variability,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 305–314,Feb. 2010.

[14] M. Onabajo, J. Silva-Martinez, F. Fernandez, and E. Sánchez-Sinencio,“An on-chip loopback block for RF transceiver built-in test,” IEEETrans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 6, pp. 444–448,Jun. 2009.

[15] H. Shin, J. Park, and J. A. Abraham, “Spectral predictionfor specification-based loopback test of embedded mixed-signal circuits,” J. Electron. Test., vol. 26, no. 1, pp. 73–86,Jan. 2010.

[16] I. Vassiliou, K. Vavelidis, T. Georgantas, S. Plevridis, N. Haralabidis,G. Kamoulakos, C. Kapnistis, S. Kavadias, Y. Kokolakis, P. Merakos,J. C. Rudell, A. Yamanaka, S. Bouras, and I. Bouras, “A single-chipdigitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for802.11a wireless LAN,” IEEE J. Solid-State Circuits, vol. 38, no. 12,pp. 2221–2231, Dec. 2003.

[17] M. J. Barragan, R. Fiorelli, D. Vazquez, A. Rueda, and J. L. Huertas,“On-chip characterisation of RF systems based on envelope responseanalysis,” Electron. Lett., vol. 46, no. 1, pp. 36–38, Jan. 2010.

[18] W. Sansen, “Distortion in elementary transistor circuits,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 46, no. 3, pp. 315–325, Mar. 1999.

[19] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A 1-GS/s FFT/IFFT processorfor UWB applications,” IEEE J. Solid-State Circuits, vol. 40, no. 8,pp. 1726–1735, Aug. 2005.

[20] Y. Chen, Y.-C. Tsao, Y.-W. Lin, C.-H. Lin, and C.-Y. Lee, “An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications,”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 146–150,Feb. 2008.

[21] C.-T. Lin, Y.-C. Yu, and L.-D. Van, “A low-power 64-point FFT/IFFTdesign for IEEE 802.11a WLAN application,” in Proc. IEEE Int. Symp.Circuits Syst., May 2006, pp. 4523–4526.

[22] P. Carbone, E. Nunzi, and D. Petri, “Windows for ADC dynamic testingvia frequency-domain analysis,” IEEE Trans. Instrum. Meas., vol. 50,no. 6, pp. 1571–1576, Dec. 2001.

[23] D. Belega, M. Ciugudean, and D. Stoiciu, “Choice of the cosine-classwindows for ADC dynamic testing by spectral analysis,” Measurement,vol. 40, no. 4, pp. 361–371, May 2007.

[24] IEEE Standard for Digitizing Waveform Recorders, IEEE Standard1057–2007, Apr. 2008.

[25] IEEE Standard for Terminology and Test Methods for Analog to DigitalConverters, IEEE Standard 1241–2010, Jan. 2011.

[26] M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Testand Measurement. New York, USA: Oxford Univ. Press, 2000.

[27] J. A. Mielke, “Frequency domain testing of ADCs,” IEEE Des. TestComput., vol. 13, no. 1, pp. 64–69, Mar. 1996.

[28] Selecting the Optimum Test Tones and Test Equipment for SuccessfulHigh-Speed ADC Sinewave Testing, Maxim Integrated, San Jose, CA,USA, 2002.

[29] J. J. Blair, “Selecting test frequencies for sinewave tests of ADCs,” inProc. IEEE Instrum. Meas. Technol. Conf., May 2002, pp. 189–193.

[30] B. Dufort and G. W. Roberts, “On-chip analog signal generation formixed-signal built-in self-test,” IEEE J. Solid-State Circuits, vol. 34,no. 3, pp. 318–330, Mar. 1999.

[31] J. Galan, R. G. Carvajal, A. Torralba, F. Munoz, and J. Ramirez-Angulo,“A low-power low-voltage OTA-C sinusoidal oscillator with a largetuning range,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2,pp. 283–291, Feb. 2005.

[32] M. J. Barragán, D. Vázquez, A. Rueda, and J. L. Huertas, “On-chipanalog sinewave generator with reduced circuitry resources,” in Proc.IEEE Int. Midwest Symp. Circuits Syst., Aug. 2006, pp. 638–642.

[33] N. Blachman, “The intermodulation and distortion due to quantization ofsinusoids,” IEEE Trans. Acoust., Speech Signal Process., vol. 33, no. 6,pp. 1417–1426, Dec. 1985.

[34] J. Duan and D. Chen, “ADC spectral performance measurement uncer-tainty in DFT method,” in Proc. IEEE Electro/Inf. Technol., May 2011,pp. 1–4.

[35] C. R. Grace, P. J. Hurst, and S. H. Lewis, “A 12-bit 80-MSample/spipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, May 2005.

[36] Y.-S. Shu, W.-M. Lee, B.-S. Song, M. Kyung, and B. Pain, “A 10∼ 15-bit 60-MS/s floating-point ADC with digital gain and offsetcalibration,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2356–2365,Sep. 2009.

[37] M. Furuta, M. Nozawa, and T. Itakura, “A 10-bit, 40-MS/s, 1.21 mWPipelined SAR ADC Using Single-Ended 1.5-bit/cycle conversion tech-nique,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1360–1370,Jun. 2011.

[38] Open-Access 45 nm PDK. (2011). VLSI Computer ArchitectureResearch Group, Oklahoma State University, Stillwater, OK, USA[Online]. Available: http://vlsiarch.ecen.okstate.edu/flows/



Hari Chauhan (S’12) received the M.S degree incomputer engineering from Northeastern University,Boston, MA, USA, in 2011, where he is currentlypursuing the Ph.D. degree in electrical engineering.

His current research interests include digital sys-tem design, digitally assisted analog circuit design,low-power VLSI design, and RF integrated circuitdesign.

Yongsuk Choi received the B.S degree in electricaland electronics engineering from Chung-Ang Uni-versity, Seoul, South Korea, in 2011. He is currentlypursuing the Ph.D. degree in electrical engineeringfrom Northeastern University, Boston, MA, USA.

His current research interests include high speed,low-power VLSI design, and analog VLSI circuitdesign.

Marvin Onabajo (S’01–M’10) received the B.S.degree (summa cum laude) from The University ofTexas at Arlington, Arlington, TX, USA, in 2003,and the M.S. and Ph.D. degrees from Texas A&MUniversity, College Station, TX, USA, in 2007 and2011, respectively, all in electrical engineering.

He was an Electrical Test/Product Engineer withIntel Corp., Hillsboro, OR, USA, from 2004 to2005. He was a Design Engineering Intern with theBroadband RF/Tuner Development Group, Broad-com Corp., Irvine, CA, USA, in 2011. He is an

Assistant Professor with the Electrical and Computer Engineering Department,Northeastern University, Boston, MA, USA. His current research interestsinclude analog/RF and mixed-signal IC design, built-in testing, data convert-ers, and on-chip sensors for thermal monitoring.

In-Seok Jung (S’11) received the B.S. and M.S.degrees in electronic engineering and semiconduc-tor engineering from Chungbuk National University,Cheongju-si, South Korea, in 2007 and 2009, respec-tively. He is currently pursuing the Ph.D. degree inelectrical engineering from Northeastern University,Boston, MA, USA.

His current research interests include high speed,low-power VLSI design, analog VLSI circuit design,and power ICs.

Yong-Bin Kim (S’88–M’88–SM’00) received theB.S. degree in electrical engineering from SogangUniversity, Seoul, Korea, the M.S. degree in elec-trical engineering from the New Jersey Instituteof Technology, Newark, NJ, USA, and the Ph.D.degree in electrical and computer engineering fromColorado State University, Fort Collins, CO, USA,in 1982, 1989, and 1996, respectively.

He was a Technical Staff Member with Elec-tronics and Telecommunications Research Institute,Daejeon, Korea, from 1982 to 1987. He was a

Senior Design Engineer with Intel Corp., Hillsboro, OR, USA, from 1990to 1993, involved in microcontroller chip design and Intel Pentium Promicroprocessor chip design. He was a Technical Staff Member with HewlettPackard Company, Fort Collins, from 1993 to 1996, involved in HP PA-8000 RISC microprocessor chip design. He was a Staff Engineer with SunMicrosystems, Palo Alto, CA, USA, from 1996 to 1998, involved in 1.5GHz Ultra Sparc5 CPU chip design. He was an Assistant Professor withthe Department of Electrical Engineering, University of Utah, Salt Lake City,UT, USA, from 1998 to 2000. He is currently an Associate Professor with theDepartment of Electrical and Computer Engineering, Northeastern University,Boston, MA, USA. His current research interests include low-power analogand digital circuit design as well as high-speed low-power very large-scaleintegrated circuit design and methodology.

accurate and efficient on chip spectral analysis

Education