a solid-state disk simulator ... · more data-intensive applications april 29, 2009 design...
TRANSCRIPT
A Solid-State Disk Simulator for Quantitative Performance Analysisfor Quantitative Performance Analysis
and Optimization
연세대학교 전기전자공학부
정 의 영정 의 영
April 29 2009Design
TechnologyLaboratory 381
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 382
Why SSD
Nice features compared to HDDSmall form factorSmall form factorShock resistanceLi ht i htLight weightLow power consumptionHi h fHigh performance
Worth to pay moreNAND flash is getting cheaperMore data-intensive applications
April 29 2009Design
TechnologyLaboratory 383
NAND Flash Memory Market Forecast
NAND becomes dominant in memory marketmarket
Source WSTSrsquo07 iSuppli(lsquo08~) SEC(lsquo08~)
April 29 2009Design
TechnologyLaboratory 384
SSD Market Forecast
Currently the market is in the opening stagestageNote PC is the major market
April 29 2009Design
TechnologyLaboratory 385
Source iSuppli (June 2008)
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 382
Why SSD
Nice features compared to HDDSmall form factorSmall form factorShock resistanceLi ht i htLight weightLow power consumptionHi h fHigh performance
Worth to pay moreNAND flash is getting cheaperMore data-intensive applications
April 29 2009Design
TechnologyLaboratory 383
NAND Flash Memory Market Forecast
NAND becomes dominant in memory marketmarket
Source WSTSrsquo07 iSuppli(lsquo08~) SEC(lsquo08~)
April 29 2009Design
TechnologyLaboratory 384
SSD Market Forecast
Currently the market is in the opening stagestageNote PC is the major market
April 29 2009Design
TechnologyLaboratory 385
Source iSuppli (June 2008)
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Why SSD
Nice features compared to HDDSmall form factorSmall form factorShock resistanceLi ht i htLight weightLow power consumptionHi h fHigh performance
Worth to pay moreNAND flash is getting cheaperMore data-intensive applications
April 29 2009Design
TechnologyLaboratory 383
NAND Flash Memory Market Forecast
NAND becomes dominant in memory marketmarket
Source WSTSrsquo07 iSuppli(lsquo08~) SEC(lsquo08~)
April 29 2009Design
TechnologyLaboratory 384
SSD Market Forecast
Currently the market is in the opening stagestageNote PC is the major market
April 29 2009Design
TechnologyLaboratory 385
Source iSuppli (June 2008)
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
NAND Flash Memory Market Forecast
NAND becomes dominant in memory marketmarket
Source WSTSrsquo07 iSuppli(lsquo08~) SEC(lsquo08~)
April 29 2009Design
TechnologyLaboratory 384
SSD Market Forecast
Currently the market is in the opening stagestageNote PC is the major market
April 29 2009Design
TechnologyLaboratory 385
Source iSuppli (June 2008)
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
SSD Market Forecast
Currently the market is in the opening stagestageNote PC is the major market
April 29 2009Design
TechnologyLaboratory 385
Source iSuppli (June 2008)
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
To boost up the market growth
Reduce the disadvantagesHopefully by Multi level cell (MLC) NANDHopefully by Multi-level cell (MLC) NANDbull Price
ndash Integrate more bits to a single cellIntegrate more bits to a single cellbull Reliability
ndash Improve the noise immunity by a novel ECC schemebull Performance
ndash Hide the poor characteristics by the smart controller
Enhance the strengthsHigher performancebull Controller Host IFbull Especially for random read write
d hApril 29 2009
DesignTechnology
Laboratory 38
And others6
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Why SSD simulator
For the challenges in the previous slideNeed a tool for analysis and explorationNeed a tool for analysis and exploration
System-level simulatorHost computer + SSDbull Host computer architecture
M hi hbull Memory hierarchybull Interaction between File system and SSD
SSD sim latoSSD simulatorArchitecturel h l i ( )Flash Translation Layer (FTL)
Also their combined effects
April 29 2009Design
TechnologyLaboratory 387
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Purpose of this talk
Not to propose a new architectureN t t f FTL l ithNot to propose a fancy FTL algorithm
But to propose a method for the analysis and exploration of SSD in a quantitative p qmanner
April 29 2009Design
TechnologyLaboratory 388
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 389
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Simulator (I)
System-level simulatorNeed to model both the host and SSDNeed to model both the host and SSDNeed to raise the abstraction levelbull For simulation speedbull For simulation speedbull But loosing accuracy
Not actively researchedNot actively researched
SSD simulatorN d t l th i t l hit t f SSDNeed to explore the internal architecture of SSDMust consider both the HW and SW features
C l t l l ld b d h ibull Cycle-accurate level would be a good choice
Not many works satisfy the above requirements
April 29 2009Design
TechnologyLaboratory 3810
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Simulator (II)
Merits of SSD SimulatorQuantitative performance analysisQuantitative performance analysisHW amp SW co-simulation FTL h id i HW h t i tiFTL research considering HW characteristicsHW optimization for specific algorithms
Real board is another solution but hellipHard to prepareLess flexibilityLess controllable
April 29 2009Design
TechnologyLaboratory 3811
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
FTL perspective (I)
Purpose of FTLImprove flash memory access patternImprove flash memory access pattern
Typical Flash characteristicsbull Operation unit
bull read write (program) page unitbull erase block unit
bull Erase-before-Writebull Asymmetric Operation Latenciesbull Erase Count Limitation
bull SLC (~100000) MLC (~10000)
H d HW i d d t t iHave used HW-independent metricsHard to evaluate FTL for various architectures
April 29 2009Design
TechnologyLaboratory 38
Cannot consider its overhead12
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
FTL perspective (II)
HW-dependent FTL OperationsM ibull Mappingbull Logical Address rarr Physical Addressbull Block level Page level Hybridbull Block-level Page-level Hybrid
bull Garbage Collectionbull Merge Switch Partial Fullbull Merge Switch Partial Full
bull Interleavingbull Wear Leveling H t S tbull Wear Leveling
bull Greedy Rate-Limiting Migration
bull Bad Block Management FTL
SectorWrite
SectorRead
Host System
bull Bad Block Managementbull Meta Databull Power-Off Recovery
Page Program
PageRead
BlockErase
NAND Flash Memory
April 29 2009Design
TechnologyLaboratory 38
bull Power-Off Recovery
13
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
FTL perspective (III)Various FTL algorithms
Mostly focus on reducing merging frequenciesL bl k b d FTL (BAST)bull Log-block based FTL (BAST)
ndash Log block is organized by an out-of-place schemebull FAST Fully-Associative Sector Translation
ndash Log block is shared by all the data blocksg ybull Super-block based FTL
ndash A set of adjacent logical blocks that share data blocks and log blocksbull LAST Locality-Aware Sector Translation
ndash Using Locality Detectorndash Using Locality Detectorndash Reduces merge by partitioning Hot Cold log blocks for random writes
bull μ-FTL Minimally Updated FTLndash Using μ-Tree amp Bitmap cache
FTL performance MetricsRPE countAll metrics are HW independentOperation overhead is not consideredLimited HW architectures
bull Single channel and single way
April 29 2009Design
TechnologyLaboratory 38
bull Ignores memory organization
14
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
HW perspective
Major topicsChannel Way optimizationChannel Way optimizationDRAM cache buffer managementH b id Fl hHybrid Flash memory arraysbull MLC + SLC
Apparently closely related to FTLN t k h t h d thi i tNot many works have touched this point
April 29 2009Design
TechnologyLaboratory 3815
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3816
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Simulation Environment
SoC DesignerTM (MaxSimTM )System-Level Modeling Tool by Carbon DesignSystem-Level Modeling Tool by Carbon Design SystemsFast platform builder using SystemCp g ybull Simulation speed over 200kcpsbull Easy to build various architectures
C t Lib i th lComponent Library is another plusbull Core Bus Memory Peripheral hellipbull Cycle Accuracybull Cycle Accuracy
HW amp SW co-simulationGUI - Monitor Profile WaveformGUI Monitor Profile WaveformRTL co-simulation
April 29 2009Design
TechnologyLaboratory 3817
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Modeling strategies
Cycle-Accurate ModelingEnough for quantitative performance analysisEnough for quantitative performance analysis
FlexibilityParameterization of important variables
Simulation speed over 200kcpsSW engineers will complain butHW engineers will appreciate
Trace Driven SimulationPerformance analysis with Real workloadsPerformance analysis with Real workloadsSynthetic workloads for specific cases
April 29 2009Design
TechnologyLaboratory 3818
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Target Architecture
Manual
Library
April 29 2009Design
TechnologyLaboratory 3819
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Component Modeling
SATA interfaceTrace inputTrace input
SRAM amp ControllerFTL code map table
SDRAM amp ControllerCache bufferDecoder Channel striping
NAND Flash Memory amp ControllerControls flash accessesControls flash accesses Way interleaving
April 29 2009Design
TechnologyLaboratory 3820
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Completed Target SSD Simulator
April 29 2009Design
TechnologyLaboratory 3821
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
What to do w Solid-State Disk Simulator
Solid-State Disk Simulator Experimental ResultsSolid State Disk Simulator Experimental Results
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3822
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
FTL Optimization Analysis
Advanced FTL developmentHW dependant function profilingHW-dependant function profiling
Optimize the functions in the performance bottleneck
Specialize FTL to the target HW architectureSpecialize FTL to the target HW architecture
Fair comparison of various FTL algorithmsFair comparison of various FTL algorithmsComparison for a common architecture
With i hit t l i tWith various architectural variants
Consideration of their computing overheadsC i f i l f kl dComparison for various classes of workloads
April 29 2009Design
TechnologyLaboratory 3823
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
HWSW Partitioning
Virtual Profiling
MicroController
Frequently Used functionamp Possible to make HW accelerator
Only SW
Make Function Component
Performance
Improvement Improvement
April 29 2009Design
TechnologyLaboratory 3824
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
RTL verification in SSD
Vera Specman hellipComponent level verificationComponent-level verification
SSD simulatorGolden reference of RTL verificationSSD-level component verification
SSD Si l tSSD Simulator
NANDFLASH
Controller
RTL IP Replacing systemC model by RTL
model
April 29 2009Design
TechnologyLaboratory 3825
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Implementation
Analysis using Solid-State Disk Simulator
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3826
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Experimental Results
Environment SettingCore SATA Cache Buffer NANDCore SATA Cache Buffer NAND
100 MHz 300 MHz 200 MHz 40 MHz
Trace Size
Random Write Read 4 KB
NAND Flash Memory SDRAM
Parameter Value Unit Parameter Value Unit
Ways 4 Bit WidthModule 64 Bit
Sequential Write Read 05 MB
BlocksWay 4096 Ranks 2
PlanesWay 1 BanksRank 4
PagesBlock 64 Burst Length 4
Page Data Size 4096 Byte Refresh Period 64 ms
Page Spare Size 128 Byte Size 16 MB
tADL 4 Cycle tCL 3 Cycley y
tBERS 80000 Cycle tDQSS 1 Cycle
tCCS 3 Cycle tRCD 6 Cycle
tCEA 3 Cycle tRFC 51 Cycle
tIEBSY 20 Cycle tRFCI 3120 Cycle
tIPBSY 20 Cycle tRP 6 Cycle
tPCBSY 120 C l tWR 6 C ltPCBSY 120 Cycle tWR 6 Cycle
tPROG 8000 Cycle
tR 1000 Cycle
tRCBSY 120 Cycle
tWB 4 Cycle
April 29 2009Design
TechnologyLaboratory 3827
NAND Flash cells are initially all erased
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Experimental Results
Channel Effect WAY Effect
120
140
160
180
(MBs)
120
140
160
180
(MBs)
40
60
80
100
Performan
ce
WAY1
WAY2
WAY4
WAY840
60
80
100
Performan
ce
CH1
CH2
CH4
CH8
0
20
1 2 4 8
Channel Number
0
20
1 2 4 8
Way Number
Trace Sequential WriteNAND Flash SLCChannel effect dominates way effectSaturated at way=4Providing quantitative analysis
April 29 2009Design
TechnologyLaboratory 38
Providing quantitative analysis
28
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Experimental Results (cont)SLC amp MLC
100
120
140
160
MBs)
100
120
140
160
MBs)
40
60
80
100
Performan
ce (M
4C4W SLC
4C4W MLC
40
60
80
100
Performan
ce (M
8C4W SLC
8C4W MLC
0
20
40
RW RR SW SR
0
20
40
RW RR SW SR
- Sequential operation -MLC can catch up SLC in multi channel amp way organization
-Thanks to channel striping and way interleaving- Random operation
- Cannot benefited by multi channel amp way organization
April 29 2009Design
TechnologyLaboratory 3829
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Experimental Results (cont)For locality exploitation Parallelizing sequential ops
A B
8 channel 4 way250
- 8 channel 4 way- Sequential Requests has
benefit at B (direct access)- In A we do not perform any locality exploitation100
150
200
rman
ce (M
Bs)
A
B any locality exploitation
0
50
RW RR SW SR
Perfor B
April 29 2009Design
TechnologyLaboratory 3830
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3831
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Multi-Core SSD Controller
random
Sequentialprocess
Single CoreIO request
sequential
random
random
Multiple amp simultaneousIO requests From host
random
random
Multi Core
random
sequential
random
Parallelprocess
IO request
random
April 29 2009Design
TechnologyLaboratory 3832
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Speed Up SSD Simulator
Cycle-aware FTL simulatorSimilar accuracy to TLMSimilar accuracy to TLM3 or 4 orders of magnitude faster than TLM
P f h t i ti f hPerformance characterization of each operation for each target architecture
TLM Simulator
FTLFTL
SSD Architecture
- Merge- Wear Leveling- Interleaving- Meta data
Timing Data Base
Host Host
April 29 2009Design
TechnologyLaboratory 3833
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Integration with PC-System simulator
PC System SimulatorTo understand the benefit of SSD in PCTo understand the benefit of SSD in PCImplementation SystemCP hit t l h t f PC SSDPropose architectural enhancement of PC w SSDbull Location South Bridge (SB) or North Bridge (NB)bull Interface SATA or other protocolsbull Interface SATA or other protocolsbull Concurrency Single port or dual port
April 29 2009Design
TechnologyLaboratory 3834
A) SP SB Architecture B) SP NB Architecture C) DP SB Architecture D) DP NB Architecture
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3835
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Summary
Growth of NAND Flash Memory amp SSD MarketMarketFTL has been studied wo HW h t i ticharacteristics
Limited HW architecture were exploredSSD Simulator is advantageous for
Quantitative performance and analysisQ p yArchitecture explorationFTL comparison and optimizationFTL comparison and optimizationHWSW partitioningGolden reference for RTL design
April 29 2009Design
TechnologyLaboratory 38
Golden reference for RTL design
36
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Contents
Introduction
R l t d W kRelated Works
Solid-State Disk Simulator Modeling
Solid-State Disk Simulator Usage
Solid-State Disk Simulator ExperimentSolid State Disk Simulator Experiment
Ongoing amp Future Works
SSummary
Demo of SSD Simulator
April 29 2009Design
TechnologyLaboratory 3837
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838
Demo of SSD Virtual Platform
SoC Designer CanvasEasy to use like schematic capture systemEasy to use like schematic capture systemFlexibility Easy to explore architecture
S C D i Si l tSoC Designer SimulatorHWSW Co-simulation amp Debugbull HW Profiling Tracing Waveform Monitorbull SW RVDS
April 29 2009Design
TechnologyLaboratory 3838