university of tokyo, associate professor: ‘07- … · 2008/12/8 3 nand flash memory ken takeuchi...
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2008/12/8
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Solid-state drive (SSD) and memory system innovation
Dec.11, 2008Ken Takeuchi
Dept. of Electrical Engineering and Information Systems, University of Tokyo
E-mail : [email protected]://www.lsi.t.u-tokyo.ac.jp
1Advanced Flash Memory DevicesKen Takeuchi
Ken TakeuchiToshiba, NAND Flash Circuit Designer: ‘93-’07University of Tokyo, Associate Professor: ‘07-
Developed 6 world’s highest density NAND (0.7μm 16Mb, 0.4μm 64Mb, 0.25μm 256Mb, 0.16μm 1Gb, 0.13μm 2Gb, 56nm 8Gb)150 Patents Worldwide (88 U.S.Patents)ISSCC Takuo Sugano Outstanding Paper Award: ’07ISSCC Program Committee (Memory): ‘07-
Ken Takeuchi Advanced Flash Memory Devices 2
ISSCC Program Committee (Memory): 07Stanford Univ. MBA: ‘03
ISSCC 200656nm 8G Flash
ISSCC 2002130nm 2G Flash
IEDM 2000160nm 1G Flash
ISSCC 1999250nm 256M Flash
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
3Advanced Flash Memory DevicesKen Takeuchi
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
4Advanced Flash Memory DevicesKen Takeuchi
Definition of SSD
SSD : Solid- State DriveMass storage to replace HDD of PC/Enterprise Server.Small, robust, low-power and high performance.SSD consists of NAND Flash Memory and NAND controller(+RAM)
5Advanced Flash Memory DevicesKen Takeuchi
J. Elliott, WinHEC 2007, SS-S499b_WH07.
NAND Flash Memory and SSD MarketPC expected as an emerging application
6Advanced Flash Memory DevicesKen Takeuchi
I. Cohen, Flash Memory Summit 2007.
Gartner Dataquest
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Memory System Bottleneck
CPU registers (<1ns)
SRAM (<1ns)
Ken Takeuchi Advanced Flash Memory Devices 7
DRAM (10ns)
HDD (10ms)
Big Gap
SLC NAND as Cache of HDD
CPU registers (<1ns)
SRAM (<1ns)
DRAM (10 )
Ken Takeuchi Advanced Flash Memory Devices 8
DRAM (10ns)
HDD (10ms)
SLC NAND (20us)
Future Memory System
CPU registers (<1ns)
S/DRAM (<1ns)
DRAM (10ns)
Ken Takeuchi Advanced Flash Memory Devices 9
DRAM (10ns)
2-4bit/cell NAND (1~10ms)
DRAM (10ns)1bit/cell NAND (20us)
NAND Controller
SSDK. Takeuchi, ISSCC 2008 Tutorial T-7.
Future Direction: Vertical IntegrationHistory of NAND Flash Memory System
MP3 Player
Application Software
File System (OS)
Go vertical
Future Block Abstracted SSD
Ken Takeuchi Advanced Flash Memory Devices 10
Smart Media
MP3 PlayerSD Card
USB MemoryBad Block Management Wear-leveling
NAND Flash Memory
Go verticalintegration to improve system-level performance.
ECC
NAND Controller
Key Challenge of SSD
Need to improve device reliability such as endurance, data retention, and disturb.
Require co-design of NAND and NAND controller
11Advanced Flash Memory DevicesKen Takeuchi
circuits to best optimize both NAND and NAND controllers.
OS/Computer architecture innovation essential.
K. Takeuchi, ISSCC 2008 Tutorial T-7.
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
12Advanced Flash Memory DevicesKen Takeuchi
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NAND Flash Memory
Ken Takeuchi Advanced Flash Memory Devices 13
NAND flash memory chip Memory circuit
Memory cell : Floating Gate-FET
K. Kanda, ISSCC, 2008.
43nm 16Gb NAND
Page & Block of NAND Flash Memory
Page : program/read unit
Bitline
Bitline
Bitline
Block : Erase unit
Ken Takeuchi Advanced Flash Memory Devices 14
Memory cells are sandwiched by select gates.Contactless structure : ideal 4F2 cell size
Bitline
Source-line2 Select-gate32 Word-lines
2 Select-gate32 Word-lines
F.Masuoka, IEDM 1987, pp.552-555.
Top View of NAND Flash Cell ArraySource-line(first metal)Bitline (second metal)
Ken Takeuchi Advanced Flash Memory Devices 15
Simple structure : High scalability, High yield
Active area
STI
SGDSGD SGS SGSWord-linesContact to bitline Contact to source-line
K. Imamiya, ISSCC 1999, pp.112-113.
MLC vs. SLC
SLC : Single-level cell or 1bit/cellMLC : Multi-level cell or >2bit/cell
2bit/cell : Long production record since 20013bit/cell or 4bit/cell : Will be commercialized this year.
Most existing SSD uses SLC. MLC based SSD is commercialized this year.
Ken Takeuchi Advanced Flash Memory Devices 16
commercialized this year.
Vth
“0” “1” “2” “3”Number of memory cells
MLC (Multi-level cell)
Vth
“0” “1”Number of memory cells
SLC (Single-level cell)
NAND Operation PrincipleRead
Bit-line voltage“1”
Selected word-line(Read voltage : 0V)
Vread (4.5V)
Bit-line (0.8V 0V)
Vread (4.5V)
Vth
“0” “1”Number of memory cells
Read voltage
Ken Takeuchi Advanced Flash Memory Devices 17
Time
“1”
“0”Vread (4.5V)0V
After precharging, bit-lines are discharged through the memory cell.
Unselected cells are biased to the pass voltage, Vread.
Small cell read current (~1uA) Slow random access (~50us)
Serial access : 30-50ns Fast read = 20-30MB/sec
NAND Operation Principle (Cont’)
Channel-FN tunneling
High reliability
L t ti
Program : Electron injection
0V0V
18V
0V
Ken Takeuchi Advanced Flash Memory Devices 18
Low current consumption
(~pA/cell)
Page based parallel program
Typical page size : 2-4kB
Erase : Electron ejection0V
20V
20V 20V
S. Aritome, IEDM 1990, pp.111-114.
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NAND Operation Principle (Cont’)
P b ff
Page
Row
decoder
Bit-line
・・・
Page : 2-4KBytes
Page based parallel programming
Ken Takeuchi Advanced Flash Memory Devices 19
Memory cell array
Page buffer
Program speed = Page size / Programming time
= 8KByte / 800us
= 10MByte/sec (56nm MLC)
All memory cells in a page are programmed at the same time.
T.Tanaka, Symp. on VLSI Circuits 1990, pp.105-106.
Page buffer
K. Takeuchi, ISSCC 2006,pp.144-145.
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
20Advanced Flash Memory DevicesKen Takeuchi
NAND Circuit Design
Random AccessHigh Speed ProgrammingHigh Speed Read
Sequential AccessHigh Speed ProgrammingHigh Speed Read
21Advanced Flash Memory DevicesKen Takeuchi
Random Access : High Speed Programming
Bit-by-bit Program Verify Scheme
FN tunneling
Program pulse18V
0V0V
0V
Bit-line
Data load
Verify‐read
Program pulse
No
Program Algorithm
22Advanced Flash Memory DevicesKen Takeuchi
T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.
During the verify-read, the program data in the page buffer is updated so that the program pulse is applied ONLY to insufficiently programmed cells.
Page buffer
・・・
PageAll cellsprogrammed ?
End
Yes
Random Access : High Speed Programming (Cont’)
Incremental Program Voltage Scheme
Program voltage, Vpgm increases by ⊿Vpgm.
Constant electric field across the tunnel oxide.
Verify read
Program pulse
Tpulse Tvfy
1 cycle
# f l N l l
⊿Vpgm
Word-line waveform
Constant tunnel current.
23Advanced Flash Memory DevicesKen Takeuchi
G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.K. D. Suh, ISSCC 1995, pp.128-129.
Achieve both fast programming and precise Vth control.
⊿Vth0 Npulse(Time)
(⊿Vth0/⊿Vpgm) cycles
Verifyvoltage
Fastest cellSlowest cell
Vth Npulse = ⊿Vth0/⊿VpgmProgram characteristics
Vth shift is constant at ⊿Vpgm.# of program pulses: Npulse cycles
Programming time, Tprog = (Tpulse+Tvfy)×Npulse
Random Access : High Speed Programming (Cont’)
Problems of MLC programming
Vth
“0” “1” “2” “3”Number of memory cells
MLC SLCY1 Y2 Y1 Y2
4‐level cell2‐level cell
24Advanced Flash Memory DevicesKen Takeuchi
Two bits in a cell are assigned to two column addresses.3 operations (“1”-, “2”- and “3”-program) required.Long programming.
“1”-program & ”1”verify
“2”-program & ”2”verify
“3”-program & ”3”verify
“1”-program & ”1”verify
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Random Access : High Speed Programming (Cont’)
Solution : Multi-page Cell Architecture
Number of memory cells
Vth
“0” “1”
1st page data : “1” “0”
1st page programX1
X2
2-level cell
X1X2
4-level cell
25Advanced Flash Memory DevicesKen Takeuchi
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.
Two bits in a cell are assigned to two rowaddresses.In average, 1.5 operations.Twice faster than conventional scheme.
2nd page program
2nd page data : “1” “0”
Vth
“0” “1” “2” “3”Number of memory cells
1st page data : “1” “0” “0” “1”
Random Access : High Speed Programming (Cont’)
Program Voltage Optimization
26Advanced Flash Memory DevicesKen Takeuchi
T. Hara, ISSCC 2005, pp. 44-45.
WL0, 31 : Higher capacitive coupling with word-lines.Initial program voltage is set lower.
Optimized program voltage accelerates the programming.
Random Access : High Speed Programming (Cont’)
Problems : FG-FG interference
27Advanced Flash Memory DevicesKen Takeuchi
J.D. Lee, EDL 2002, pp. 264-266.M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90.
FG-FG coupling shifts the Vth of a memory cell as the neighboring cell are programmed.To tighten the Vth distribution, ⊿Vpgm is decreased, causing a slow programming.The Vth modulation becomes significant as the memory cell is scaled down.
Random Access : High Speed Programming (Cont’)
Solution : FG-FG Coupling Compensation[3-step programming] [Programming order]
Step 1
Step2
Step3
28Advanced Flash Memory DevicesKen Takeuchi
N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.
FG-FG coupling is suppressed by 90%.Large ⊿Vpgm enables a fast programming.
p
Step 1. The memory cell is ROUGHLY programmed.Cells are programmed BELOW the target Vth.
Step 2. Neighboring cells are programmed.Step 3. The memory cell is PRECISELY programmed.
Random Access : High Speed ReadProblems of MLC read
Vth
“0” “1” “2” “3”Number of memory cells
Y1 Y2 Y1 Y24-level cell2-level cell
① ② ③
29Advanced Flash Memory DevicesKen Takeuchi
Two bits in a cell are assigned to two column addresses.3 operations (“1”-, “2”- and “3”-read) required.Long random read.
MLC
“1”-read
“2”-read
“3”-read
“1”-read
SLC
① ② ③
Random Access : High Speed Read (Cont’)Solution : Multi-page Cell Architecture
X1
X2
2-level cell
X1X2
4-level cell
Vth
“0” “1” “2” “3”Number of memory cells
2nd d t “1” “0”
1st page data : “1” “0” “0” “1”
30Advanced Flash Memory DevicesKen Takeuchi
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.S. Lee, ISSCC 2004, pp.52-53.
Two bits in a cell are assigned to two rowaddresses.In average, 1.5 operations.Twice faster than conventional scheme.
1st page read : ②, ③ EXOR
2nd page read : ①
2nd page data : “1” “0”
①② ③
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Sequential Access : High Speed Programming
Parallel OperationIncrease page sizeMulti-page operationMulti-chip operation (Interleaving)
T b di d i “NAND C t ll Ci it D i ” tiTo be discussed in “NAND Controller Circuit Design” section
Pipeline OperationWrite/Read CacheCache Page Copy
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Parallel Operation : Increase Page SizePage size trend
By increasing the word-line length, the page size has been extended to increase the write and read throughput.
Bit-line
・・・
Page
5000
6000
7000
8000
9000
e (B
yte)
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But, the large page size also causes problems.Noise issue due to the large RC delay of a word-line
Page buffer
0
1000
2000
3000
4000
0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Page
siz
e
Design rule
Problems : SG-WL noise
Selected
Bit-line
SGD
[Conventional read/verify-read]
1.5V
SG-WL capacitive coupling
Parallel Operation : Increase Page Size (Cont’)
33Advanced Flash Memory DevicesKen Takeuchi
SelectedWL31
SGS
WL0
Bit-line precharge
Bit-line discharge
WL bounce
Read failure
K. Takeuchi, ISSCC 2006,pp.144-145.
Parallel Operation : Increase Page Size (Cont’)Solution : Raise neighboring SG BEFORE bit-line discharge
34Advanced Flash Memory DevicesKen Takeuchi
K. Takeuchi, ISSCC 2006,pp.144-145.
Parallel Operation : Increase Page Size (Cont’)Problems : WL-WL noise
35Advanced Flash Memory DevicesKen Takeuchi
K. Takeuchi, ISSCC 2006,pp.144-145.
Parallel Operation : Increase Page Size (Cont’)Solution
36Advanced Flash Memory DevicesKen Takeuchi
K. Takeuchi, ISSCC 2006,pp.144-145.
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Parallel Operation : Multi-page OperationMulti-page operation
Operate multi-page simultaneously to increase the write/read throughput.
[Multi-page operation] 0.25um 256Mb NAND
37Advanced Flash Memory DevicesKen Takeuchi
K. Imamiya, ISSCC 1999, pp.112-113.
Pipeline Operation : Write/Read CachePipelining of data-in/out & cell read/write
Implement data cache in NANDInput /output data to the data cache during cell read/program
[Write Cache Example : 0.13um 1Gbit NAND]
38Advanced Flash Memory DevicesKen Takeuchi
H. Nakamura, ISSCC 2002, pp.106-107.Data Cache
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
39Advanced Flash Memory DevicesKen Takeuchi
SSD Performance
Random accessOS changes such as directory entry and file system metadataApplication S/W change50% of data is < 4KB.R d i l
[Data transfer size in PC application]
Ken Takeuchi Advanced Flash Memory Devices 40
Random access mainly decides the performance of PC.
Sequential accessBootHibernation
K.Grimsrud, IDF2006, MEMS004.
SSD Performance (Cont’)
Read Write Erase
NAND (SLC) 25us 300us 1ms
NAND (MLC) 50us 800us 1ms
HDD 3ms 3ms N.A.
Random access
Ken Takeuchi Advanced Flash Memory Devices 41
Read : SSD with SLC and MLD has a great advantage over HDD.Write : SSD still has a performance advantage. Write performance can be an issue in the future if the NAND performance degrades by scaling the memory cell or increasing the number of bits per cell.
Erase are hidden by operating the erase during the idle period.
SSD Performance (Cont’)
NAND : Single chip operation NAND : 4 chip interleaving
Read Write Read Write
NAND (SLC) 25MB/sec 20MB/sec 100MB/sec 80MB/sec
NAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/sec
HDD 80MB/sec 80MB/sec ‐ ‐
Sequential access
[Block diagram of SSD w interleaving function]
Ken Takeuchi Advanced Flash Memory Devices 42
SSD (SLC) : Comparable read and write performance with HDD.SSD (MLC) : Comparable read performance. By introducing 8chip interleaving, the write performance can be comparable with HDD.
[Block diagram of SSD w. interleaving function]
C. Park, NVSMW 2006, pp.17-20.
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SSD Performance (Cont’)Slow random write problem
Page : program/read unit
Bitline
Bitline
Block : Erase unit
Ken Takeuchi Advanced Flash Memory Devices 43
In case a part of the block is over-written, a block copy operation is performed.
Bitline
Source-line2 Select-gate32 Word-lines
2 Select-gate32 Word-lines
Garbage Collection & Slow Random WriteSystem performance degradation of a large block
70nm 8G MLC (ISSCC2005)
32WLs
[Frequent block copy]56nm 8G MLC (This work)
32WLs
Old block
New block
① Cell read
(ISSCC2006)
Ken Takeuchi Advanced Flash Memory Devices 44
4KB page (max)512KB block 1MB block
8KB page (max)
NAND controller
Page buffer② Data-out, ECC, Data-in
③ Cell program
Fast block copy required
System performance degradation
Block copy time = (T_Cell read+T_Data_out+TECC+T_Cell program)
×(# of pages per block)= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Pipeline Operation : Cache Page CopySolution : Fast block copy
Old block
New blockCell Read
Page iOld block
New block
Old block
New block
Page i+1
Cell read
Cell program
Old block
New block
Step1 Step2 Step3 Step4
Ken Takeuchi Advanced Flash Memory Devices 4545
K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi
NAND controller
Page bufferData-outECC NAND
controller
Page buffer
NAND controller
Page buffer
NAND controller
Page buffer
Data-outECC
Step 4 : Pipelining of programming Page iand data out / ECC of Page i+1.
Fast block copy
Smaller Block Size: All Bit-line Architecture
56nm NAND(Alternate bit-line architecture)
43nm NAND(All bit-line architecture)
All bit-line architecture# of pages in a block is half.Block copy time is also half.
Ken Takeuchi Advanced Flash Memory Devices 46
K. Takeuchi, ISSCC 2006,pp.144-145.
R. Cernea, ISSCC 2008,pp.420-421.K. Kanda, ISSCC 2008, pp.430-431.
Solution for Slow Random WriteFast pipeline block copy operationSmaller block size (All bit-line architecture)Page based data allocation
Not to overwrite an old page but write data to an empty page.Change the logical-physical address table
Ken Takeuchi Advanced Flash Memory Devices 47
Change the logical-physical address table.
D. Barnetson, Electonic Journal 192th Technical Symposium, 2008, pp.91-102.
Old page New page
SSD Power ConsumptionPower consumption
NAND : Single chip operation NAND : 4 chip interleaving
Read Write Read Write
NAND (SLC) 20mA 20mA 80mA 80mA
NAND (MLC) 20mA 20mA 80mA 80mA
HDD >300mA >300mA ‐ ‐
Ken Takeuchi Advanced Flash Memory Devices 48
Actual Power Consumption
In SSD, additional current (~100mA) are consumed in the NAND controller, RAM and IO.
C. Park, NVSMW 2006, pp.17-20.
In all modes, the power consumption of SSD is smaller than HDD.
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SSD ReliabilitySSD is robust.
No mechanical parts.Need to be careful in PC/server application
Portable consumer electronics application(Digital still cameras, MP3 players, Camcorders)
Effective data retention time << 10years
Ken Takeuchi Advanced Flash Memory Devices 49
Effective data retention time << 10yearsData quickly transferred to PC or DVD through USB drive and memory cards.Most probably data backup in PC
PC/Enterprise server applicationHigher reliability required w.o. backupNeed longer data retention time : 5-10 years
SSD Reliability (Cont’)Failure mechanism of NAND
Program disturbDuring programming, electrons are injected to unselected memory cells.Read disturbDuring read electrons are injected to unselected
Ken Takeuchi Advanced Flash Memory Devices 50
During read, electrons are injected to unselectedmemory cells. Write/Erase endurance & Data retentionAs the Write/Erase cycles increase, damage of the tunnel oxide causes a leakage of stored charge.
SSD Reliability (Cont’)“Classic” program disturb
Program inhibitBitline (Vcc)
Vpgm(18V)
Vcc
ProgramBitline (0V)
Vpass(10V)
Ken Takeuchi Advanced Flash Memory Devices 51
Both selected and unselected cells suffer from the disturb.
Vpass disturb cell10V
D S0VVpass(10V)0VVcc
(10V)
Vpgm disturb cell18V
D S~8V
K. D. Suh, ISSCC 1995, pp.128-129.
SSD Reliability (Cont’)“Modern” program disturb
Ken Takeuchi Advanced Flash Memory Devices 52
Hot carriers generated at the select gate edge inject into the memory cell causing a Vth shift.The Vth shift can be reduced by increasing SG-WL space.
J. D. Lee, NVSMW 2006, pp. 31-33.K.T.Park, SSDM 2006, pp.298-299.
SSD Reliability (Cont’)“Modern” program disturb (Cont’)
Ken Takeuchi Advanced Flash Memory Devices 53
The Vth shift can be reduced by adding dummy WL.K.T.Park, SSDM 2006, pp.298-299.
Select Tr. Dummy Tr. WL0
SSD Reliability (Cont’)
Read disturb
4.5V
D S0V
Selected word-line(0V)
Vread (4.5V)
Bitline (0.8V 0V)
Ken Takeuchi Advanced Flash Memory Devices 54
0V
Vread (4.5V)
0V
Vread (4.5V)
Weak program bias conditionUnselected word-lines suffer from the read disturb.
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SSD Reliability (Cont’)
Program disturb and read disturb is a “bit error” not a “burst error”.
Two bits in MLC are assigned to different pages.
Program disturb and read disturb summary
X1
X2
X1X2
Page assignment of MLC
Ken Takeuchi Advanced Flash Memory Devices 55
Even if one MLC cell fails, one bit in two pages fails.
ECC(Error correcting code) effectively corrects the bit error.
Existing ECC corrects 4-12bit errors per 512Byte sector.
2-level cell 4-level cellK. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.
SSD Reliability (Cont’)Write/Erase Endurance & Data Retention
Endurance : how many times data are writtenData retention : how long the data remains validClear correlation between endurance and data retention
Damages to the tunnel oxide during write and
Ken Takeuchi Advanced Flash Memory Devices 56
K. Prall, NVSMW 2007, pp. 5-10.
erase cause the data retention problems.Traps are generated during write and erase.The unlucky cell with traps results in a leakage path, causing the charge transfer.The leakage current is called SILC (Stress Induced Leakage Current).
To guarantee data retention, Write/Erase cycles are limited to 100K (SLC) or 10K (MLC).
SSD Reliability (Cont’)100K (SLC) or 10K(MLC) W/E cycles acceptable?
W/E cycles estimation for PC32GB SSDUsage scenario : 2~5GB/day (#)
Service for 5years100% efficient wear leveling
Ken Takeuchi Advanced Flash Memory Devices 57
g(365 days/year) x 5years / (32GB / 2~5GB/day) = 114~285 W/E cycles114~285 cycles are far below the NAND limitation of 100K for SLC or 10K for MLC.Actual W/E cycles are higher for the file management such as garbage collection.
(#) W.Akin, IDF 2007_4, MEMS003.Y.Kim, Flash Memory Summit 2007.
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
58Advanced Flash Memory DevicesKen Takeuchi
SSD SW Architecture
Flash Translation Layer (FTL)
Host I/FNAND Controller
File system
SSDATA I/F
OS
Low level driver
Ken Takeuchi Advanced Flash Memory Devices 59
Flash Translation Layer (FTL)
Bad block management Wear-leveling
InterleavingAddress translation from logical address to physical
address of NAND
NAND I/F
NAND Flash Memory
ECC
HW ArchitectureBlock diagram (Single channel)
60Advanced Flash Memory DevicesKen Takeuchi
C. Park, NVSMW 2006, pp.17-20.
HDD-like architecture : DRAM buffer to hide NAND random accessHigh power consumptionHigh cost
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HW Architecture (Cont’)Block diagram (Multi-channel)
DRAM eliminated :Random access of NAND is faster than HDD.Low power consumption
61Advanced Flash Memory DevicesKen Takeuchi
C. Park, NVSMW 2006, pp.17-20.
p pLow costMulti-channel
Parallel operationHigh bandwidth
High Speed TechnologyInterleaving : Sequential Parallel Write
62Advanced Flash Memory DevicesKen Takeuchi
C. Park, NVSMW 2006, pp.17-20.
2-channel 4-way interleavingMax write throughput : 80MB/sec for MLC.HW driven automatic operation.
High Reliability TechnologyWear-leveling
Problem Write/Erase cycle of NAND is limited to 100K for SLC and 10K for MLC.Solution
Write data to be evenly distributed over the entire storage.Count # of Write/Erase cycles of each NAND block.
63Advanced Flash Memory DevicesKen Takeuchi
Based on the Write/Erase count, NAND controller re-map the logical address to the different physical address.Wear-leveling is done by the NAND controller (FTL), not by the host system.
Bitline
Bitline
Bitline
Block : Erase unit
High Reliability Technology (Cont’)
Example of wear-levelingIf the block is occupied with old data, data is programmed to a new block.If there is no free block, the invalid block are erased.
Block 1Block 2Bl k 3
Block 1Block 2Bl k 3
64Advanced Flash Memory DevicesKen Takeuchi
Block 3Block 4Block 5Block 6Block 7Block 8Block 9
Rewrite old file
New File Write new file to an empty block
Old file
Empty block
Block 4 InvalidBlock 3Block 4Block 5Block 6Block 7Block 8Block 9
High Reliability Technology (Cont’)
Static dataData that does not change such as system data (OS, application SW).Dynamic dataData that are rewritten often such as user data.
65Advanced Flash Memory DevicesKen Takeuchi
Dynamic wear-levelingWear-level only over empty and dynamic data.Static wear-levelingWear-level over all data including static data.
High Reliability Technology (Cont’)Dynamic wear-leveling
Write/Erase countRed : Static data such as system data.Blue : Dynamic data such as user data
66Advanced Flash Memory DevicesKen Takeuchi
Physical block address
N.Balan, MEMCON2007.SiliconSystems, SSWP02.
Block with static data is NOT used for wear-leveling.Write and erase concentrate on the dynamic data block.
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High Reliability Technology (Cont’)Static wear-leveling
Write/Erase count Red : Static data such as system data.Blue : Dynamic data such as user data
67Advanced Flash Memory DevicesKen Takeuchi
Physical block addressWear-level more effectively than dynamic wear-leveling.Search for the least used physical block and write the data to the location. If that location
Is empty, the write occurs normally.Contains static data, the static data moves to a heavily used block and then the new data is written. N.Balan, MEMCON2007.
SiliconSystems, SSWP02.
High Reliability Technology (Cont’)Bad Block Management
Program/Erase characteristics vs. endurance
68Advanced Flash Memory DevicesKen Takeuchi
As the Write/Erase cycles increases, erase failure occurs, resulting in a bad block.The NAND controller detects and isolates the bad block.
Y.R. Kim, Flash Memory Summit 2007.
High Reliability Technology (Cont’)High Reliability Technology (Cont’)ECC (Error Correcting Code)
To overcome read disturb, program disturb and data retention failure, ECC have to be applied.Since failure pattern is
69Advanced Flash Memory DevicesKen Takeuchi
Since failure pattern is random, BCH is sufficient.
Existing NAND controller can correct 4-12bit error per 512Byte sector.
NAND with embedded ECC is also published. R. Micheloni, ISSCC2006, pp.142-143.
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
70Advanced Flash Memory DevicesKen Takeuchi
Why OS?Motivation
Existing OS is optimized for magnetic drives.Current SSD based PC uses the conventional OS and just replace HDD with SSD.To achieve the best performance and reliability
71Advanced Flash Memory DevicesKen Takeuchi
To achieve the best performance and reliability of SSD, OS especially file system should be optimized.Windows 7 will treat SSD differently from HDD.
New Memory System: NAND/HDD ComboNAND as a cache
Intel RobsonMicrosoft Ready Boost
Multi-drive of NAND/HDDSanDisk Vaulter DiskNAND : OS dataHDD : User data
Ken Takeuchi Advanced Flash Memory Devices 72
H. Pon, NVSMW 2007. http://www.sandisk.com/Assets/File/pdf/oem/Vaulter_brochure.pdf
Temporary solution until NAND cost becomes comparable with HDD cost.
2008/12/8
13
MLC/SLC Hybrid SSDFuture Direction : Hybrid SSD with SLC and MLC
Concept : Right device for the right use.Enjoy the Benefit of both SLC and MLC.SLC : Fast and highly reliable but low capacity.
Use SLC as a cache or system data storage.MLC : Large capacity but slow. Use MLC as user data storage.OS support essential: SSD does NOT know the contents of the file.
Toshiba LBA-NAND
Ken Takeuchi Advanced Flash Memory Devices 73
Samsung Combo SSD J. Elliott, WinHEC2007.Toshiba LBA NAND
http://www1.toshiba.com/taec/index.jsp
Spansion MirroBit Eclipsehttp://www.spansion.com/products/MirrorBit_Eclipse.html
2006 20102007 2008 2009
PATA4/8/16/32GB
SATA-I8/16/32/48/64GB
SATA-II8/16/32/48/64GB
MLC(Multi Level Cell)
Combo(SLC+MLC)
SLC(Single Level Cell)
SATA-II16/32/64/96/128GB
SATA-III56/112/224/336/448GB
SATA-II14/28/56/84/112GB
SATA-III32/64/128/192/256GB
SATA-II16/32/48/64/96/128GB
SATA-II32/48/64/128/256GB
SATA-II28/56/112/168/224GB
57/32 64/45 100/80 160/160 800/800 1300/1300R/W Speed:
SATA-III 48/64/128/256/512GB
Performance Optimization
Sector size optimizationMinimum write/read unit of NAND is a page.Typical page size is 4-8KByte.A page is written only ONCE to avoid the program disturbance.With current OS having 512Byte sector,
Page
74Advanced Flash Memory DevicesKen Takeuchi
one sector write wastes >80% of data in a page.
LBD(Long Block Data) sector standard (Windows Vista) : 4KByte sector size fits better with SSD.
1 sector write
・・・
Remaining portion becomes garbage.
Frequent Garbage CollectionSystem performance degradation of a large block
70nm 8G MLC (ISSCC2005)
32WLs
[Frequent block copy]56nm 8G MLC (This work)
32WLs
Old block
New block
① Cell read
(ISSCC2006)
Ken Takeuchi Advanced Flash Memory Devices 75
4KB page (max)512KB block 1MB block
8KB page (max)
NAND controller
Page buffer② Data-out, ECC, Data-in
③ Cell program
Fast block copy required
System performance degradation
Block copy time = (T_Cell read+T_Data_out+TECC+T_Cell program)
×(# of pages per block)= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Page Size Trend
6000
7000
8000
9000
e) 800
1000
1200
yte)
As the page size increases as NAND is shrinking, larger sector size such as 64KByte or 128KByte is required.
Ken Takeuchi Advanced Flash Memory Devices 76
0
1000
2000
3000
4000
5000
6000
0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Page
siz
e (B
yte
Design rule
0
200
400
600
800
0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Blo
ck s
ize
(KB
y
Design rule
Reliability OptimizationEnhanced Write Filter (Windows Embedded)
Decrease write/erase cycles of NAND, extending the NAND lifetime.Control the file allocation to store frequently rewritten file in DRAM and not to access NAND.Enhanced Write Filter (EWF) is located between file system and low level driver interfacing with SSD.
77Advanced Flash Memory DevicesKen Takeuchi
OS/Application SW support essential: Again, SSD does NOT know the contents of the file.
http://msdn2.microsoft.com/en-us/library/ms912909.aspx
SSD
Enhance Write Filter
File System
Application
Low-level Driver
Reliability Optimization (Cont’)SMART (Self-Monitoring, Analysis and Reporting Technology)
Monitor the storage and report/predict the failure.SMART for HDD is NOT smart because it is very difficult to predict the mechanical failure.(Google report http://209 85 163 132/papers/disk failures pdf)
78Advanced Flash Memory DevicesKen Takeuchi
(Google report, http://209.85.163.132/papers/disk_failures.pdf)
SMART for SSD can be really smart.Product lifetime can be predicted because the failure rate is highly correlated with the write/erase cycles.
Predict the SSD lifetime by monitoring the write/erase cycles and replace SSD before the fatal failure occurs.
http://www.tdk.co.jp/tefe02/ew_007.pdf
2008/12/8
14
Outline
SSD, Memory System InnovationNAND OverviewNAND Circuit DesignSSD OverviewNAND Controller DesignOperating System for SSDGreen IT with SSDSummary
79Advanced Flash Memory DevicesKen Takeuchi
Green IT : Power Crisis of Data CenterData through internet is increasing drastically.In the U.S, power consumption at the data center doubled during last 5 years. (5 nuclear power plants!)In 2025, the data increases by 200 times and the power consumption increases by 12 times.
Ken Takeuchi Advanced Flash Memory Devices 80
Data Center
Power increase of HDD
Replace HDD with SSD
Ken Takeuchi Advanced Flash Memory Devices 81
SSD(NAND Flash)
HDD
Problems of NAND Flash MemoryReliabilityLow write/erase cycles: Currently <10K cycles (MLC) and decreasing as scaling down memory cells.
>100K cycles required
Power Consumption
Ken Takeuchi Advanced Flash Memory Devices 82
pBecause of the scaling, the parasitic capacitance increases and the power consumption doubles.
Low power memory device required
CapacityCurrently Gbyte TByte required
Operation Current Trend of NAND
100
A]
In the scaled VLSIs, most power is consumed to charge and discharge signal-lines.Inter signal-line capacitance, Cwire-wire drastically increases to keep the low signal-line resistance.
Ken Takeuchi Advanced Flash Memory Devices 83
0
20
40
60
80
10 20 30 40 50 60 70
Ope
ratio
n cu
rren
t [m
A
10 20 30 40 50 60 70Feature size [nm]
80
60
40
20
0
Cwire-wire Cwire-wire
Cwire-wire Cwire-wire
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Fe(Ferroelectric)-NAND Flash MemoryNAND Flash Memory w. Ferroelectric Transistor
Scalable below 20nmLow voltage/power operation: 20V 5VWrite/Erase cycles: 10K cycles 100M cyclesMost suitable for data server application
Ken Takeuchi Advanced Flash Memory Devices 84
MFIS Structure(Metal-Ferroelectric-
Insulator-Semiconductor)S. Sakai, NVSMW 2008, pp.103-104.
p-Sin+n+
MFI
PtSrBi2Ta2O9
Hf-Al-O
2008/12/8
15
Operation Principle of Fe-NAND Flash
WL0
SGD
BL BL
FeFET
5V
n+
MFI
n+
0V
n+n+
MFI
Low voltage operation
Ken Takeuchi Advanced Flash Memory Devices 85
WL31
SGS
Source Line
0V
p-well Si
n+n
Program
5V
p-well Si
n+n+
Erase
S. Sakai, NVSMW 2008, pp.103-104.
Sr Bi
SrBi2Ta2O9 (SBT)
a = 0.5506 nmb = 0.5534 nmc = 2.498 nm
Scalable below 20nm
SrBi2Ta2O9~ 400nm
Hf-Al-O
TEM Photograph
Ferro electricity is maintained in 20nm size.
OTa
a
b
c
Ken Takeuchi Advanced Flash Memory Devices 86
Si
IL
Hf-Al-O~ 10nm
IL: Interfacial layer major component – SiO2
S. Sakai, NVSMW 2008, pp.103-104.
10 Year Data Retention
10-10
10-8
10-6
10-4
urre
nt, I
d (A
)
1st 2nd 3rd4th
37.0 days
33 5 d
On states
n+n+
MFI
PtSrBi2Ta2O9
Hf-Al-O
Ken Takeuchi Advanced Flash Memory Devices 87
10-14
10-12
10 10
Dra
in C
u
100 102 104 106 108
Time, t (s)
4th 33.5 days
Off states10 years
p-Sin+n
Buffer layer improves Si‐interface characteristics.
Excellent W/E Cycles up to 100M1.1
1.0
0.9
0.8
0.7
0.6
0 5
Vth
(V
) Erased Programmed
Fe-NAND
Ken Takeuchi Advanced Flash Memory Devices 88
0.5103 104 105 106 107 108
Number of Cycles
Y.R. Kim, Flash Memory Summit 2007.
NAND
S. Sakai, NVSMW 2008, pp.103-104.
Co-design of NAND and Controller Circuits
20
40
60
80
100
系列1系列2系列3
Ope
ratio
n cu
rren
t [m
A]
80
60
40
20
Selective BL precharge & Advanced SL program
Selective BL prechargeConventional
23% reduction
48%reduction
Power Detect(PD)
NANDChip4
CE4, R/B4
NANDController
NANDChip1
NANDChip2
NANDChip3
CE3, R/B3CE2, R/B2CE1, R/B1
NAND Flash
By co-designing both NAND and NAND controller circuits, the power consumption of SSD is reduced by 60%.
Ken Takeuchi Advanced Flash Memory Devices 89
010 20 30 40 50 60 70
O
10 20 30 40 50 60 70Feature size [nm]
0( )
ALE, CLE, RE, WE, WP, IO
Time
Time
Time
Time
Current waveform of NAND Chip1
Current waveform of NAND Chip2
Current waveform of NAND Chip3
Current waveform of NAND Chip4
NAND Controller K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Memory
Co-design of NAND and Controller Circuits
• Low Power Circuit Technology– Selective bit-line precharge scheme– Advanced source-line program
• Low Noise Circuit Technology– Intelligent interleaving
90Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
2008/12/8
16
SSD Write Performance• Interleaving: write N NAND chips in parallel
Performance_SSD = N × Performance_NAND
・・
Channel 4
NANDChip16
Channel 1
NANDChip1
NANDChip2
NANDChip15
NANDController
• Limitation of NN × I_NAND < Icc_constraint
• Key NAND design issue: Decrease I_NAND to maximize N
91
NANDChip16
Channel 4
NANDChip1
NANDChip2
NANDChip15
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
NAND Bit-line Capacitance Trend• Inter bit-line capacitance, CBL-BL drastically
increases to keep the low bit-line resistance.
10
CBL-BL CBL-BL CBL-BL CBL-BL
0
2
4
6
8
10
10 20 30 40 50 60 70
Bit-
line
capa
cita
nce [
a.u.
]
10 20 30 40 50 60 70Feature size [nm]
92
K. Kanda, ISSCC, 2008.43nm 16Gb NAND
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Current & Performance TrendNAND operation current SSD performance
40
60
80
100
tion
curr
ent [
mA
]
80
60
40 40
60
80
100
rman
ce [M
Byt
e/se
c]
80
60
40
100
0
20
10 20 30 40 50 60 70
Ope
rat
10 20 30 40 50 60 70Feature size [nm]
20
0 0
20
10 20 30 40 50 60 70
SSD
Per
for
10 20 30 40 50 60 70Feature size [nm]
0
20
C_bit‐line↑ I_NAND ↑ N↓ Performance_SSD↓
• Low power circuit of NAND required.
93Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Multi-level Cell Program
Data load
Program pulse
Bit-by-bit Program Algorithm
Vth
“A” “B” “C”Number of memory cells
Erased state
1st page program 2nd page programVA VB VC
All cellsprogrammed ?
End
Verify‐read
Yes
No “A”-program & ”A”verify
“B”-program & ”B”verify
“C”-program & ”C”verify
94Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
• All bit-lines are precharged irrespective of the programdata.
• Page based program 8KByte(Page size) bit-lines are precharged.Total bit-line capacitance > 200nF!
Conventional Verify Read
Bit-line (0.8V 0V) “0” “1”Number of memory cells
95
Bit-line voltage
Time
“1”
“0”
0V
Selected word-line(Read voltage : 0V)
Vread (4.5V)
Vread (4.5V)
Bit line (0.8V 0V)
Vread (4.5V)
Vth
“0” “1”
Read voltage
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Bit-line Bit-line
• During verify, precharge bit-line based on the programdata in the page buffer.
• Skip unnecessary bit-line precharge and save currentduring verify.
• Area overhead < 1%Page Buffer
Selective Bit-line Precharge Scheme
Latch1
IO CSL /IO
N3
N2
PRE2
Latch2
N1
N1
N2
N3 PRE1
* * *
* *Additional Transistor
96
PRE1 PRE2“A”-verify “High” “High”“B”-verify “High” “Low”“C”-verify “Low” “High”
Ken Takeuchi Advanced Flash Memory Devices
2008/12/8
17
1st Page Program (“A”-verify)
Vth
“A” “B” “C”Number of memory cells
Erased state
VA VB VC
TimeBit-line
prechargeBit-line
discharge
Bit-line
Word-line VA
“A”-program incomplete“A”-program completeProgram inhibit
Bit-lineprecharge
Bit-line discharge
Bit-line
Word-line VA
“A”-program complete / incompleteProgram inhibit
Time
[Conventional] [Proposed]
97
1st page program 2nd page programA B C
Ken Takeuchi Advanced Flash Memory Devices
2nd Page Program (“B”-verify)
Vth
“A” “B” “C”Number of memory cells
Erased state
1st 2ndVA VB VC
98
TimeBit-line
prechargeBit-line discharge
Bit-line
Word-line VB
“B”-program incomplete
TimeBit-line
prechargeBit-line discharge
Bit-line
Word-line VB
“B”-program complete / incomplete“C”-program complete / incompleteProgram inhibit
“B”-program complete“C”-program complete / incompleteProgram inhibit
[Conventional] [Proposed]
1st page program 2nd page program
Ken Takeuchi Advanced Flash Memory Devices
2nd Page Program (“C”-verify)
Vth
“A” “B” “C”Number of memory cells
Erased state
1st 2ndVA VB VC
99
[Conventional] [Proposed]
TimeBit-line
prechargeBit-line discharge
Bit-lineWord-line VC
“C”-program incomplete
TimeBit-line
prechargeBit-line discharge
Bit-lineWord-line VC
“B”-program complete / incomplete“C”-program complete / incompleteProgram inhibit
“B”-program complete / incomplete“C”-program completeProgram inhibit
1st page program 2nd page program
Ken Takeuchi Advanced Flash Memory Devices
Result – Selective BL precharge
80
100
系列1[mA
]
80 Conventional
23% reduction 100
yte/
sec]
100
• 23% current reduction.• 50% performance improvement.
100
0
20
40
60
10 20 30 40 50 60 70
系列2
Ope
ratio
n cu
rren
t [
10 20 30 40 50 60 70Feature size [nm]
60
40
20
0
Selective BL precharge
0
20
40
60
80
10 20 30 40 50 60 70
系列1
系列2
SSD
Per
form
ance
[MB
y
10 20 30 40 50 60 70Feature size [nm]
80
60
40
0Selective BL precharge
Conventional20
50%improved
Ken Takeuchi Advanced Flash Memory Devices
Source-line Program (VLSI’99)
Bit-line (1V)
V
SGD(0V 0.7V)
Bit-line (2.5V)
SGD(4.5V)
[Conventional] [Source-line program]
• Save current during program pulse.• Bias 2.5V from a low capacitance source-line.• Low voltage swing for a high capacitance bit-line
101
K. Takeuchi, Symposium on VLSI Circuits, pp.37-38, 1999.
Inhibitvoltage
Source-line (2.5V)
Vpass(10V)
Vpgm(18V)
SGS(4.5V 0V)
Vpass(10V)
Vpass(10V)
Vpgm(18V)
SGS(0V)
Source-line (1V)
Vpass(10V)
Inhibitvoltage
Demonstrated in0.25um NAND
Ken Takeuchi Advanced Flash Memory Devices
Capacitance ComparisonBit-line
Bit-line
Bit-line
Source-line2 SG, 64 CG 2 SG, 64 CG
C = C + C
102
Cbit-line = Cwire(bitline) + CjunctionCsource-line = Cwire(source-line) + Cjunction
Cwire(bitline) >> Cjunction, Cwire(source-line)
Cbit-line >> Csource-line
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
2008/12/8
18
Advanced Source-line Program• Total source-line capacitance in a chip exceeds 20nF for
sub-50nm NAND.• Hierarchical source-line structure• Only metal layout change; No area overhead
Sub-array Sub-array
Bit-line
103
Local source-line
Row decoder Row decoder Row decoder Row decoder Row decoder
Local source-lineSource-line
decoderSource-line
decoder
Global source-line
Switch
Bit-line
Bit-line
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Read Operation
• All Source-line switch: ON• Minimize the source-line resistance.• Suppress the source-line noise.
Sub-array Sub-array
Bit-line
104
Local source-line
Row decoder Row decoder Row decoder Row decoder Row decoder
Local source-line
Source-linedecoder
Source-linedecoder
Global source-line
ON
Bit-line
Bit-line
ON
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Program Operation
• Only one of 16 sub-arrays activated• Source-line capacitance: 90% reduced
Sub-array Sub-array
Bit-line
Bit line
105
Local source-line
Row decoder Row decoder Row decoder Row decoder Row decoder
Local source-line
Source-linedecoder
Source-linedecoder
Global source-line
ON
Bit-line
Bit-line
OFF
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
80
100
系列1[mA
]
80 Conventional
23% reduction
Result – Advanced SL program
• 60% current reduction.• 250% performance improvement.
100
yte/
sec]
100
0
20
40
60
80
10 20 30 40 50 60 70
系列2系列3
Ope
ratio
n cu
rren
t [
10 20 30 40 50 60 70Feature size [nm]
80
60
40
20
0
Selective BL precharge & Advanced SL program
Selective BL prechargeConventional
48%reduction
106
0
20
40
60
80
10 20 30 40 50 60 70
系列1系列2系列3
SSD
Per
form
ance
[MB
y
10 20 30 40 50 60 70Feature size [nm]
80
60
40
0Selective BL precharge & Advanced SL program
Selective BL prechargeConventional
20
250%improved
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Intelligent Interleaving• Disperse the current peak and avoid the
power supply noise.Bit-line precharge & charge pump ramp-up
cause >100mA current peak.
107
Time
Time
Time
●
●
●
Time
NAND Chip1
NAND Chip2
NAND Chip3
NAND Chip4
[Current waveform during program and verify]
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Control Circuit• Introduce Power Detect (PD) signal.• When a NAND starts bit-line precharge &
charge pump ramp-up, PD becomes low.• NAND controller issues a write command
when PD is high and NAND is ready.CE1 R/B1
108
Power Detect(PD)
NANDChip4
CE4, R/B4
NANDController
NANDChip1
NANDChip2
NANDChip3
CE3, R/B3CE2, R/B2CE1, R/B1
ALE, CLE, RE, WE, WP, IO
PDR/B1
Program_Enable1(Chip1)
PDR/B3
Program_Enable3(Chip3)
PDR/B2
Program_Enable2(Chip2)
PDR/B4
Program_Enable4(Chip4)
●
●
●
Ken Takeuchi Advanced Flash Memory Devices
2008/12/8
19
Current Waveform
Time
Time
Time
Current waveform of NAND Chip1
Current waveform of NAND Chip2
Current waveform of NAND Chip3
Current waveform of NAND Chip4
109
●
●
●
Time
Power Detect (PD)-signalR/B1 (chip1)
R/B2 (chip2)
R/B3 (chip3)
R/B4 (chip4)●
●
●
Ken Takeuchi Advanced Flash Memory Devices
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Summary: Co-design of NAND and Controller Circuits
• Co-design of NAND and NAND controller.– To improve SSD speed, decrease the NAND current
and maximize # of NAND operated in parallel.
• Two low power circuit technologies proposed.– Selective bit-line precharge schemeg– Advanced source-line program– 60% current reduction.– 250% SSD performance improvement.
• Intelligent interleaving realizes highly reliable and high-speed SSD.
Ken Takeuchi Advanced Flash Memory Devices 110
3D-integrated SSDFirst demonstration of 3D-integrated SSD.With smart Mix & Match, the power decreases by 70%.
3D-SiPMPU Core
CacheROM
Logic
AnalogFlash
DRAM
Ken Takeuchi Advanced Flash Memory Devices 111
To be presented at ISSCC in Feb. 2009@San Francisco. 13.2. “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator
for 3D-Integrated NAND Flash SSD”
MPU Core
Logic
AnalogCache
Flash ROM
DRAM
SoC3D SiPCache
Summary
New Memory SystemSLC/MLC Hybrid SSD solves the system bottleneck.
Emerging Market: Power Crisis at data centerSSD is expected to save power at data center.
Device, circuit and OS innovation required.Co-design of NAND and NAND controller circuitsOS optimization such as sector size optimizationFe(Ferroelectric)-NAND flash memory device3D-integrated SSD circuits
112Advanced Flash Memory DevicesKen Takeuchi
Thank you!
E-mail : [email protected]://www.lsi.t.u-tokyo.ac.jp
Ken Takeuchi Advanced Flash Memory Devices 113