%a k;h 6ha|Õ! j=u ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... ·...

5
!·" 2015 !" 28 #" $ ElectronicSci&Tech/Feb15 2015 !!! "#$%&#'()# *+, !"#$20140626 )*+," 9: 1987 —),123453467FPGA Þ< O ó ¾xz£Email fanxiaoxing1987 @126com doi 1016180/jcnkiissn1007-7820201502043 %a K;H 6 Ha |Õ! j=U 7> _ ¸ ÛÜÝÞÜßÖ à !"#$%&'( #$£*&uoDLVÜ.! !" 710071 : ; ®¯d'N FPGAó¾xz£Cw¦õänaY÷CÖ IP JÞ@ Xilinx 8]C ISEXY NG FPGAÀÊGCLJ RocketIO<IJ FIFOÞÖRSró¾xXYN EDK»¼vo@ FPGAó¾ xz£GrCÖ#Bu IP J8ЦÑÏK´c«d6;CÏTQ<=> FPGA EDK ó¾xIP JNPI à¢RocketIO MPMC PLB ࢠ?@ABC TP3312  DEFGH A  DIJC 1007-7820 2015 02-164-05 DesignofHighspeedDataTransceiverEmbeddedUserIPCoreBasedonEDK FANXiaoxing XIPengfei MENGQi MinistryofEducationKeyLaboratoryofElectronicInformationCountermeasureandSimulationTechnologyMinistry ofEducation XidianUniversity Xian710071 China Abstract ThispaperintroducestheuserIPcoredesignofmultichannelhighspeeddatatransceivermodule FPGAbasedembeddedsystems.OftheXilinxsISEdevelopmenttools FPGAdeviceshardcoreandsoftcoreFIFO RocketIOisusedtodesigntheuserlogic.ThecustomFPGAIPcoreusedinembeddedsystemsispackedusingthe embeddeddevelopmenttoolsofEDK.Theeffectivenessofthemethodisverifiedbyactualtest. Keywords FPGA EDK embedded IPcore NPIbus RocketIO MPMC PLBbus a\Øht¶9~_wxFPGAXó #8+yw+\DE>aÈÉJ6 FPGAö| "Òa9ó#8Pft PowerPC ARMnó#sFPGA £¢yP°Ntó#8Pft9 FPGA£¢1S³ ? FPGAÈ"¡YW FPGAó#8È"Ît ÂÌÍ9{ü¹íX)¹íyÂò FPGA£¢ý Ît'AåÕ9 IP ñ_С|¶_ alå¡YØh9Þ¡¤L'íãDt +9qw¥wÕÈ"û`aX6ÂYZF tÈ"9Ð3ag U£ È " FPGA i,Xilinx ª y ° t EDK EmbeddedDevelopmentKit ), ÒpaW FPGAKoó #8P f tñ Õ i,g4éêt'A* PowerPC i,¿9 IP ¢a EDK~i,I' í¹}i,1ãDqwpX EDKy9 IP åûÐÑi,â$Xi,y9¢aw Xilinx ª y9öqwg4 ISE IntegratedSoftwareEnvi ronment y45J6 EDKyÅ59 IP ÐÈÉ xÎtYóa ISE y9 IP ¡X EDK67í ¢a9 IP i,)i,{N FPGA*¢ï9F :mNVXÝKæ9Èû! 7> /S³aÁ IP %µÞ¡bâ H-Ü 1 #BuÖ IP !BÜ bâ H-IP W Xilinx ªy Virtex-5FX «9 PowerPCó#8+i,aÁ IP m ^ PLB %E-ìX PowerPC +ym^ GTX

Upload: others

Post on 27-Feb-2021

1 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: %a K;H 6Ha|Õ! j=U ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... · 2019. 1. 17. · )3·)4 2015!"28#"2$ ElectronicSci&Tech/Feb15,2015!!!"#$%&#’()#*+,!"#$:20140626)*+,:"9:(1987—),fi,12345。3467:

)3

·)4

2015!"

28#"

2$

ElectronicSci&Tech/Feb15,2015

!!!

"#$%&#'()#

*+,

!"#$

:20140626)*+,

:"9:

(1987—),�

,12345

。3467

FPGA� Þ < O � ó ¾ x z £

。Email:fanxiaoxing1987@126com

doi:1016180/jcnkiissn1007-7820201502043

%a K;H 6Ha|Õ!��j=U� 7> _¸�

ÛÜÝ

,ÞÜß

,Ö

 à

(!"#$%&'( #$Nò��£�*��&uo©oDLVÜ�

,.! !"

 710071)

:

 ;

 ®¯d'N

FPGAó¾xz£Cw¦õänJÈaY�÷C�Ö

IPJ�Þ

。@

Xilinx8]C

ISEXY�

NG

,�

FPGAÀÊGCLJ

RocketIO<IJ

FIFO�Þ�ÖRS

;r�ó¾xXY�N

EDK»¼vo@

FPGAó¾

xz£Gr�C�Ö#Bu

IPJ

,8ЦÑÏK´c«�d�6;CÏTQ

<=>

 FPGA;EDK;ó¾x

;IPJ

;NPIà¢

;RocketIO;MPMC;PLBà¢

?@ABC

 TP3312  DEFGH

 A  DIJC

 1007-7820(2015)02-164-05

DesignofHighspeedDataTransceiverEmbeddedUserIPCoreBasedonEDK

FANXiaoxing,XIPengfei,MENGQi(MinistryofEducationKeyLaboratoryofElectronicInformationCountermeasureandSimulationTechnologyMinistry

ofEducation,XidianUniversity,Xian710071,China)Abstract ThispaperintroducestheuserIPcoredesignofmultichannelhighspeeddatatransceivermodule

FPGAbasedembeddedsystems.OftheXilinxsISEdevelopmenttools,FPGAdeviceshardcoreandsoftcoreFIFORocketIOisusedtodesigntheuserlogic.ThecustomFPGAIPcoreusedinembeddedsystemsispackedusingtheembeddeddevelopmenttoolsofEDK.Theeffectivenessofthemethodisverifiedbyactualtest.

Keywords FPGA;EDK;embedded;IPcore;NPIbus;RocketIO;MPMC;PLBbus

  a\�Øh��t¶9~�_wx

,FPGAXó

#8�+yw+\DE>a

。ÈÉ

,J6

FPGAö|

"Òa9ó#8Pft

PowerPC、ARMnó#s

FPGA£¢y

。P°Ntó#8Pft9

FPGA£¢1S³

?

FPGAÈ"

。¡Y�W

FPGAó#8È"�Ît�

ÂÌÍ9{ü¹í

,X)¹íy

,�Âò

FPGA£¢ý

�Ît'AåÕ9

IPñ�_��Ð�

,¡|�¶_�

¶�a�lå

。¡Y�Øh9Þ¡¤L

,'íãDt

�+9qw�¥

,wÕ�È"û`aX6ÂYZ

,�F

tÈ"9Ð�3ag

[1]。

U£È"

FPGAi,

,Xilinxªy°�t

EDK(EmbeddedDevelopmentKit),

ÒpaW

FPGAKoó

#8Pft

、ñ�¶�Õi,g4

,éêt'A*

PowerPCi,¿�9

IP�

,¢a

EDK~�i,�I'

í¹}i,�1�ãDqw�p

,�X

EDKy9

IP��åûÐÑi,â$Xi,y9¢a

。w

Xilinxª

y9ö��¶qwg4

ISE(IntegratedSoftwareEnvironment)

y45J6

EDKyÅ59

IP�

。ÈÉ

,�

x�Ît�Yóa

ISEy9

IP�¡�X

EDK67í

¢a9

IP�i,

。)i,�{N

FPGA*¢ï9F

:��mN

,VX�ÝKæ9Èû

!

 7> 9�

/S³aÁ

IP�%µÞ¡bâ

1H­

Ü

1 #Bu�Ö

IP!BÜ

1H­

,IP��W

Xilinxªy

Virtex-5FX�«9

PowerPC��ó#8�+i,

。aÁ

IP�m

^

PLB%E-ìX

PowerPC�+y

;m^��

GTX�

461

Page 2: %a K;H 6Ha|Õ! j=U ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... · 2019. 1. 17. · )3·)4 2015!"28#"2$ ElectronicSci&Tech/Feb15,2015!!!"#$%&#’()#*+,!"#$:20140626)*+,:"9:(1987—),fi,12345。3467:

ÛÜÝ

,X

:78

EDK1¿ÍËâ°0áâ;åã

IP�`

)3

·)4

!!!

"#$%&#'()#

*+,

�«w),

,*

FPGAïo~���mN

,),ª':

g��

60Gbit·s-1;),m^�æKÈ_

NPIì�

Ý#Kæjkt

MPMC,?0

MPMC��

,�m^

MPMCVXKæ�Ý

"

 2-DG/37? M<R î_

RocketIOGTXQ

Xilinxªy

FPGAy9��

,Q

�Y45ma;

、Ûa;

、¾È,

、¾N�9z1ð�

�«wt

。i,"¢aÉ��{N*

FPGAïo9F

:��mNÈû

i,\a

Virtex-5FXT�«

FPGA,P

GTX�E

¤;bí

[2]:(1)F:ýrg«w

,�ÂmÕ<=

750Mbit·s-1~65Gbit·s-19),ª':g

。(2)K

ótw)�UÅN_ì«�UÉ3KÈ

,ÚÛtïo

#�

。(3)/Õ��U),w)¹8

。(4)5å�ó

'��A#³

,�Ft�Ú;

。(5)�Øh9w¼G

�D

、ì«E;[@t_\ü�S[@t

,�FNO9

{Î;

。(6)<=°Â_lÂ!�

。(7)�Øh9¢

K�A�â

50/75Ω#[

,ÚÛtïì�â#[

(8)<=Ko9��_��Ë6c<K8

,¹%ó<

(9)8b/10bØ{Ù

,�Øh9Ì0£v�V

(COMMA)Ac

,¹8ÌÍ

,<=6Y��mN�ç

。(10)45

aÁ¸IDÅÀâ�

+,i,H�

,X

ISEy³´

Xilinx{¹

GTX�

�}Ù±F±

[3]�}

GTX�

,c<«w),;û

。i

,"

GTXÅÀ?

150MHzÒa�U

,30Gbit·s-1�

�:g

,\a

8b/10bØÙ

,Ko

16bit),

,K�V.

/

K285。â

2Ê�t¢a�£

GTX«w),9�Z

,â

2?a

Chipscopeî×9�Zâ

Ü

2 GTXJÈrÏÄÚÜ

X

Virtex-5FPGAý�}��mÕ�£

GTX�

tile0,X

FPGAïo"

tile0_0mÕ

GTX9w)â*

tile0_1mÕ

GTX9ì«â¿-

,ªN

tile0_0mÕw)

),

,tile0_1mÕì«),9mNË�

。m^w)ô

õÙ~�c<

,bâ

2H­

,tile0_1mÕì«s9),

5

30�p9/�

,¡Q.,X×�ý9�¥

。NO

tile0_txcharisk0_i?

“00”,�3

tile0_txdata0_iX�

ýw)9Q),

;NO

tile0_rxcharisk1_i?

“00”,�3

tile0_rxdata1_iì«s9Q),

,wåQjk�V

;N

O

tile0_rxbyteisaligned1_i?

“1”,�3

tile0_rxdata1_iì«s9),¯c£v

[2]。

#

 7}y[! 4>48 V 9>7 Øc

Xì«),�

,"

GTXì«â«s9),m^F

:),%E

NPI%E

[4]Ý#Kæ~��æ

;Xw))

,�

,²"),�#Kæ~��æ

,GTXw)âm^

NPI%E0Kæy×),

,i<w)�ø

。Xilinxªy

X

EDKqwg4¢�ÎtKæjktñ�

MPMC,£

Kæ9�Ýq>m^óa

MPMC{N

,ÈÉ�F:)

,«waÁ

IP�E

NPIì�*

MPMC~�),ª'

#

!

 4>48

MPMC(Multi-PortMemoryControlletr)Q�Âý

o<=r),ª'K8

(DDR_

DDR2)_ò),ª'

K8

(SDRAM)9�)}Kæjkt

[4]。MPMC5

8¿���9â�

,�Ââ�R�I��y~Kæ

MPMC9|�t½³�S9TÒ|��üSP²<

Õ�

,MPMC9�Ââ�[S5�æ

,HIXÝ#),

,),Q²Ý#�æ

,n¡Ââ�×ÍKæÝ#¬<

þ0�æÝ#Kæ

。),Ý#�æþÝ#Kæ9^h

£aÁå�Î

。HI£aÁ9����

,ðE"),

Ý#

MPMC9â�Ø�

MPMC9�Ââ�R�ÅÀN�I-ì

PowerPCPft

、MicroBlaze、CoreConnect_

MPMCNPIÞ¡9

Â;ì�KÈ

(PIMs)。MPMCÃ�Î

PLB、XCL、SDMA

_

NPI4Yì�

。XCL�EXPft9

Cache0Kæ�×),�¢a

;SDMAXïo),Ea

DMA¹8Ý#Kæ�¢a

,P<=

SGDMP;PLB�E

aWPftm^

PLB%Ey~Kæ

;NPIì�QXa

ÁXi,yªa

MPMC¤;9ì�

。i,\ajk

mÕ*),mÕAq9¹8

,åÃa%E

,�F;û

Py

,\a

PLBì�*Pft~�jkNò_HIN

ò9l¨

,\a

NPIì�y~Kæ

。â

3?X

EDK6

7í"

MPMC9â�ÅÀ�

PLB_

NPIì�

Ü

3 MPMC½4K7

561

Page 3: %a K;H 6Ha|Õ! j=U ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... · 2019. 1. 17. · )3·)4 2015!"28#"2$ ElectronicSci&Tech/Feb15,2015!!!"#$%&#’()#*+,!"#$:20140626)*+,:"9:(1987—),fi,12345。3467:

)3

·)4

ÛÜÝ

,X

:78

EDK1¿ÍËâ°0áâ;åã

IP�`

!!!

"#$%&#'()#

*+,

#

"

 9>7 |ny[!

NPIì�5Ií¤;

:(1)�Î�¹ò9Kæì

�Iê`åÕ�ç

。(2)�ÎF�E

、),E_jk

NO�~�Kæq>

。(3)Û0Õ�m^

FIFO~�

),9�

/Ý

。(4)�IÅÀN

32ð?

64ð9),�

ÖIê`åÕ9�+�z

[4]。

NPIì�jkt

(NPI_CTRL)aWVX

NPIì�

�ç

,),�Ö?

64ð

,<=

burstg>K8

,��

burst�?ݨ6�Iª'

256Byte),

,��

burst<�¶½/¸uÎF�

,Ísí�Â

burst9��

F�

w)),�

,NPIì�jkt

(NPI_CTRL)+,ì

Þ_ÅÀNò0KæyFS9��F�P�×FS)

A9),sw)),� =

(send_data_fifo),i<V

GTXw)s

FPGAï

;ì«),�

,GTXì«s9),

Ý#ì«),� =

(received_data_fifo),i<V

NPIì�jkt

(NPI_CTRL)+,ìÞ_ÅÀNò"),

Ý#Kæy9FS��F�P

â

4_â

5A�Q

MPMCy

64ð

NPIì�

128Byte�Ö

burst�_Ý�Zâ

[4]。ây

,sizeñ­

burst�

Ö

,addr�F�

。çE~�

burst�q>�

,²

"

sizei?

0x04,addri?

0x80,Õ�"

addrReqÀ

?5:ëzF�|�

,ç

AddrAck5:�ñ­F�ë

zÍsÛ0

,ÿ?

25�U�p<

,RdFIFO_PopN

O½5:ñ­),¯��

,c^

1Â

、2Â?

3�U

�p/4<

,��F�

0x80P9

128Byte),=½^

��XX

RdFIFO_Dataâ�

。çE~�

burstÝq>

,"

WrFIFO_PushÀ?5:

,X

WrFIFO_Push5:

�Ý#

32wordØ

128Byte),

,WrFIFO_BE?

0XFFñ­��Ý#9

64ð),[5:

,çÝs

32word9

¨<�Â�

,Ê�Ý#9��F�

addr_

burst�Ö

size,Õ�"

addrReqÀ?5:�ëzF�|�

,ç

AddrAck5:�ñ­F�ëzÍsÛ0

,ab

MPMCjkt"

WrFIFO9),Ý#KæFS��F�P

ç

WrFIFO9),ýoÝ#Kæ�

WrFIFO_emptyÀ

?5:

Ü

4 64ø

NPIÌ4

burstþ

Ü

5 64ø

NPIÌ4

burstû

$

 |ÕÙ}kí

VW¢a9åQòmÕ

GTX,ÈÉ),ð�åî

Å

。HISÆQ0Kæy×),V

GTXw�?"

GTXì«s9),Ý#Kæ

,R�E~��æPf

Xì«),�

,ò�mÕ

GTX9),ð�?

16bit,\a�mÕ~�),ª'

,HIÃ

32bit),

。NPIì

�\a9),ð�Q

64bit,HI�E~�ð�0¨

�ì«),Q1¸9

,ÈÉ��

GTXì«s9),å

�SX�¥ýÕ�

,�û5²<s�9��

,Èɪa

�

FIFO¡��å�æ

[5],{üð�åîÅ_�¥å

Õ�~�

。4µì«),�æhZÞ¡bâ

6H­

Ü

6 ÌaJÈ;W�÷!BÜ

6�Ösì«),�æKÈV

3ÂÅ�

FIFO¡N

。Py

First_fifo_1_

First_fifo_2?

16bit'#

16bit'�

,¡Nß�å�æ

;Received_data_fifo?

32bit'#

64bit'�

,?ß�å�æ

。m^�å�

æ

,"��

GTXì«s9

32bitåÕ�),0?

64bitÕ�),

,þm^

NPIì�Ý#Kæ

。ì«),�æ

KÈ9g>�Zm^

Chipscopeî×Þ5bâ

7H­

Ü

7 ÌaJÈ;W�÷ÄÚÜ

â

7y

,�mÕ

GTXw)9RQôõÙ

,Fitrst_fifo_1Ý#),<

First_fifo_2Ý#),o

2027�U�

661

Page 4: %a K;H 6Ha|Õ! j=U ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... · 2019. 1. 17. · )3·)4 2015!"28#"2$ ElectronicSci&Tech/Feb15,2015!!!"#$%&#’()#*+,!"#$:20140626)*+,:"9:(1987—),fi,12345。3467:

ÛÜÝ

,X

:78

EDK1¿ÍËâ°0áâ;åã

IP�`

)3

·)4

!!!

"#$%&#'()#

*+,

p

。Received_data_fifo��Õ�0

Fitrst_fifo_1_

Fitrst_fifo_2y��S�),

,�0?

64bit'�

m^�å�æ

,NÈ{üt��),åÕ�9~�

m^�å�æ

,),0?

64bit~#

NPIì�jkK

È

(NPI_CTRL),i<Ý#

MPMC。Xw)),�

,m^

NPIì�0Kæy�×9),

?

64bit,��

GTX9),ð�?

32bit,HIFQ�E

~��æI{Nð�0¨

。È?w)),Q�¸9

,H

IåæXw)åÕ�9~�

,ÈÉð�ªaÅ�

FIFO¡��å�æØ�

。4µw)),�æhZÞ¡b

â

8H­

。w)),�æKÈg>�ZV

Chipscopeî×Ís

,bâ

9H­

Ü

8 YfJÈ�÷!BÜ

Ü

9 YfJÈ;W�÷ÄÚÜ

9H­

,Send_data_fifo"0

NPIì�ì«s

9

64bit),0¨?

32bit,�ª'Ê��

GTX9w

tile0_txdata0_i_

tile0_txdata1_i。

%

 �j=U� 7> _6�½

Iý{N9ëKÈg>RðX

ISE67í{N�

�qw

,F�åûX

EDK67í°ì>?ó#8

IP�¢a

,ÈÉ�E~�

EDKaÁ

IP�9�;

。EDK?i,â$�Ît/¸}i,Ù±

(BaseSystemBuilder,BSB),

�IFùghHE:{Ni,^h

[1]。

m^ÉÙ±

,���W

PowerPC9¹òó#8�+

P

SystemAssemblyViewâ

,�+Þ¡âA�bâ

10_â

11H­

Ü

10 SystemAssemblyViewÜ

Ü

11 z£!BÜ

IP�m^

PLB%E-ìX

PowerPCPft

ý

。PLB%E

[6]Q�YFS�

、¾/4

、F;û9Pf

t%E

,aW-ìF;û

CPU、F:æätjkt

、|

�t

、F:9

DMAjktnF;û

、'S�9¢ýi

»

。VW

PLB%E�çNO6

,­34

,?¢aÁu

¹%F¢a

、�Eqw~Ö

,Xilinxªy?aÁqwt

y�aÁ

IP�Ù±

CIP(CreateandImportPeripheralWizard),

y�aÁ/S³

IP�

[7]。)Ù±/¸ÅN

PLB%E*aÁ���¥9ì�

,Ø

IPIF(IPInterface)。ªa

IPIF{ü

PLB%Eì�_aÁ��ì��¥9

。XaÁ��Ö�

,PLBì�ñX?¹ò9

IPIC(IPInterConnect)

ì�

。aÁ¢a)Ù±F�+,�

E./¿`9KÈ_Èû

[8]。i,y

PLB%Eða

WªôÛA9�)_HINò

,ÈÉ

,PLBKÈÅkN

t0i»

。��KÈ

SLAVEAttachment�Ît

PLB0i»9��Èû

,ÊX

PLB%E_

IPIC�¥���

ç_�Z90¨

,PLBKÈ9Þ¡bâ

12H­

Ü

12 PLBV46_SLAVE_SINGLE!BÜ

761

Page 5: %a K;H 6Ha|Õ! j=U ‚œ - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/forum/201509/... · 2019. 1. 17. · )3·)4 2015!"28#"2$ ElectronicSci&Tech/Feb15,2015!!!"#$%&#’()#*+,!"#$:20140626)*+,:"9:(1987—),fi,12345。3467:

)3

·)4

ÛÜÝ

,X

:78

EDK1¿ÍËâ°0áâ;åã

IP�`

!!!

"#$%&#'()#

*+,

PLBKÈy9

User_logic?X

ISE67íqw9

��

,ªNbâ

13H­

。"

RocketIOKÈ

,),�æ

,NPIì�

(NPI_CTRL)jkKÈa Ï-ì

,a

IPIC_

IPIF-�

,N?ó#8

IP�9��

Ü

13 �ÖRS!BÜ

¢a

CIPÅN9aÁ/S³

IP�ræX

EDKg

h$B9

pcorex¶�

,aÁ

IP�$Bbâ

14H­

Ü

14 �Ö

IPJ,ý!BÜ

x¶�

hdlaWæäaÁ

IP9

HDL¡Ù

,Ø

v?

vhdx¶

。i,¢a

VHDL�õ

[9],HIëKÈ9

HDL¡Ùx¶RræX

vhdlx¶�í

。x¶�

netlistaWræi,Has9,ñx¶

。�i,¢at

ISEg49

IP�

,RocketIO、FIFO、icon�

ila,P,ñx¶

RræX

netlistx¶�í

。x¶�

dataaWæäaÁ

IP9ÅÀx¶

[1]。MPDx¶?ôPftïiTç

(MicroprocessorPeripheralDefinition),S³tïiì

。X

MPDx¶y«�t%Eì�â�_Ñ]-ì

«�t�)_Ñ]�

。PAOx¶?ïiABìÞx

(PeripheralAnalyzeOrder),éêt

hdlx¶9«ñ

Qü�_S³ABìÞH�9

。BBDx¶�7S³

(BlackBoxDefinition)x¶

,ef1|}9�¶,G9

x¶ðÀ

,aWHi,ïi9�7oA

。º�

PowerPC¹ò�+gh

,ì«

FPGAïo),

,m^��ïO�

�Ý~

DDR2y9),

。Vâ

15�IÖs

,ôõÙ¼

�X8ð*åÕ�~�

,ñ3Hi,�stEz

Ü

15 ø4Â<�

DDR2þlJÈ

B

 ���

��t�Ya

ISE��qwg4y9

IP��¡

�ó#8qwÈ"

EDKy

,aÁ/S³

IP�9¹C

���i,{NtF:),«wmN9Èû

。Éï

i,\a��

GTX,�m^õ�

GTXmÕ)

,?@Å

À

GTX?uFS�

,Iõ��+S�

,45Ô®9�

x;

。i,X-ì

PowerPCPft9�+í{N

[10],

ðE\a

PLB%E

,É/S³

IP�I°ìÆ�s

MicroBlazePft�+y

,45Ԯ9�;

_`DE

[1] ø}

.¢ý�Øh�+Gf�`a

[M].Z[

:ÙN'(

�ST

,2010.[2] Xilinx.Virtex-5FPGAGTXtransceiveruserguide[M].

USA:XilinxConpration,2009.[3] Xilinx.Virtex-5FPGARocketIOGTXtransceiverwizardv1.

5gettingstartedguide[M].USA:XilinxConpration,2008.[4] Xilinx.Multi-portmemorycontroller(MPMC)(v.4.03.a)

[M].USA:XilinxConpration,2008.[5] Xilinx.FIFOgeneratorv4.4userguide[M].USA:Xilinx

Conpration,2008.[6] Xilinx.PLBusageinXilinxFPGAs[M].USA:XilinxCon

pration,2005.[7] 

©~�

,�ï�

,Wþ

.�*

XilinxFPGA¢ýó#8aÁ

IP�qw

[M].!"

:!"#$%&'(�ST

,2008.[8] Xilinx.PLBV46slavesingle(v1.01a)[M].USA:Xilinx

Conpration,2008.[9] 

oj�

,�Î

.VHDL�¶¬þ�õ*)���#�i,

[M].!"

:!"#$%&'(�ST

,1998.[10]

,W�Æ

,Xv

,n

.FPGAý9ó#8�+i,V�

[M].!"

:!"#$%&'(�ST

,2008.

861