241-440 computer system design lecture 2
DESCRIPTION
241-440 Computer System Design Lecture 2. Instruction Set Architecture. What’re the component of ISA?. Machine Instruction Set Instruction format Nature of the fetch through execute. Varies Programming Model. What must an instruction specify?. Which Operation is perform? ADD r1,r2,r3 - PowerPoint PPT PresentationTRANSCRIPT
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241-440 COMPUTER SYSTE
MDESIGN LECTURE 2
Instruction Set Architecture
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WHAT’RE THE COM PONENT OF ISA?
Machine Instruction SetInstruction formatNature of the fetch through execute
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VARIES PROGRA MMING MODEL
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WHAT MUST AN INSTR UCTION SPECIFY?
Which Operation is perform?
ADD r1,r2,r3Where to find the operands
ADD r1,r2,r3Place to store the result
ADD r1,r2,r3Location of next instruction
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BASIC ISA CLASS Accumulator (1 register)
1 address add A; acc <= acc + mem[A]
1 + x address addx A; acc <= acc + mem[A+x] Stack :
0 address add tos <= tos + next General Purpose Register
2 address add A, B
3 address add A, B, C
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BASIC ISA CLASSES(CON’T) Load/Store
load Ra, Rb Ra <= mem[Rb]
Store Ra, Rb mem[Rb] <= Ra
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COMPARE NUMBER OF INSTRUCTION
Code Sequence for C = A + B
Stack Accumulator Register Register
(reg. - mem) (load/store)
Push A Load A Load R1,A Load R1,A
Push B Add B Add R1,B Load R2,B
Add Store C Store C, R1 Add R3,R1,R2
Pop C Store C,R3
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CPU REGISTERStack Register Arithmetic Register &
Address Register 24
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GENERAL PURPO SE REGISTER
1975 - 1995 all machines use general purpose registers. Advanced of Registers
- faster than memory
- easier for compiler to use
- hold variables
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SUMMARY INSTRUC TION SET CLASS
Data Movement Instructions
- Load
- Store Arithmetic and Logic (ALU) Instruction
- Add, Sub, Shift … Branch Instructions
- Br, Brz, …
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- 3 ADDRESS MAC HINE AND ISA
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- 2 ADDRESS MA CHI NE I SA
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- 1 ADDRESS MAC HI NE ANDI SA
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- 0ADDRESS MAC HI NE ANDI SA
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EEEEEEEE - *a = (b+c) d e
-3 address -2 address -1 address EEEEE ,, EEE, load b EEEE E ,, add a,c EEE E push c
sub a,a,e mpy a,d mpy d EEE sub a,e sub e push d
store a mpy push e sub pop a
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REAL MACHINE Have mixture of 3, 2, 1 or 0 address instructions if ALU instructions only use registers for operands and result,
machine type is load-store mix of register-memory and memory-memory
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BREAK 5 MINUTES
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ADDRESSING MOE E
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ADDRESSING MOE E
Addr essi ng Mode Exampl es Meani ngRegi st er Add r4,r3 r4 <= r4 + r3I mmedi at e Add r4,#3 r4 <= r4 + 3
Displacement Add r4,100(r1) r4 <= r4 + mem[100+r1]indirect(r) Add r4,(r1) r4 <= r4 + mem[r1 ]
index+base Add r3,(r1+r2) r3 <= r3 + mem[r1+r2]Direct Add r1,(1001) r1 <= r1 + mem[1 0 0 1 ]
indirect(m) Add r1,@(r3) r1 <= r1 + mem[mem[r3]]-auto incre Add r1,(r2)+ r1 <= r1 +mem[r2 ];r2 =r2 +d-auto decre -Add r1, (r2) -r2 <=r2 d,r1 <=r1 +mem[r2 ]
scaled Add r1,100(r2)[r3] r1 <=r1+mem[100+r2+r3*d]
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MIPS REGISTERS - 31 32 0 0x bit GPR (R = ) - 32 32x bit FP register PC EE EE-E EEEEEEEEE EEEEEE EEEEEEEE
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0R1R
3R1
PC
lohi
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MEMORY ADDRESSING
EEEEEEE EE EEEEE EE E-EEEE EEEEEE1980, 8()
How do byte address map onto words? Can a word be placed on any byte boundary?
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ENDIANESS ANDALIGNMENT E E EE: 6 8, , , :8086,(, ) 2
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GENERIC OF INSTRUCT ION FORMAT WIDTH
Variable :
Fixed:
Hybrid:
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EEEEEEE EEE Variable length instructions, if code size is ver
y important. Fixed length instructions, if performance is mo
st important. Embedded Machine (ARM, MIPS) have optiona
-l mode to execute 16 bit . (decide performance or density)
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TO BE CONTINUOUS
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PART II : LECTURE2
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MIPS ISA TARGET Embedded System E EEEEEEEE EEEEEEE E EEEEEEEE EEEE, , , 2
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MIPS ISA2
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MIPS ADDRESSIN G MODES
- All instructions have 32 bit wide.
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MIPS ARITHMETIC INSTRUCTION
Instruction Example Meaning1.add 1 2 3add $ ,$ ,$ 1 2 3$ = $ + $2.subtract sub $1,$2,$3 ------------------
3.add imme addi $1,$2,100 ------------------ 4.add unsign 1 2 3addu $ ,$ ,$ ------------------
5. 1 2 3subu $ ,$ ,$ ------------------6. -----------------1 2100addiu $ ,$ ,7.multiply EEEE 2 3$ ,$
2 3Hi,Lo = $ x$8. multu $2,$3 ------------------
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MIPS ARITHMETIC INSTRUCTION
I nst r uct i on Example Meani ng9.divide 2 3div $ ,$ 2 3Lo=$ /$ ,
2 3Hi=$ mod$ ,10. 23Divu $ ,$11.mov mfhi $112. mflo $1
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MIPS LOGICAL INSTRUCTION
I nst r uct i on Example Meani ng13.AND EEE14.OR or15.XOR xor16.NOR nor17. EEEE18. ori19. xori
20.shift left logical sll $1,$2,1021. 1 210Srl $ ,$ ,
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MIPS LOGICAL INSTRUCTION
I nst r uct i on Example Meani ng 22 210.shift right arithm sra $,$ ,
( )23. sllv24. srlv25. EEEE
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MIPS DATA TRANSF ER INSTRUCTIONS 26. sw 500(r4),r3 Store word
27. sh 5 0 2 (r4 ),r3 store half word
28. 41 4 3sb (r ,r store byte29. lw r1,30(r2) load word30. 140 2Lh r , (r ) load half word31. 140 2Lb r , (r ) load byte32 lui r1,40 load upper
16 16immediate ( bits shifted left by )
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TESTI NGCONDI TION Condition Code
EEE 1 2 3r ,r ,rbz label
Condition RegisterEE E 1 2 3r ,r ,rEEE 1r ,label
Compare and BranchEEE 1 2r ,r ,label
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MIPS COMPARE A ND BRANCH
Compare and BranchBEQ rs,rt,offsetBNE rs,rt,offset compare to zero and BranchBLEZ rs, offsetBGTZ rs, offsetBLT <BGEZ >=BLTZAL 0 31if R[rs] < then branch and link(to R )BGEZAL >=
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MIPS JUMP, BRAN CH COMPARE
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SOFTWARE CONVEN TIONS FOR REGISTE
R2
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NOTE FOR MIPS INS TRUCTION SET
0 0R always = “ ” (even if u try to write) / EEE EEEE -+4 >31 Imme arith and logical are extended
- EE EEE EEEE EEEEEE EE EE EEEE32- arith imme op are sign extend to 32 bits
data loaded by lb, lh extended- lbu, lhu are zero extended- lb, lh are sign extedned
Overflow occur in ADD, SUB, ADDI EEEEE EE ’ ADDU, SUBU, ADDIU, AND, OR, XOR, NOR, SHIFT,
MULT, MULTU, DIV, DIVU
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MIPS ARITHMETIE 3Instruction has operands Operand order is fixed
Pascal Code : a := b + c; MIPS Code : 0 1 2add $s , $s , $s
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MIPS ARITHMETIE
Pascal Code : E EE: = + + ; - e := f a;
MIPS Code : 0 1 2add $t , $s , $s 0 0 3add $s , $t , $s 4 5 0sub $s , $s , $s
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REGISTER & MEMORY Registers were used in Arithmetic Instructions
- 32 registers
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MEMORY ORGANIZATION Memory is an index into the array Byte Addressing = points to a byte of memory 2
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1 8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data
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MEMORY ORGANIZATION - 32 4For MIPS, a word is bit or bytes232 bytes with byte addresses from 0 to 2
-321
230 words with byte address from 0, 4, 6, …,2
-324
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32 bits of Data32 bits of Data32 bits of Data32 bits of Data32 bits of Data32 bits of Data
48
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MIPS LOAD/STORE INSTRUCTION
Code : [8 ] = + [ 8 ] ; 8 8 4 32A[ ] ==> x = (word alignment)
MIPS Code : lw $t0,323($s ); 0 2 0add $t ,$s ,$t ;
sw $t0,32 3($s );
Arithmetic Operand is Register, not Memory!!
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EXAMPLE : Swap (int v[], int k);
EEEEE{ ; temp = v[k];
1v[k] = v[k+ ]; swap:1v[k+ ]=temp; lw $15, 0[$2]
} lw $16, 4[$2] sw $16, 0[$2] sw $15, 4[$2]
31jr $
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MEANING
EEE 2 4 2$ , $ , $ 2 4 2$ = $ + $ ;lw 16 0 2$ , [$ ]
16 0 2$ = Memory[ + $ ]sw 15 4 2$ , [$ ]
4 2 15Memory[ +$ ] = $
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MACHINE LANGUAGE Instructions, like register & words of data are
32bits long.- 0 1 2add $t , $s , $s- 0 9 1 17 2 18register : $t = , $s = , $s =
Instruction Format
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MACHINE LANGUAGE - I type for Data transfer instruction Example : lw $t0, 32($s2) 2
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CONTROL Decision Making instructions MIPS conditional branch instructions:
- 0 1bne $t , $t , label- beq $t0, $t1, label
: ( =) = +;EEE 01$s ,$s ,LabelEEE 3 0 1$s , $s , $s
Label : ...
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CONTROL MIPS unconditional Branch Example :
if ( i != j) EEE 4 5$s , $s , label;h=i+j; EEE
3 4 5$s , $s , $s ; el se E lab2
-h=i j; lab1 : sub $s3 , $s4 , $s5 lab2 : …
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SUMMARIZE :2
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HOMEWORK
Use MIPS Assembly to write program.
1. “Factorial Program” n is input, Example : if n=3,
3 3 2 1 6result = ! = x x =
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HOMEWORK
Use MIPS Assembly to write program.
2 E EEEE EEEEEEE EEEE EEE E EEE EE EEE MIPS instructions
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MIPS INSTRUCTI ON ENCODING
EEEEEE EEE E EEE EEEEEE EE EEE 318Figure .
Page 153,
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