241-440 @ w.s. 24-440 computer system design lecture 7 wannarat suntiamorntut

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241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

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Page 1: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

2 -4 440 Computer Syste

mDesign Lecture 7

Wannarat Suntiamorntut

Page 2: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

PIPELINE

Page 3: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipeline in the R eal world

30Washer takes minutes 33 333333330 33 333333330 33 333333330

Page 4: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Sequential Laundry

8 4take hours for loads

Page 5: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipeline laundr y

333 3 333333.5 4

Page 6: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Datapath opera tion in MIP

333333 / 3333 333 33

Page 7: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Apply Pipeline

Page 8: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipeline Executio n Representation

Page 9: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipeline give us If we would like to execute 100 instructi

333 33:45/ 11 00= 4 500 Multiple cycle : 10ns/cycle x 4.6 CPI x 10

0 = 4600 ns Pipeline (Ideal) : 10ns/cycle x (1 CPI x 10

0 + 4 cycle drain) = 1040 ns

Page 10: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Comparison : singl e, multiple, pipeline

Page 11: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipeline Hazard Structure Hazard

Same resources at the same time Data Hazard

Instruction depend on result of priorinstruction

Control Hazard Br anch I nst r uct i on

Page 12: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Single Memory ( Structure H.)

Page 13: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Control H. Solution

Page 14: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Control H. Solut ion (Predict)

Page 15: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Control H. Solut ion (Delay)

Page 16: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Data H. 333 r1 , 2, 3 333 2 r1 336 and 7r , r1 , 5 33 4r , r1 338

Page 17: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Data H. on R1

Page 18: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Data H. (By pas sing) with Load

Must Solve by Delay / Stall

Page 19: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Pipelined Processor

Page 20: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Control and Datapath

Page 21: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

-Load and R type

Pipeline Conflict or Structural Hazar3

Page 22: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Observation Each unit can only be used by one instruction

Each unit must be used at the same stage for all instructions

3333 33 33333 3333 33333332

Page 23: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

1. Insert Bubble into pipeline

Page 24: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

-2. Delay R type

Page 25: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Modifies Contro l & Datapath

Page 26: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Datapath + Control

Page 27: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Try it 10 lw 1 2 35r , r ( )14 addl 2 2 3r , r ,20 sub 3 4 5r , r , r24 beq 6 7 100r , r ,30 333 8, 9, 17r r34 add 10 11 12r , r , r

100 and 13 14 15r , r ,33333 333333

Page 28: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

10Fetch :

Page 29: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

Fetch1 4 / Deco de 10

Page 30: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

3 3332 0

de 14, Execute10

Page 31: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Mem10

Page 32: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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10WB

Page 33: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Page 34: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Page 35: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Page 36: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Page 37: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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Page 38: 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

241-440 @ W.S.

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