17-1 maven iper may 22-23, 2012 particles and fields package pre-environmental review may 22 -23,...

17-1MAVEN IPER May 22-23, 2012

Particles and Fields PackagePre-Environmental Review

May 22 -23, 201217 - PFDPU

D. Gordon / W. Donakowski PFDPU Team

Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission


Introduction

Topic/Content Presenter Allocated Time Duration

Overview/Block Diagram D. Gordon 0:05

Electrical (Status/Test Results)

D. Gordon 0:10

Mechanical(Status/Test Results)

W. Donakowski 0:10

Vibration W. Donakowski 0:05

Thermal Vac D. Gordon 0:05

Wrapup /Questions D. Gordon 0:05


Overview

Electrical Components covered in this presentation:

• DCB• REG• IIB

Remaining PFDPU resident boards are covered by the Instrument specific presentations.

Mechanical presentation covers the entire PFDPU

Vibration and Thermal Vacuum Procedures performed on the entire PFDPU


PFDPU Hardware Team

• DCB (Processor)– Dorothy Gordon

• REG (Power Supplies, Switches and Actuator Control)– Peter Berg and Dennis Seitz

• IIB (Instrument Power Regulators and Signal Distribution)– Chris Tiu

• Mechanical– William Donakowski

• QA and Manufacturing – Jorg Fischer– Chris Scholz – William Whitehead (visiting, R&QA)– Mike Raffanti

• PFDPU Resident Instrument Boards– SEP/DAP Team (SSL)– DFB/BEB Team (LASP)– MAG Team (GSFC)


Electrical Block Diagram

Regulated Power

Serial Data Interface

Electrostatic Analyzer

SWEA Electronics

Electrostatic Analyzer

SWIA Electronics

LPW Boom/Sensor (2)

LPW Electronics

EUV Sensor Sensors

SEP Electronics

MAG Sensors (2)

Sensors

MAG Electronics

ESA/TOF Analyzer

STATIC Electronics

LVPS A LVPS B DCB A DCB B

C&DH A C&DH B C&DH A C&DH B 28V Bus 28V Bus

SEP Sensors (2) Sensors

PFDPU IIB not shown, sits between LVPS(REG)/DCB and the Instruments

REG2REG1 DCB1 DCB2


Relevant Documentation

• MAVEN_PF_SYS_004 – PFDPU to Instruments ICD• MAVEN_PF_SYS_003 – Power Converter Requirements• MAVEN_PF_PFDPU_001 – Data Controller Board Specification• MAVEN_PF_SYS_021_PowerDistribution• MAVEN_PF_SYS_014_Grounding• MAVEN_PF_SYS_013 – Harnessing Drawing• MAVEN_PF_SYS_016 – Connector Pinouts• MAV-IDP-MEC-002 MAVEN PFDPU• MAV-IDP-MEC-020 DAP Assy • MAV-IDP-MEC-022 IIB Assy • MAV-IDP-MEC-026 REG Assy • MAV-IDP-MEC--028 DCB Assy • Schematics & PCB Layouts (REG, IIB, DCB, FPGA Daughter Board)• MAVEN_PF_TP_046_PFP_FM_Integration&Test• MAVEN_PF_TP_042_REV A PFDPU_Vibration_Test Procedure• MAVEN_PF_TP_044_PFDPU_Thermal_Vac_Test• MAVEN_PF_TP_031_PFDPU_CPT• MAVEN_PF_TP_045_PFDPU_LPT


Status/Test Results - DCB

• DCB and FPGA Daughter Board– Both Flight Boards have been received and have passed board

level test• MAVEN_PF_PFDPU_DCB_600C_TESTPLAN

– Initial test using prototype FPGA daughter board– Final test/characterization using flight FPGA daughter board– Cleaning/Conformal Coat and final assembly completed– Following board level recheck, ready for PFDPU Integration

• FPGA– Final flight port completed as of 28 FEB 2012– Static Timing Analysis predicts 21 MHz operation over

temperature/radiation environment (FPGA SCLK = 16.8MHz)– Flattenned/backannotated simulation verification– All realtime tests successful


DCB and FPGA Daughter Board


DCB Current Measurements

Actual current drain is somewhat less than predicted (FPGA Designs tools have tended to give pessimistic estimates).

Draw on analog supplies has been reduced by keeping the ADC in standby mode most of the time. Stability of supplies has been verified with REG board.

Power turnon profiles of FPGA supplies verified with REG/DCB boards (stable within 5 ms, 1.5V supply on prior to 3.3V supply crossing to a logic “high”).

VoltageNominal Current

(PREDICT)

Max Current(PREDICT)

Measured On Flight Boards

at Ambient+5VA 20mA 50mA 17ma / 1 mA

-5VA 25mA 50mA 25ma / 1 mA

+5VD 5mA 10mA 1mA

+3.3VD 220mA 450mA 65 – 100 mA

+1.5VD 150mA 350 mA 95 – 110 mA

17-10MAVEN IPER May 22-23, 2012

Status/Test Results - REG

REG FM1

17-11MAVEN IPER May 22-23, 2012

REG Test/Qualification

Tests in process for FM1 and FM2:System clock syncMain converter inrush currentOutput switches functionOutput voltage regulation and ripple over output load and input voltage rangesEfficiency versus input powerMain transformer waveformsCurrent and voltage monitor calibrationsOutput over-current sense functionOn board thermometerActuator section inrush currentActuator functionActuator dead man timer function

Status:Improved resistor is required for the Current Monitor (IMON) circuit

Awaiting Flight parts (Vishays) (due 5/14)Soft start modification/test underway

17-12MAVEN IPER May 22-23, 2012

IIB

Flight IIB

17-13MAVEN IPER May 22-23, 2012

IIB Test/Qualification/Status

Flight board tests completed:Parts installation inspection Connector pin-to-pin measurements Tantalum capacitor power-on polarity Power converter waveforms Output voltage regulation Output voltage ripple Input current ripple Power efficiency

Measured EfficienciesLPW Half load: 73.7% Full load: 77.8%

SEP Half load: 73.7% Full load: 78.6%

MAG1 Half load: 62.6% Full load: 70.1%

MAG2 Half load: 61.2% Full load: 70.6%

Status:Cleaning completedConformal Coat scheduled for week of 14 MAY 12

17-14MAVEN IPER May 22-23, 2012

PFDPU CPT and LPT

• Comprehensive and Limited Test Plans– Exercise the DCB and REG (and the IIB as needed)

• Focus on subsystems not covered by the Instrument CPTs– Flexible configuration

• Can be run with any number of instruments integrated• Option to perform MAG Heater Control and Actuator Subsystem checkouts• Can be performed with GSE or Instrument Hardware

– Analog Housekeeping logged to facilitate trending• Most test executions run at 28V IN to allow comparisons between various

results• CPT

– One hour test per instrument • Goal: run the CPT for the entire suite within 1 day• Tests both sections of the PFDPU (redundant DCB/REG) and both S/C

Interfaces (redundant A/B sides)• LPT

– Reduced version of CPT (runs in about 10 minutes)• Goal: run the LPT for the entire suite in about 1 hour

– Operates on one section of PFDPU and one S/C Side (configurable per test)

17-15MAVEN IPER May 22-23, 2012

PFDPU Integration and Test Flow

PFP PER

PFP EMC Tests

PFDPU Magnetics

PFP CPT

PFDPU Vibration PFDPU CPT PFDPU +MAG TVac

SEP Sensor Vibration

SEP Sensor Magnetics

MAG Sensors

SEP Sensor TVac

LPW Boom Magnetics

LPW Boom Vibration

LPW Boom Tvac (Hot/Cold Deploy)

SWEA Magnetics SWEA Vibration SWEA CPT SWEA TVac PFP CPT

PFP PSR

SEP Sensor CPT

LPW Boom post-vibe deploy

LPW Preamp Thermal Vac

STATIC Cal

SEP Cal

SWIA Magnetics SWIA Vibration SWIA CPT SWIA TVac

STATIC Vibration & AccousticsSTATIC Magnetics STATIC CPT STATIC TVac

SWIA Final Cal

EUV Final Cal

5/21-5/22

7/16-7/27

7/27

8/7-8/98/6 8/10 8/21-9/5

8/6-8/107/30-8/3 8/13-8/16 8/17 8/21-9/5

7/30 7/31-8/5 8/6 8/7-8/20 8/24-9/5

7/30-8/24 8/27 8/28-8/31 9/4 9/5-9/20

7/30-9/5

7/30 7/31-8/5 8/6 8/7-8/20

7/30 – 8/8 8/9 8/9-8/16 8/18-9/148/17

MAG Final Cal

9/6-9/10

9/28-10/11

10/30

17-16MAVEN IPER May 22-23, 2012

PFDPU PFRs

The majority relate to manufacturing issues, minor layout or parts tuningMost require minor rework, for some the disposition is to “leave as-is”Solutions are implemented, we are awaiting final sign-off

PFR_052 (REG) involves damage requiring parts replacementFRB heldAnalysis identified damaged or stressed partsAll damaged and stressed parts replaced and re-testedReady to close

DescriptionAssembly

SubAssy

Component

Engineer

MRB Waiver Link

Date opened

MAVEN_PFR_015_REG_PWB PFDPU REG D. Seitz X REG1 done, waiting for REG 2 as of 4/23/12 .MAVEN_PFR_036_PFDPU_REG_501A_SN101-002_post_JPL_inspection PFDPU REG D. Seitz X waiting for signatures 4/23/12 4/19/2012MAVEN_PFR_037_NCR_PFDPU_REG_monitor_gains PFDPU REG D. Seitz waiting for signatures 4/23/12 4/19/2012MAVEN_PFR_038_NCR_PFDPU_REG_monitor_offsets PFDPU REG D. Seitz awaiting procurement; NCR PFR and rework docs in progress 4/23/12 4/19/2012MAVEN_PFR_039_NCR_PFDPU_REG_Q16_Q23 PFDPU REG D. Seitz replacing two transistors that were under-rated 4/19/2012MAVEN_PFR_040_PFDPU_REG_buck_rework PFDPU REG Buck D. Seitz X MRB on 4/18/12, paperwork written, mods to FM1 and FM2 in progress 4/23/12MAVEN_PFR_041_NCR_PFDPU_REG_loop_adjust PFDPU REG D. Seitz To be writ ten and out for signatures on 4/23/12 4/23/2012MAVEN_PFR_042_PFDPU_DCB_FPGA_DB_J3 PFDPU DCB FPGA Gordon X PFR writ ten, to go to MRB soon 5/4/12 4/23/2012MAVEN_PFR_043_PFDPU_IIB_Layout_Gnd_Error PFDPU IIB Layout Tiu X waiting to see if we need an MRB, rework started 4/24/2012MAVEN_PFR_048_NCR_PFDPU_REG_FM1_L9 PFDPU REG D. Seitz Changes to be made and tested bef. Conformal coating 4/27/2012MAVEN_PFR_049_NCR_PFDPU_REG_OC_outputs PFDPU REG D. Seitz Changes to be made and tested bef. Conformal coating 4/27/2012MAVEN_PFR_050_NCR_PFDPU_REG_Inrush_Timing PFDPU REG D. Seitz Changes to be made and tested bef. Conformal coating 4/27/2012MAVEN_PFR_052_PFDPU_REG_SN101-001_Actuator_Reverse_Voltage PFDPU REG Actuator D.Seitz X 5/4/2012

17-17MAVEN IPER May 22-23, 2012

Requirements Validation (FRD and ERD Based)

FRD BasedID Title Revision F, CCR-0389 Links

from Verification

Verification

Verification Description Responsible Person

Verification Status

Verification Event

Verification Documentation

PF20 PFDPU Instrument Electronics

The PFDPU shall house the instrument electronics for MAG, SEP, and LPW.

MRD239 PFDPU Inspection

see PDR & CDR presentation material on PFDPU design

Gordon

completePFP iCDR

MAVEN_PFIS_RVW_0069, MAVEN_PF_ICDR_10_PFDPU, slides 10-7, 10-9, 10-31

PF22 PFDPU Boot Memory

PFDPU shall implement a boot memory segment that is non-writable in-flight.

MRD244 PFDPU Inspection

see PDR & CDR presentation material on PFDPU design

Gordon

Complete CDR

MAVEN_PFIS_RVW_0069, MAVEN_PF_ICDR_10_PFDPU, slide 10-67

ERD BasedID SYS-RQMT-0010, Revision M (CCR-0406, Dated

12/14/2011)PFP RQMT

Waiver / Deviation

Additional Impacts

Responsible Person

Verification Level

Verification Method

Verification Event

Verification Status

Verification Description

604 Redundant Component TVAC TestingRedundant components shall be exercised suffi ciently during the test program, including cold and hot starts, to verify proper orbital operations. Testing to validate all applicable operational modes shall be performed. The method of conducting the tests shall be described in the environmental verification test specification and procedures

Y Gordon PFDPU Test Component Thermal Vac Tests

Thermal Vacuum tests

17-18MAVEN IPER May 22-23, 2012

Requirements Validation (ICD Based)ID Spacecraft to Payload ICD [MAV]

Verif. Method

[MAV] Responsible Org.

Verification Level

Verification Description

Resonsible Person

Verification Status

Verification Event Verification Documentation

ICD801 3.1.2.1 Unregulated Power Switches

Title

ICD805 The payload shall operate nominally with an input voltage range of 24-36V.

Voltage at the payload interface during nominal operations is expected to range from 28V to 31V.

Test Payload

Package Power subsystem test BergPackage Integration Test report

ICD1403 The payload shall survive without damage indefinitely in an input voltage range of 0 - 36Vdc.

Test Payload

Package Power subsystem test BergPackage Integration Test report

ICD837 3.1.2.7 Power Fault Handling Title

ICD839 Each payload shall survive the sudden loss and reapplication of power without warning.

Test PayloadPayload Power subsystem test Berg

PFP pre-delivery ATP (CPT) Test report

ICD866 3.1.3.2 Asynchronous RS-422 Data/Telemetry Electrical Interface

Title

ICD867 The spacecraft C&DH shall provide an A-side and a B-side, asynchronous, data/telemetry RS-422 interface for each DPU.

Spacecraft

ICD868 Instrument signals shall be provided to the active spacecraft C&DH only (voltages shall not be applied to Off spacecraft C&DH).

Test Payload

PFDPU Functional Test Gordon

Component functional tests (pre-PFP package I&T) Test report

ICD869 The instrument shall send telemetry only to the active spacecraft C&DH based on the side indicator signal shown in figure 3.1.3-1.

Test Payload



ICD870 Upon power on, the Payload shall autonomously detect the active S/C interface side using the side select indicator before enabling its RS-422 drivers. Disabled instrument drivers may be either powered off or tri-stated.

Test Payload



Snapshot of PFDPU Requirements (First 6 out of 25 PFDPU Related Requirements shown above). Excerpted from MAVEN_PF_SYS_033B_VerificationMatrixMost items verify the S/C to PFDPU Interface (both functional and low level hardware)Some items are tested/verified with the FM I & T Procedure; others will require dedicated test reports. Some functional tests are generic and can be performed on the ETU with results extrapolated to Flight.

17-19MAVEN IPER May 22-23, 2012

MAVEN PFDPUParticle and Fields Data Processing Unit

Bill Donakowski

UCB/SSLMechanical Engineer

[email protected]

17-20MAVEN IPER May 22-23, 2012

PFDPU Overview

11 Individual Cards Bolted Together Open Frames, 6061 T6 Al Separate S/C Attach Bracket Bolted to S/C via 6 X 8-32 bolts

Thermally coupled to S/C Electrically grounded to S/C

Ground Straps Straps provided by L-M

Black anodized exterior surfaces No Thermal Blankets Mass CBE 7 Kg

17-21MAVEN IPER May 22-23, 2012

PFDPU STATUS and SCHEDULE

• Analysis (FEM Dynamics/Steinberg) Completed• Box Structural Enhancements Incorporated• Flight Hardware Status

– UCB Flight Hardware Build nearly complete (SEP/REG/DCB/IIB)– LASP hardware (BEB/DFB) delivery imminent– GSFC hardware (MAG, ACHE) delivery imminent

• Card Electrical Check-out May/June 2012• Complete PFDPU Build-Up July 2012• Vibration Testing August 2012• TVAC Testing August - September 2012 (UCB/SSL)

17-22MAVEN IPER May 22-23, 2012

Structural Dynamics Analysis

• Steinberg Fatigue Life Analysis/FEM Analysis Approach Utilized

• Concern: Failure of electrical components (primarily leads of large chips) due to fatigue

• Analysis Completed on Individual Frames and PFDPU Assy– UCB (Pankow) for DEB, REG, SEP, IIB– LASP/GSFC for MAG, DFB, REG– Analysis reviewed and approved by Project

• Project Design Guidelines Established– Individual Cards redesigned to increase stiffness – Max card stiffness below 300 Hz – PFDPU Structural Packaging stiffness increased

• Minimum 600 Hz (2 X 300 Hz)• Per Steinberg approach

17-23MAVEN IPER May 22-23, 2012

Box Structural Enhancements

Each Side Box Frame Walls Thickness increased to .150” (was: .100”)(6061 T6)

Frame Side Walls Thickness Increased; New Shear Panels Introduced

4-40 Screws and Washers

New 2 X Side Shear Panels, .080” Thick

(6061 T6)

PCBs bonded to Frames Hysol EA9309 w/ Boron Nitride FillerSEP, REG, IIB, DCBIncreases Box StiffnessAllows better thermal path to Frames

LASP/GSFC Cards Frames redesigned by host organizations to stiffen frames

17-24MAVEN IPER May 22-23, 2012

PFDPU Vibration Testing

• Test Procedure MAVEN_PF_TP_042_PFDPU_Vibration_Test

• Scheduled for August 2012• First test of completed Unit• Protoflight Hardware• Hardware to be kept clean by bagging• Standard Test Protocols Pass/Fail Criteria• Box unpowered throughout testing• Pre- and Post- electrical checkout to be performed at SSL

17-25MAVEN IPER May 22-23, 2012

MAVEN PFDPU TVAC Testing

17-26MAVEN IPER May 22-23, 2012

PFDPU TVAC Testing

• Test Procedure – MAVEN_PF_TP_044_PFDPU_Thermal_Vac_Test

• Scheduled for August - September 2012• PFDPU TVAC to be performed in SSL Chamber (Snout 1)• Hardware to be kept clean by bagging during transfer to

Thermal VAC Chamber• Overview has been presented by Thermal Engineer

– One non-op cycle from –30 to +60C– 7 operational cycles from –30 to +50C (as measured at the

baseplate)– Bakeout at 60C following the Electrical Testing

AFT Min AFT Max FA Min FA Max PF Min PF Max AFT Min AFT Max PF Min PF MaxParticles and Fields PFDPU -20 45 -25 50 -30 55 -20 50 -30 60

Instrument Operating Temperatures (°C) Non Operating Temperatures (°C)

17-27MAVEN IPER May 22-23, 2012

PFDPU TVAC Cycles

Performance test executed at each hot and cold plateauCPT (performed at first and last hot/cold cycles) verifies both redundant sections of the PFDPU, along with PFDPU resident instrument functionality (such as Actuators and Heater subsystems)Flight Magnetometers in chamber with PFDPU for TVAC qualification

Cycle Number: 32 4 5 6 71

21

3

4

5

6 7

9

8 n

17-28MAVEN IPER May 22-23, 2012

PFDPU TVAC Functional Plan Overview

17-29MAVEN IPER May 22-23, 2012

PFDPU TVAC Hardware/GSE Configuration

MAG 1 P F -J 2 6

M A G T herm al G SEG S E

S ig n a lI nto H o s t P C

F e e d -Th ru C o n n e c t o r

G S E _ E t h e rn e t

SEP DetectorE TU -H W

S ID E A o r S I D E B

Mag netom eterF L T-H W

P FDP U FLT-HW

HO ST PC GSEG S E

R S 2 3 2 -I F (D B 9 )E t h e rn e t

IIBP F -J 1 3

P F -J 2 3P F -J 1 8

P F -J 0 2

P F -J 0 1

REG 2P F -J 2 1

LPW D FB P F -J 0 7


Po w er Sw itch G S E

2 8 V _ A C T

2 8 V _ O P

2 8 V

t o H o s tP C

Data Archiving andInterface toInstrument SpecificGSE computers

Po w er Su p p lyG S E

2 8 V

ADAPT ER PLAT EM G S E

LPW PreAm psE TU -H W

DC B 1P F -J 1 2

Tests alternatebetween S/C Side A andS/C Side B cablesduring the performanceof the CPT.


A ctu ato r Sim ulato rG S E

t o H o s t P C

A c t C n t lI n

t o H o s t P C

Tests are divided between PFDPURedundant Sections 1 and 2. WhenSection 1 is used the PowerSwitch drives J11 and the S/CSimualtor drives J12. WhenSection 2 is used the the PowerSwitch drives J21 and the S/CSimualtor drives J22.




DC B 2P F -J 2 2

M ISG (In s t Sim u lato r)G S E

E t h e rn e t

M I S G -J 9

Mag netom eterF L T-H W

SEP 2 P F -J 2 6

G S E _ E t h e rn e t

S/ C Sim u lato rG S E

S C S I M -J 1

S C S IM -J 3

SEP DetectorE TU -H W

T herm a lV ac uumC ham b er

REG 1P F -J 1 1

LPW BEBP F -J 1 7

P F -J 2 7

SEP 1 P F -J 1 6

MAG 2 P F -J 2 5


17-30MAVEN IPER May 22-23, 2012

PFDPU – Wrapup/Questions

• Much progress since CDR of May 2011• Flight Hardware has been built and associated risks retired

– Manufacturing: CGA624 manufacturing successful– Mechanical: Improvements to PFDPU allay vibration concerns– Thermal: Heat conduction path enhancements & lower than expected

current draws• Hardware/Software Integration validated with the ETU PFDPU

– Operates as a parallel/alternate PFDPU Testbed– ETU Instruments have been combined into this setup– Available for “dry runs” of the CPTs, RTSs and software testing

• High-Fidelity Simulator (ETU DCB and REG) functioning successfully at Lockheed-Martin since March’12 delivery

• Integration of Flight PFDPU proceeding• Next Steps: Environmental Testing

– EMC => Vibration => Magnetics => TVAC

17-31MAVEN IPER May 22-23, 2012

Backup Particle and Fields Data Processing Unit

17-32MAVEN IPER May 22-23, 2012

Controlling Documents

• Mission Requirements– MAVEN_PF_QA_002, PFP Mission Assurance Implementation Plan – MAVEN-PM-RQMT-0005D_MRD.xlsx – MAVEN-PFIS-RQMT-0016D+_2-7-2011.xlsx– MAVEN_PF_SYS_033B_VerificationMatrix.xlsx

• Systems Requirements Document– MAVEN_PF_SYS_003 – Power Converter Requirements– MAVEN-SYS-RQMT-0010 – Environment Requirements

• Interface Control Documents– MAVEN_PF_SYS_004I_PFDPUtoInstrumentICD – MAVEN-SC-ICD-0007 - Spacecraft to PF ICD– MAV-IDP-MEC-003 MAVEN PFDPU MICD

17-33MAVEN IPER May 22-23, 2012

PFDPU Driving Requirements (1)ID Title Verification Level Verification Method Description Mission Requirements DocumentPF11 PFDPU Redundancy Package Inspection, design

documentation, PDR, CDR

The common parts of the PFDPU (Power regulator and switching, spacecraft interface, and processing element) shall be redundant, with interfaces to the (single string) instruments designed such that no credible single point failure shall cause the loss of mission.

Object Identifier:MRD236

PF12 PFP Processing Element Package Inspection, design documentation, PDR, CDR

The PFDPU shall contain a single Data Control Board (DCB) per side containing a common processing element to control and process data from PFP instruments and interface with the spacecraft

Object Identifier:MRD236 Object Identifier:MRD239

PF13 PFP to Instrument Signal Interface Package CPT The PFDPU shall combine the instrument interfaces from the two redundant PFDPU processing systems into a single interface to each instrument such that either side can communicate with each instrument when the other side is powered off


PF14 PFP to Instrument Signal Interface Package CPT The PFDPU shall combine the instrument interfaces from the two redundant PFDPU processing systems into a single interface to each instrument such that no damage occurs if both sides are powered on at the same time


PF15 PFP Power Distribution Package CPT Each redundant side of the PFDPU shall convert primary unregulated 28V from the spacecraft into regulated 28V which it shall switch separately to each instrument as specified in the PFDPU to Instruments ICD. Power services include one each for SWEA, SWIA


17-34MAVEN IPER May 22-23, 2012

PFDPU Driving Requirements (2)ID Title Verification Level Verification Method Description Mission Requirements DocumentPF16 PFP Sudden Removal of Power Package Power system test PFP shall survive a sudden removal of

power (without warning)Object Identifier:MRD235

PF17 PFP to Instrument Power Interface Package CPT The PFDPU shall combine the regulated, switched 28V from the two redundant PFDPU power converters into a single service to each instrument such that either side can provide power when the other side is powered off


PF18 PFP to Instrument Power Interface Package CPT The PFDPU shall combine the regulated, switched 28V from the two redundant PFDPU power converters into a single service to each instrument such that no damage occurs if both sides are powered at the same time


PF19 PFP MAG Heater Power Package MAG thermal vac The PFDPU shall include two circuits (one per MAG sensor), each of which will take an unregulated 28V power service and generate an AC heater power service, including a feedback loop from a temperature sensor in each MAG sensor.


PF20 PFDPU Instrument Electronics PFDPU Inspection The PFDPU shall house the instrument electronics for MAG, SEP, and LPW.

PF21 MAG Redundancy Package Inspection There shall be two MAG sensors with separate interfaces to the PFDPU such that no credible single point failure shall cause the loss of data from both sensors


PF22 PFDPU Boot Memory PFDPU Inspection, design documentation, PDR, CDR

PFDPU shall implement a boot memory segment that is non-writable in-flight.


PF99 Mission Lifetime Package Instrument The PF instrument shall be designed to meet a mission lifetime of at least 23 months after launch (cruise 10 months, transition to final orbit 1 month, nominal mapping operations 12 months)
