1 Evgeny Bolotin – ICECS 2004

Automatic Hardware-Efficient Automatic Hardware-Efficient SoC IntegrationSoC Integration

by QoS Network on Chipby QoS Network on Chip

Electrical Engineering Department, Technion, Haifa, Israel

Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

QNoC Research Group, Electrical Engineering DepartmentTechnion – Israel Institute of Technology

Haifa, Israel

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OutlineOutline

• Introduction: SoC Integration Challenge

• NoC Concept and QNoC Architecture

• SoC Automatic Integration by QNoC

• Summary

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The Integration Challenge:The Integration Challenge: Growing Chip DensityGrowing Chip Density

1998Asic - 0.35 m

2004SoC – 90 nm

Memory, I/O

P

• Design complexity - High IP reuse

• Scalable and Efficient, High Performance Interconnect

• Integration Challenge

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The Growing Gap: Computation vs. Communication

From ITRS, 2001

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Traditional SoC Nightmare

Variety of dedicated interfaces Poor separation between computation and communication.

Design and Verification Complexity Unpredictable performance

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Solution – Network on Chip (NoC)

• Scalability

• Concurrency, effective spatial reuse of resources

• Higher bandwidth

• Higher levels of abstraction

• Modularity – Productivity Improvement

Easier SoC Integration!

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NoC vs. “Off-Chip” NetworksWhat is Different?

• Routers on Planar Grid Topology

• Short PTP Links between routers

• Unique VLSI Cost Sensitivity: Area-Routers and LinksPower

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NoC vs. “Off-Chip Networks”• No legacy protocols to be compliant with …

• No software simple and hardware efficient protocols

• Different operating env. (no dynamic changes and failures)

• Custom Network Design – You design what you need!

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Replace

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Example1: Replace modules

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NoC vs. “Off-Chip Networks”

M odule

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Example2: Adapt Links

Adapt Links

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Example3: Trim Unnecessary (ports, buffers, routers, links)

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QNoC: QoS NoC

Define Service Levels (SLs):• Signaling

• Real-Time

• Read/Write (RD/WR)

• Block-Transfer

Different QoS for each SL

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QNoC Architecture

• Mesh Topology

• Fixed shortest path routing (X-Y)Simple Router (no tables, simple logic)No deadlock scenarioPower efficient communication

• Wormhole RoutingFor reduced buffering

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QNoC Wormhole Router

R outer

Module

Moduleor

another router Input Port Output Port

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SoC development with QNoC

CharacterizeTraffic

SystemM odules

SystemSim ulations

System Architecture Definition System Integration and Verification

M ap traffic to gridQ NoC

Architecture

O ptim ize

Estim ate cost

Topology andP lacem ent

O ptim izedQ NoC

Hardware

SoCFabrication

Q NoCVerifia tion

M odel

SystemVerification

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Integration Automation Tools

QNoC Placement and Topology Generation• Analyzes System Modules and Traffic

• Derives NoC Topology and Module Placement

• Minimizes Spatial Traffic Density

For Lower Area and Power

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Integration Automation Tools

QNoC Customization• Maze-Router – for efficient packet routing

• Link Load Calculator – for capacity allocation

• QNoC Network Simulator – for QoS assuring

Placed Modules Relative Link Load Simulated QoS

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Integration Automation Tools

Automatic Hardware Generation• Use calculated QNoC parameters and QNoC VHDL

templates library• Create Synthesizable VHDL description of QNoC• Including

• Module wrappers• Synchronization and SER/DES circuitry • Routing logic and tables

System Verification• QNoC verification models• For hardware and system simulations

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Summary

• SoC Integration Challenge

• NoC Concept

• QNoC Architecture

• SoC Integration by QNoC

• Automatic Integration Tools

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More Info:

www.ee.technion.ac.il/qnocwww.ee.technion.ac.il/qnoc