1 coupling aware timing optimization and antenna avoidance in layer assignment di wu, jiang hu and...
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Coupling Aware Timing Optimization and Antenna
Avoidance in Layer Assignment
Di Wu, Jiang Hu and Rabi Mahapatra
Texas A&M University
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Outline
Background and previous works Problem formulation Improved probabilistic coupling
capacitance model Antenna avoidance through tree
partitioning Layer assignment heuristic Experimental results
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Coupling capacitance
Coupling capacitance (crosstalk) induces two different problems: Functional noise:
Delay noise:
Coupling capacitance between segment i and j.
ij
ijij Dist
LenfjiCC ),(
• fij : switching activities between i and j.• Lenij : coupling length.• Distij : coupling distance.• and : technology dependent constants.
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Coupling induced delay
Delay from CC in Elmore delay model
Same amount of coupling leads to different delay depending on coupling location.
Most of previous works on layer/track assignment consider crosstalk only, not its impact on timing. [ThakurISCAS95’] [KayISPD00’]
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CCRCCRd absaji
a
non-critical sink
critical sink
b Extra delay from CC to the critical sink
i
j
2
CC
2
CCs
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Antenna effect
Occurs during manufacturing Conductor layers fabricated from lowest layer
to highest layer. Conductor layers, connected only to the gate
oxide, called antenna. Risk of gate damage is proportional to the
antenna size.
Sink 1Diffusion Sink 2
Antenna violation
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Antenna avoidance methods
Diode insertion Add protection diode to gate in case of antenna
violation. [ChenISQED00’] [HuangTCAD04’]
Jumper insertion Break long antenna by switching wire to the top
layer and switch back immediately. [HoISPD04’] Layer assignment
Reduce antenna length by layer assignment. [ShirotaCICC98’] [ChenISDFT00’]
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Jumper insertion vs. layer assignment
Each jumper costs two vias and a short segment on the top layer.
Diffusion Gate
Diffusion Gate
Diffusion Gate
Jumper insertion
Antenna violation
Layer assignment
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Layer assignment problem formulation
Given Global routing solution. Required Arrival Time (RAT) for each sink. Via constraints on the boundaries of two
adjacent GRCs. (Global Routing Cells) Goal
Maximize the minimum slack among all sinks considering coupling.
Number of antenna violations is minimized. Via constraints are satisfied.
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Probabilistic coupling model
A routing region r with n uniformly spaced tracks and k wire segments.
Cr : probabilistic coupling capacitance for a target wire i in r.
Cr?Cr???
target wire itarget wire i
other wireother wire
Routing region Routing region rr
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Improved probabilistic model
Linear model: a totally random model. Improved model: suitable for a
track/detailed router with coupling avoidance. If k < n/2, enough empty tracks to separate signal
nets.
If k > n/2, adjacent empty tracks are disallowed, otherwise waste of empty tracks.
CCrr=0=0
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Derivation of the probabilistic model
k,n,1: number of permutations target wire has one adjacent wire.
k,n,2: number of permutations target wire has two adjacent wires.
k,n: total number of permutations. Each of k,n,1, k,n,2 and k,n limits to the cases
that no two empty tracks are adjacent to each other.
otherwiseotherwiseifif 2/nk
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Derivation of k,n
Empty tracks can only be inserted into limited “slots” to avoid their adjacency.
After empty tracks are inserted, perform permutation on the wires.
!1k
kn
k
k,nk,n = = 2/nk
a wirea wire
potential slot potential slot for empty tracksfor empty tracks
k,nk,n: total # of permutations : total # of permutations with no adjacent empty with no adjacent empty tracks.tracks.
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Derivation of k,n,1
Target wire is not on boundary
)!1(1
1
1
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k
kn
kk
target wire itarget wire i
other wireother wire
empty trackempty track
bundlebundle
potential position potential position for empty tracksfor empty tracks
k,n,1k,n,1 – not_on_boundary = – not_on_boundary = 2/nk
k,n,1k,n,1: total # of : total # of permutations target wire permutations target wire has one neighboring wire.has one neighboring wire.
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Derivation of k,n,1
Target wire is on boundary
k,n,1 = k,n,1 -not_on_boudary + k,n,1 -on_boudary
)!1(1
2
kkn
k
target wire itarget wire i
other wireother wire
empty trackempty track
bundlebundle
potential position potential position for empty tracksfor empty tracks
k,n,1k,n,1 –on_boundary = –on_boundary = 2/nk
k,n,1k,n,1: total # of permutations : total # of permutations target wire has one target wire has one neighboring wire.neighboring wire.
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Derivation of k,n,2
)!2(1
2
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k
kn
kk
target wire itarget wire i
other wireother wire bundlebundle
potential position potential position for empty tracksfor empty tracks
k,n,2k,n,2 = = 2/nk
k,n,2k,n,2: total # of permutations : total # of permutations target wire has two neighboring target wire has two neighboring wires.wires.
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Comparison of linear model and improved model
Comparison of the improved probabilistic model with a linear model [BecerSLIP02] when k =0 ~ 30 and n=30.
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Antenna avoidance through layer assignment
Separators : segments that surround an antenna. If separators are limited on the top metal layer (Ltop),
antenna problem becomes a tree partitioning problem.
MetaMetal 1l 1MetaMetal 2l 2MetaMetal 3l 3MetaMetal 4l 4
Sink Sink vv
Antenna for Antenna for vv
““don’t care” region don’t care” region for for vv
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Tree partitioning for antenna avoidance (TPAA)
Find the minimum number of separators such that the size of each resulting sub-tree (containing sinks) is less than Amax (Maximum allowed antenna size).
Example:
TTss
WW(TTss): total length of tree TsTs
separatorsseparators
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Linear optimal tree partitioning algorithm
An bottom-up approach, adapted from [KunduSIAM77’], each node in the tree processed at most once.
At each node u, if W(Tu) > Amax, remove minimum number of separators in Tu (assign to Ltop), such that the resulting W(Tu) Amax.
A O(n) SPLIT technique to find minimum separators.
1 11 1
1 1
AAmaxmax=5=5
WW(TTuu): total length of tree TTuu
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Constrained tree partitioning
Each metal layer has a preferred routing direction (horizontal or vertical) not every segment can be assigned to Ltop. Feasible branch: root edge of a branch can be assigned
to Ltop. Define BMF(u) : maximal feasible branches for Tu. Apply tree partitioning on BMF(u) with Amax,reduced.
Amax,reduced=Amax- ∑ Weight( infeasible edge separating BMF(u))
u
a
bdc
e
2
1
AAmaxmax=30 =30 AAmax,reducedmax,reduced=27=27
infeasible edge
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Tree partitioning based optimal jumper insertion
Similar techniques can be applied to jumper insertions.
Time complexity is O(n) and can be applied to the work of [HoISPD04].
1 11 1
1 1
AAmaxmax=5=5
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Layer assignment heuristic
Consider both coupling induced delay and antenna effects.
Proceeds in a panel by panel order. Within a panel, most congested region is
processed first.Global cell processing order
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Layer assignment heuristic
Within each global cell - an MILP problem, we provide a simple heuristic:
1. Assign antenna-critical segments to Ltop.2. Sort non-critical segments in non-increasing
order of min timing slacks.3. Partition the non-critical segments to layers
min slack is maximized. Coupling estimated with the probabilistic model.
4. Enforce via constraints. 5. Update slacks for each segment (net) in this cell.
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Layer assignment example
Layer assignment example on one global cell.
Layer 0Layer 0
Layer 1Layer 1
Layer 2Layer 2
Layer 3Layer 3
300ps250ps100ps 20ps100ps
240ps230ps50ps 20ps100ps
antenna criticalTiming slacks before LA
Timing slacks after LA
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Benchmark circuits ISPD98/IBM circuits [AlpertISPD98].
Circuit #GRC #nets #tracks verti panel
#tracks hori panel
ibm01 64×64 8.8K 10 10
ibm02 80×64 15.7K 22 18
ibm03 80×64 14.6K 15 14
ibm04 96×64 17.9K 19 17
ibm05 128×64 19.3K 34 32
ibm06 128×64 21.9K 18 15
ibm07 192×64 29.0K 23 21
ibm08 192×64 36.3K 22 18
ibm09 256×64 41.6K 18 14
ibm10 256×128 43.7K 23 20
ibm11 256×128 50.0K 13 12
ibm12 256×128 51.6K 18 15
ibm13 256×128 59.4K 13 12
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Benchmark circuit Placement by Dragon [WangICCAD00]. Global routing by a rip-up and re-route router. Our method is compared with three other
methods: Method 1: consider only total coupling
capacitance. Method 2: coupling capacitance estimated by a
trial track/layer assignment method. Method 3: coupling capacitance is estimated using
the linear model. Results are validated by a timing-driven track
router.
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Experimental results - timing
-1200
-1000
-800
-600
-400
-200
0
ps
ibm01 ibm02 ibm03 ibm04 ibm05 ibm06 ibm07 ibm08 ibm09 ibm10 ibm11 ibm12 ibm13Average
Circuits
Timing Results
Method 1
Method 2
Method 3
Our Method
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Experimental results – Antenna violations
LA: Layer Assignment without Antenna Avoidance. LAAA: Layer Assignment with Antenna Avoidance.
0
2000
4000
6000
8000
10000
12000
ibm01 ibm03 ibm05 ibm07 ibm09 ibm11 ibm13
Circuits
# Antenna Violations
LA
LAAA
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Experimental results – via violations
JI : Jumper Insertion.
0
5000
10000
15000
20000
25000
ibm01 ibm03 ibm05 ibm07 ibm09 ibm11 ibm13
Circuits
# Via Violations
LA+JI
LAAA+JI
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Experimental result - CPU
0
100
200
300
400
500
600
sec
ibm01 ibm02 ibm03 ibm04 ibm05 ibm06 ibm07 ibm08 ibm09 ibm10 ibm11 ibm12 ibm13 Average
Circuits
CPU
CPU time is similar for all methods
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Conclusion
An improved probabilistic crosstalk model is proposed to fit for a coupling-aware timing-driven track/detailed router.
Antenna avoidance through tree partitioning.
Experimental results showed : significant via reductions compare to jumper
insertions. timing improvement using the improved
probabilistic model. Thank you!
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))()(()(maxmax,
uBbureduced
MFbWTWAA
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SPLIT example A sub-tree Tu has 5 branches and Amax=24.
W(Tu)=28. median-find-and-half : Find median, then halve. SPLIT({6,2,9,7,4},24) = SPLIT ({9,7},12)={9}
2 2 2 3 3
2 2 2 5 2 2 1
Tu