Mahapatra Vitae

August 30, 2010

Curriculum Vitae

Rabi N Mahapatra

Professor

Department of Computer Science & Engineering Texas A&M University

College Station, TX 77843 Voice: 979-845-5787,

E-mail: rabi AT cse.tamu.edu URL: http://faculty.cse.tamu.edu/rabi/

Professional Experience | Educational Background | Research Interests | Publications | Grants & Contracts | Student Supervision | Teaching | Professional Activities | Honors | Intl. Outreach |

Professional Experiences

Professor, September 2010 Department of Computer Science and Engineering, Texas A&M University Associate Professor, September 2001 – August 2010 Department of Computer Science and Engineering, Texas A&M University

Academic Visitor, June 2001 – August 2001 IBM T J Watson Research Labs, ARL, Austin, worked on power modeling of IBM 405 embedded processor.

Associate Research Professor, November 2000 – May 2001 Department of Computer Science and Engineering, Texas A&M University

Visiting Assistant professor/Senior-Lecturer, August 1995 – November 2000 Department of Computer Science and Engineering, Texas A&M University

Assistant Professor, August 1992 – July 1995 Department of ECE, Indian Institute of Technology, Kharagpur

Lecturer, August 1984 – July 1992 Department of ECE; Indian Institute of Technology, Kharagpur

BOYS-CAST Fellow, August 1987 – July 1988

Center of Advanced Computer Studies, University of South Western Louisiana

Educational Background Top

Ph.D, Computer Engineering, Thesis: “Performance Analysis of Multiprocessor Based Architectures for some Orthogonal Transforms”, Indian Institute of Technology, Kharagpur, India, 1991

M.S. Engg., Electrical Engineering, Sambalpur University, India, 1984

B.S. Engg. (Hons), Electronics and Telecommunication, Sambalpur University, India, 1979

Research Interests Top

Low-power Embedded System Design, Network on Chip, SoC Reliability, Low-power IP Lookup

Mahapatra Vitae

August 30, 2010

Architectures, Configurable Low-power Architectures, Intention-based searching,

Publications Top

A. Referred Journal Publications

Manuscripts Published and Accepted for Publication

1. Amar Rasheed* and Rabi Mahapatra, "The Three-Tier Security Scheme in Wireless Sensor Networks with Mobile Sinks," To appear in the IEEE Transactions on Parallel and Distributed Systems (TPDS).

2. Heeyeol Yu* and Rabi Mahapatra, “A Power- and Throughput-Efficient Packet Classifier with Bloom Filters; to appear in IEEE Transactions on Computers.

3. S. Mandal*, P. Bhojwani*, S. Mohanty, and R. Mahapatra, ”IntelliBatt: Intelligent Battery System for Embedded Systems”, IEEE Computer Magazine, April 2010.

4. Yoonjin Kim, Rabi N. Mahapatra, and Kiyoung Choi, "Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture," accepted as a regular paper for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

5. Amar Rasheed* and Rabi Mahapatra, "Key Pre-distribution Schemes for Establishing Pairwise Keys with a Mobile Sink in Sensor Networks," To appear in the IEEE Transactions on Parallel and Distributed Systems (TPDS).

6. S. Mandal* and R. Mahapatra, “PowerAntz: Ant behavior inspired power budget distribution scheme for Network on Chip systems,” to appear in Elsiever Micro Electronics Journal,

7. Y. Kim* and R. Mahapatra, "Dynamic Context Compression for Low Power Coarse-Grained Reconfigurable Architecture," Accepted for publication in IEEE Transaction on VLSI Systems.

8. Y. Kim*, R. Mahapatra, I. Park, and K. Choi, “Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture,” to appear in, IEEE Transactions on VLSI Systems, vol. 17, no. 5, pp.593-603, May 2009.

9. D. Dechev, R. Mahapatra and B. Stroustrup, "Practical and Verifiable C++ Dynamic cast in Autonomous Space Systems", Special Issue on Real-time Distributed Computing and Ubiquitous computing in Memory - Intl. Journal of Computing Science and Engineering (JCSE), December 2008.

10. Singhal, R*, Gwan Choi; Mahapatra, R.N.; “Data Handling Limits of On-Chip Interconnects”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 6, June 2008 Page(s):707 - 713

11. Bhojwani, P.S*.; Mahapatra, R.N.; “Robust Concurrent Online Testing of Network-on-Chip-Based SoCs “,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 9, Sept. 2008 Page(s):1199 - 1209

12. Subrata Acharya*, Rabi N. Mahapatra: A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems. IEEE Trans. Computers 57(2): 215-230 (2008)

13. John Mark Nolen*, Rabi N. Mahapatra: Time-Division-Multiplexed Test Delivery for NoC Systems. IEEE Design & Test of Computers 25(1): 44-51 (2008)

Mahapatra Vitae

August 30, 2010

14. S. P Mohanty, E. Kougianos and R. Mahapatra, "Hardware Assisted Watermarking for

Multimedia," Special Issue on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia, Intl Journal on Computers and Electrical Engineering (Elsevier Ltd.), Vol. 35, No. 2, March 2009.

15. Seraj Ahmad, Rabi N. Mahapatra: An Efficient Approach to On-Chip Logic Minimization. IEEE Trans. VLSI Syst. 15(9): 1040-1050 (2007)

16. D. Wu*, J. Hu and R. Mahapatra, “Antenna Avoidance in Layer Assignment”, IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006).

17. A. Rajaram*, J. Hu, R. Mahapatra, "Reducing Clock Skew Variability via Cross Links", IEEE Transactions on CAD, 25(6), 1176-1182 (2006)

18. A. Rajaram*, J. Hu, W. Guo, R. Mahapatra and B. Lu, “Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation,” IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006).

19. Vijay Kappagantula*, Subrata Acharya* and Rabi N Mahapatra, "A partitioning Algorithm for Power Constrained Reconfigurable Real-Time System", Microprocessors and Microsystems Journal. (Accepted).

20. R. Mahapatra and W. Zhao., "An Energy efficient Slack Distribution Technique for Multimode Distributed Real-time embedded Systems", IEEE Transactions on Parallel and Distributed Systems Volume 16, Issue 7, July 2005 pp.650 - 662.

21. V. C. Ravikumar*, R. Mahapatra and L. N Bhuyan, “EaseCAM: An Energy and Storage Efficient TCAM-based Router Architecture”, IEEE Transactions on Computers, Vol.54, No.5, May 2005 pp.521-533.

22. A. Kumar and R. Mahapatra "An Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Finite Buffer Space", Computers and Communication Journal, Elsevier Publications, Volume 29, Issue 1, 2005, pp. 42-51.

23. Ravikumar V C*, and Rabi N Mahapatra, “Ternary-CAM Architecture for IP Lookup Using Prefix Properties”, IEEE Micro, April/May 2004, pp.60-69.

24. S. Mahapatra* and Rabi Mahapatra, “Mapping of Neural Net Models onto Systolic Arrays”, Journal of Parallel and Distributed Computing”, Vol. 60, 2000, pp. 677-689.

25. S. Mahapatra*, R. N. Mahapatra and B. N. Chatterji, “Mapping of Neural Net Models onto Massively Parallel Hierarchical Computer Systems”, Journal of System Architecture”, Vol. 45, No. 11, May 1999, pp. 919-929.

26. Ashis Pani*, G. P. Bhattacharjee and R. N. Mahapatra "Event Scheduling using Allen Algebra", Intl. Journal of Computer Mathematics (ICJM), Vol. 70, pp. 87-97, 1998.

27. R. N. Mahapatra, A. Kumar* and B. N. Chatterji, "Performance Analysis of 2-D Inverse Fast Cosine Transform Employing Multiprocessors", IEEE Transaction on Signal Processing, Vol.45, No.5, May'97, pp.1323 - 1335.

28. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Modeling Hadamard Haar Transform Algorithm for Omega Connected Multiprocessor", Signal Processing, Elsevier Publishers, Vol.58, No. 3, May 1997, pp.293 - 301.

29. S. Mahapatra*, R. N. Mahapatra and B. N. Chatterji, "A Parallel formulation of Back Propagation learning on Distributed Memory Multiprocessors", Parallel Computing, Vol., No.12, Feb. 1997, pp.1661-1675.

Mahapatra Vitae

August 30, 2010

30. R. N. Mahapatra and S. Mahapatra*, "Mapping Neural Network Models onto Two-

Dimensional Processor Arrays", Parallel Computing Journal, Vol. 22, No. 10, Jan. 1997, pp. 1345-1357.

31. C. R. Tripathy*, R. N. Mahapatra and R. B. Misra, "Reliability Analysis of Hypercube Multicomputers", Microelectronics and Reliability, Vol. 37 (6), 1997, pp. 885-891.

32. C. R. Tripathy*, S. Patra*, R. B. Misra and R. N. Mahapatra, Reliability Evaluation of Multistage Interconnection Networks with Multistate Elements", Microelectronics and Reliability, Vol. 36, No.3, 1996, pp.423-428.

33. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Performance Modeling of Discrete Cosine Transform for Star-Graph Connected Multiprocessors", Intl. Journal of Circuits Systems and Computers, Vol. 6, No.6, 1996, pp. 635-648

34. C.R. Tripathy*, R. N. Mahapatra and R. B. Misra, "Fuzzy Reliability Evaluation of Multistage Interconnection Network", Computer science and Information, Vol. 25, No. 4, Dec. 1995, pp.17-29.

35. R. N. Mahapatra and Sudipta Mahapatra*, "Modeling 2-D IFCT Algorithm on a Multistage Interconnection Network", Signal Processing, Vol. 30, No.2, 1993, pp. 235-243.

36. R. N. Mahapatra and H. Pareek*, "Modeling a Fast Parallel Thinning Algorithm for Shared Memory SIMD Computers", Information Processing Letters, Vol. 40, No. 5, Dec. 1991, pp.257-261.

37. A. Dutta*, S.V. Joshi* and R. N. Mahapatra, "Modeling Morphological Thinning Algorithm for Shared Memory SIMD Computers", Parallel Processing Letters, Vol. 1, No.1, 1991, pp.59-65.

38. R. N. Mahapatra, "Microprocessor Implementation of Fast Convolver", IETE Technical Review, Vol.5, No.5, Aug. 1988, pp.326-328.

Journal Manuscripts currently under review

39. Yoonjin Kim*, Rabi N. Mahapatra, and Kiyoung Choi, “An Approach to the Design of Cost-Effective Coarse-Grained Reconfigurable Architecture”, IEEE Transactions on VLSI Design Systems.

40. Heeyeol Yu* and Rabi Mahapatra, “An Indexing Hash Table using Multi-Predicate Bloom Filters in Packet Classification”, under review with IEEE Transactions in Networking.

41. Heeyeol Yu* and Rabi Mahapatra, “Throughput- and Power-Efficient Hybrid CAMs for Parallel IP lookups”, under review with The International Journal of Computer and Telecommunications Networking.

42. N. Gupta*, S. Mandal* and R. Mahapatra, “Reliability aware Dynamic Power Management in Multiprocessor Real Time Systems”, submitted to ACM Transactions on Embedded Computing (TECS), Special Issue on Embedded Systems for Real-time Multimedia.

43. Yoonjin Kim*, E J Kim and Rabi Mahapatra, “Hierarchical Multiplexing Interconnection Structure for Cost-Effective Stage-Level Reconfigurable Chip Multiprocessor”, submitted to special issue of EUROSIP Journal on Embedded systems on Reconfigurable Computing.

44. Amar Rasheed* and Rabi Mahapatra, “Mobile sink with multiple channels to defend against wormhole attacks in wireless sensor networks”, submitted to Intl. Journal on Computer

Mahapatra Vitae

August 30, 2010

Communication (Elsevier Publication).

Journal Manuscripts under preparation

45. Amar Rasheed* and R. Mahapatra, “Energy Efficient Cross-layer Transmission Protocol for Wireless Sensor Networks,” to be submitted to IEEE Trans. on Mobile Computing.

46. R. Sridharan* and R. Mahapatra, “Analysis of Real-time Embedded Applications in the Presence of Stochastic Fault Model”, to be submitted to IEEE Transaction on Computers.

47. J. D. Lee* and R. Mahapatra, “Testing Many-Core Systems-on-Chip with Distributed Test Vector Storage", to be submitted to IEEE Design &Test.

48. A. Biswas*, J. Panigrahy*, S. Mohan*, A. Tripathy* and R. Mahapatra, “Meaning Representation and Comparison for Intention based Search”, IEEE Transactions on Knowledge and Data Engineering.

49. Yoonjin Kim* and Rabi N. Mahapatra, "Dynamic Context Management Strategy for Low Power Coarse-Grained Reconfigurable Architecture," to be submitted to ACM Transactions on Embedded Computing Systems"

B. Referred Books, Book Chapters and Edited Books

50. Y. Kim and R. Mahapatra, “Design of Low-Power Coarse-Grained Reconfigurable

Architectures,” CRC Press, 2010.

51. R. Singhal*, G. Choi, and R. Mahapatra, “Data Integrity for On-Chip Interconnects”, VDM

Verlag Publisher, Accepted for publication.

52. Biswas, A, Mohan, S, and Mahapatra, Rabi, "Intelligent Technologies for Distributed Search

P2P Networks", to appear in Handbook of Research on P2P and Grid Systems for Service-

Oriented Computing: Models, Methodologies and Applications, IGI Publisher 2009, Editors:

Antonopoulos, Exarchakos, Li and Liotta.

53. Biswas, A, Mohan, S, and Mahapatra, Rabi, "Semantic Technologies for Searching in e-

Science Grids", to appear in Semantic e-Science, Springer AoIS Book Series 2009. Editors:

Chen, Wang and Cheung.

54. M. Nolan* and R. Mahapatra, “A TDM Test Scheduling Method for Network on Chip,” Microprocessor Test and Verification, IEEE Computer Society Press, 2006.

55. Rabi N. Mahapatra, Guest Editor, Special Issue on Embedded System Codesign, Intl. Journal on Microelectronics Journal (MEJ), November 2003, Elsevier Publication.

56. Rabi N. Mahapatra, Editor, "Trends in Information Technology", McGraw Hill Publications, 1998.

57. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Modeling of Wavelet Transform on Multiprocessor Systems", IT: Challenges and Opportunities, Tata McGraw Hill Publication, Nov.1995, pp. 335--346.

58. B. K. Das*, R. N. Mahapatra, "An Efficient Circle Detection Scheme using a Two Dimensional Array of Accumulators", Pattern Recognition, Image Processing and Computer Vision: Recent Advances, Narosa Publishing House, New Delhi, 1995, pp. 230-237.

59. V. A. Kumar*, B. K. Das* and R. N. Mahapatra, "Performance Analysis of Hough Transform on Parallel Architectures", Frontiers in Parallel Computing, Narosa Publishers, 1990, pp. 279-288.

Mahapatra Vitae

August 30, 2010

C. Referred Highly Selective Conference Proceedings

1. R. Sridharan and R. Mahapatra, "Reliability Aware Power Management for Dual-Processor Real-Time Embedded Systems," to appear in the Proceedings of IEEE/ACM Design Automation Conference (DAC), 2010.

2. S. K. Mandal, R. Denton, S. P. Mohanty and R. Mahapatra, "Low Power Nanoscale Buffer Management for Network on Chip Routers", To appear in Proceedings of GLSVLSI 2010.

3. Mohan, S., Biswas, A., Panigrahy, J, Tripathy, A & Mahapatra, R.,"A Parallel Architecture for Meaning Comparison", to appear in the Proceedings of IPDPS 2010.

4. N. Gupta, S. K. Mandal, A. Mandal, J. Malave & R. N. Mahapatra, "A Hardware Scheduler for Real Time Multiprocessor System on Chip", 23rd International Conference on VLSI Design, 2010, pp.264-269.

5. John Yu, Rabi Mahapatra and Laxmi Bhuyan,'A Hash-based Scalable IP lookup using Bloom and Fingerprint Filters', to appear in the Proceedings of ICNP 2009.

6. A. Biswas, S. Mohan and R. Mahapatra, "Search Co-ordination using Semantic Routed Network", to appear in Proceedings of the 18th International Conference on Computer Communications and Networks, ICCCN 2009.

7. Jason D Lee, Praveen Bhojwani and Rabi Mahapatra, "A Distributed Concurrent On-Line Test Scheduling Protocol for Many-Core NoC-Based Systems," to appear in the Proccedings of IEEE International Conference on Computer Design (ICCD), 2009.

8. A. Biswas, S*. Mohan, A. Tripathy, J. Panigrahy, and R. Mahapatra,"Semantic Key for Meaning Based Searching" in 2009 IEEE International Conference on Semantic Computing (ICSC 2009),14-16 September 2009, Berkeley, CA, USA.

9. Yoonjin Kim* and Rabi N. Mahapatra, "Hierarchical Reconfigurable Computing Arrays For Efficient CGRA-based Embedded Systems," to appear in the 46th IEEE/ACM Design Automation Conference, San Francisco, California, July 2009 (Acceptance rate 22%).

10. Amar Rasheed* and Rabi Mahapatra, "A Key Pre-distribution Scheme for Heterogeneous Sensor Networks," The 5th ACM International Wireless Communications and Mobile Computing Conference, IWCMC 2009 Wireless Sensor Networks Symposium, pp. 263-268, June 21-24, 2009, Leipzig, Germany.

11. Yoonjin Kim* and Rabi N. Mahapatra, “Dynamic Context Management for Low Power Coarse-Grained Reconfigurable Architecture”, to appear in the Proceedings of the 19th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI 2009). Boston, Massachusetts. May 2009. (Acceptance 16%)

12. A. Biswas*, S. Mohan*, S. Panigrahy*, A. Tripathy*, & R. Mahapatra, “Representation and Comparison of Complex Concepts for Semantic Routed Network”, Proceedings of 10th International Conference on Distributed Computing and Networking (ICDCN), pp.127-138, 2009. (Acceptance 13%)

13. Heeyeol Yu* and Mahapatra, "A Memory-Efficient Hashing by Multi-Predicate Bloom Filters for Packet Classification, “Proceedings of IEEE 27th INFOCOM Conference on Computer Communications. vol., no., pp.1795-1803, 13-18 April 2008. (Acceptance 236/1160, 20%)

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August 30, 2010

14. Y. Kim* and R. N. Mahapatra, "A New Array Fabric for Coarse-Grained Reconfigurable

Architecture", Proceedings of 11th EUROMICRO Conference, dsd.pp.584-591, 2008. (Acceptance 27%)

15. Heeyeol Yu*, R. Mahapatra, "A space- and time-efficient hash table hierarchically indexed by Bloom filters", Proceedings of IEEE International Symposium on Parallel and Distributed Processing, (IPDPS 2008), pp.1-12. (Acceptance 105/410, 25%)

16. S. Mandal*, P. Bhojwani*, S. Mohanty, and R. Mahapatra, "IntellBatt: Towards smarter battery design, "Proceedings of 45th ACM/IEE Design Automation Conference, (DAC 2008), pp.872-877, 8-13. (Acceptance 147/639, 23%)

17. R. Sridharan*, N. Gupta*, and R. Mahapatra, "Feedback-controlled reliability-aware power management for real-time embedded systems," Proceedings of 45th ACM/IEE Design Automation Conference, (DAC 2008), pp.185-190. (Acceptance 147/639, 23%)

18. J. D. Lee*, N. Gupta*, P. Bhojwani*, R. Mahapatra, "An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems, "Proceedings of 9th International Symposium on Quality Electronic Design, (ISQED 2008), pp.184-189. (Acceptance 90/300, 30%)

19. A. Biswas*, S. Mohan* and R. Mahapatra, "Optimization of Semantic Routing Table", Proceedings of 17th International Conference on Computer Communications and Networks, 2008, pp.1-6. (Acceptance 104/399, 26%)

20. Amar Rasheed* and Rabi Mahapatra, "An Efficient Key Distribution Scheme for Establishing Pair wise Keys with a Mobile Sink in Distributed Sensor Networks", Proceedings of the 27th IEEE International Performance Computing and Communications Conference ( IPCCC 2008 ), pp.264-270. (Acceptance 42/141, 29%)

21. Heeyeol Yu*, Rabi Mahapatra, "A Throughput-Efficient Packet Classifier with n Bloom filters", Proceedings of GLOBECOM NGNPS 2008, pp.1-5. (Acceptance 30%)

22. R. Samanta*, J. Surprise* and R. Mahapatra, "Dynamic Aggregation of Virtual Addresses in TLB using TCAM Cells," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, January 2008, pp.243-248. (Acceptance 31%)

23. S. Mandal*, R. Mahapatra, "PowerAntz: Distributed Power Sharing Strategy for Network on Chip, IEEE Proceedings of IEEE International Symposium on Low Power Electronic Design (ISLPED 2008), pp.177-182. (Acceptance 31%)

24. J. D. Lee, R. Mahapatra, "In-Field NoC-Based SoC Testing with Distributed Test Vector Storage" Proceedings of IEEE ICCD 2008, pp.206-211. (Acceptance 34%)

25. D. Dechev, R. Mahapatra, B. Stroustrup, D. Wagner, "C++ Dynamic Cast in Autonomous Space Systems", Proceedings of 11th IEEE International Symposium on Object Oriented Real-Time Distributed Computing , pp.499-507, (ISORC 2008). (Acceptance 35%)

26. Yoonjin Kim* and R. Mahapatra, "Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array," IEEE International Conference on Computer Design, October 2007, (Acceptance rate 21%).

27. P. Bhojwani* and R. Mahapatra, "A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip", Proceedings of ACM/IEEE Design Automation Conference (DAC), 2007, pp. 670-675 . (Acceptance rate 25%, ~800 submissions)

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August 30, 2010

28. P. Bhojwani* and R. Mahapatra, "An Infrastructure-IP for online testing of network-on-chip

based SoCs", Proceedings of IEEE Intl. Symposium for Quality Electronic Devices (ISQED), 2007, pp. 867-872 . (Acceptance rate ~30%, 300+ submissions).

29. R. Sridharan* and R. Mahapatra, "Analysis of Real-time Embedded Applications in the Presence of Stochastic Fault Model," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007, pp.83-88. (Acceptance rate 31%).

30. R. Samanta* and R. Mahapatra, "An Enhanced CAM Architecture to Accelerate LZW Compression," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007, pp.824-829. (Acceptance rate 31%).

31. P. Bhojwani*, J. D. Lee* and Rabi Mahapatra, "SAPP: Scalable and Adaptable Peak Power Management in NoCs", to appear in Proceedings of Intl. Symposium on Low Power Electronic Devices (ISLPED), August 2007. (31%)

32. R. Singhal*, G. Choi, and R. Mahapatra, "Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects," Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2006. (20%, 530+ submissions)

33. R. Singhal*, G. Choi and R. Mahapatra, "Programmable LDPC Decoder Based on the Bubble-Sort Algorithm," Proceedings of ACM/IEEE International Conference on VLSI Design 2006, pp.203-208. (27%, 328 submissions)

34. S. Ahmad* and R. Mahapatra, “TCAM Enabled On-Chip Logic Minimization”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2005). (Acceptance rate 20%).

35. Vivek Rai* and Rabi Mahapatra, "Lifetime Modeling of a Sensor Network", Proceedings of the IEEE Intl. Conf. on Design, Automation and Test in Europe (DATE) 2005. (Acceptance rate: 25% out of 820 submissions)

36. D. Wu, G. Venkataraman, J. Hu, Q. Li, and R. Mahapatra, "DiCER: Distributed and Cost-Effective Redundancy for Variation Tolerance," Accepted for Publication in Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2005. (Acceptance rate 25%)

37. P. S Bhojwani*, R. Mahapatra, E. J. Kim and T. Chen; "A Heuristic for Peak Power Constrained Design of Network on Chip (NoC) based Multimode Systems", IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2005, pp.124-129. (Acceptance rate 27.5% out of 352 submissions).

38. R. Singhal, G. Choi and R. Mahapatra, "Programmable LDPC Decoder Based on the Bubble-Sort Algorithm," Accepted for Publication in Proceedings of ACM/IEEE International Conference on VLSI Design 2006.

39. S. Ahmad*, N. Jayakumar*, S. Khaitri and R. Mahapatra, “X-Routing using Two Manhattan Routing Instances,” Accepted for Publication in Proceedings of IEEE International Conference on Computer Design (ICCD) 2005.

40. D. Wu*, J. Hu and R. Mahapatra, “Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment”, Proceedings of ACM Intl. Symposium on Physical Design (ISPD), 2005. (Acceptance rate: 32%).

41. Seraj Ahmad* and Rabi N Mahapatra, "m-Trie: An Efficient Approach to On-chip Logic Minimization", Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2004. (Acceptance rate: 24% out of 520 submissions)

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August 30, 2010

42. Siddharth Choudhury* and Rabi N Mahapatra, “Energy Characterization of File Systems for

Diskless Embedded Systems”, Proceedings of ACM /IEEE Intl. Design Automation Conference (DAC) 2004, pp. 566-569. (Acceptance rate: 20% out of 785 submissions)

43. Anand Rajaram*, Jiang Hu and Rabi N Mahapatra, “Reduced Clock Skew Variability via Cross Links”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2004) pp. 18-23. (Acceptance rate: 20% out of 785 submissions), (Nominated for best paper award)

44. Praveen S Bhojwani*, Rabi N. Mahapatra, E. J. Kim and Thomas Chen; "A Heuristic for Peak Power Constrained Design of Network on Chip (NoC) based Multimode Systems", to appear in IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2005. (Acceptance rate 27.5%, 97 papers accepted out of 352 submissions)

45. Anand Rajaram*, Wei Guo, Bing Lu, Rabi Mahapatra and Jiang Hu, "Analytical Bound for Unwanted Clock Skew due to Wire Width Variation”, Proceedings of IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2003, pp. 401-407. (Acceptance rate: 25%)

46. V C Ravikumar*, Rabi Mahapatra, and J.C Liu, “Modified LC-Trie based Efficient Routing Look Up”, IEEE/ACM Proceedings on MASCOTS, October 2002, pp. 177-182. (Acceptance rate: 30% of 180 submissions)

47. Abhijit Prasad*, Wangqi Qui* and Rabi Mahapatra, “Hardware Software Partitioning of Multifunction Systems”, Proceedings of Intl. Conf. on Information Technology, Dec 2002. (Acceptance rate: 25% out of 280 papers)

D. Referred Publications in Selective Conferences with High Visibility

48. Amar Rasheed and Rabi Mahapatra, "Mobile Sink Using Multiple Channels to Defend Against Wormhole Attacks in Wireless Sensor Networks," The 28th IEEE International Performance Computing and Communications Conference, IPCCC '09. 14-16 Dec 2009, Page(s): 216-222.

38. Amar Rasheed and Rabi mahapatra, "Secure Data Collection Scheme in Wireless Sensor Network with Mobile Sink", Proceedings of 7th IEEE Intl. Symposium on Network Computing and Applications 2008, pp.332-340. (Acceptance 36%)

39. R. Singhal, S. Chang, G. Choi, and R. Mahapatra, "Error Control Coding for Combinatorial Circuits based on Output Delay Correlation", Accepted for Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2007.

40. A. Rasheed and R. Mahapatra, "An Energy-Efficient Hybrid Data Collection Scheme in Wireless Sensor Networks," Proceedings of IEEE Intl. Conference on Intelligence Sensors, Sensor Networks and Information Processing (ISSNIP), Dec 2007, Accepted for Publication.

41. J. D. Lee, P. Bhojwani and R. Mahapatra, "A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications," Proceedings of 10th IEEE High Assurance System Engineering Symposium (HASE 2007), Nov 2007, pp. 407-408.

42. P. Bhojwani* and R. Mahapatra, "Core Network Interface Architecture and Latency Constrained On-Chip Communication", IEEE Symposium on Quality Electronic Design, 2006 (ISQED), pp.358-363 . (40%, 300+ submissions)

43. R. Singhal*, G. Choi and R. Mahapatra," Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk", Proceedings of IEEE Symposium on Quality Electronic Design", 2006 (ISQED), pp.407-412. (Acceptance rate 40%)

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August 30, 2010

44. A. Kumar* and R. Mahapatra, "Integrated Scheduling and Buffer Management Scheme for

Input Queued Switches with Extreme Traffic Conditions", Proceedings of IEEE International Conference on Computer Communication (ICC) 2005. (Acceptance rate 34% out of 2000+ submissions).

45. D. Wu*, J. Hu, M. Zhao and R. Mahapatra, "Timing Driven Track Routing Considering coupling Capacitance", Proceedings of IEEE Intl. Conference on ASP-DAC 2005 (Acceptance rate 40%).

46. R. Singhal*, G. Choi and R. Mahapatra, “Quantized LDPC Decoder Design for Binary Symmetric Channels”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005.

47. K. Padhi and R. Mahapatra, "A Technique for Identification of Voice in Stereo Soundtracks, "Accepted for Publication in Proceedings of IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005).

48. Di Wu*, Jiang Hu, Rabi Mahapatra and Min Zhao, “Layer assignment for Crosstalk Risk Minimization”, Proceedings of IEEE Intl. Conference, ASP-DAC 2004, pp. 159-162. (Acceptance rate 50%)

49. Praveen Bhojwani* and Rabi Mahapatra, “Interfacing Cores with On-chip Packet-Switched Networks”, IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2003. (Acceptance rate 39%)

50. M. Satpathy, R. N. Mahapatra, S Choudhuri* and S. V. Chintis, “Optimizing power consumption through lazy activation record”, HPCA Workshop on ITERACT-7, Anaheim, CA, Feb 9, 2003., IEEE Computer Society Press , pp. 37-50. (Acceptance rate 50%)

51. Marius Pirvu, Laxmi Bhuyan and Rabi Mahapatra, “Hierarchical Simulation of a Multiprocessor Architecture", Proceedings, Intl. Conference on Computer Design (ICCD), October 2000.

52. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Modeling of Wavelet Transform for De Bruijn Graph Connected Multiprocessors", Proceeding Intl. Conf. on PDPTA'97, pp. 1482- 1489, 1997

53. C. R. Tripathy*, R. B. Misra and R. N. Mahapatra, "Evaluation of Fuzzy Reliability of Multistage Interconnection Networks", Proc. Intl. Conf. on Automation,India,pp.587-591,1995

54. S. Mahapatra* and R. N. Mahapatra, "Mapping of Back propagation Learning onto Distributed Memory Multiprocessors, Intl. Conf. on Algorithms & Architectures for Parallel Processing, Brisbane, April 1995.

55. R. N. Mahapatra and J. Majumdar*, "Implementation of Fast Hartley Transform on Multiple Bus Cache Coherent Multiprocessors", Intl. Conf. on Parallel Distributed Systems (ICPADS), Taiwan, Dec. 1994.

56. C. R. Tripathy*, S. Patra*, R. N. Mahapatra and R. B. Misra, "Reliability Modeling and Analysis of Multiprocessor Systems", Intl. Conf. on Stochastic, Optimization and Computer Applications, Coimbatore, pp. 77-91, Dec. 1994.

57. R. N. Mahapatra, A. Kumar* and B. N. Chatterji, "Vector Hartley Transform Employing Multiprocessors", Intl. Symposium on Parallel processing (IPPS), pp.250-253, April, 1992.

Mahapatra Vitae

August 30, 2010

58. R. N. Mahapatra, V. Ashok Kumar*, B. K. Das* and B. N. Chatterji, "Performance Analysis

of Parallel FFT Algorithm on Multiprocessors", Intl. Conference on Parallel Processing (ICPP), vol.III, pp.368-369, August, 1990.

59. R. N. Mahapatra and B. K. Kar*, "A Multilayered VLSI Array for Multistage Interconnection Network", Fourth Intl. Symposium on VLSI Design, Jan. 1991.

60. R. N. Mahapatra, V. A. Kumar*, and B.N. Chatterji, "Performance Analysis of Fast Hartley Transform Algorithm on Multiprocessor Systems", Intl. Symposium on Computer Architecture and Digital signal Processing, Hong Kong, Oct. 1989.

61. K. V. S. Rao, N. Adiseshu, R. N. Mahapatra and B. K. Sarap, "Design and Development of 32-element Microstrip Dipole Conformal Array", Intl. Symposium on Electronics, Devices and Circuits, Kharagpur, Dec. 1987.

E. Referred Publications in Workshops and as Posters

62. A. Mandal, S. Mandal, A. Trpathy, and R. Mahapatra, "A Bio-inspired Framework for Secure System on Chip," to appear in Proceedings of Workshop on SoC Architecture, Acclerator and Workload, Jan 2010.

63. S. K. Mandal, N. Gupta, A. Mandal, J. Malave, J. D. Lee and R. Mahapatra, "NoCBench: A Benchmarking Platform for Network on Chip", In Proceedings of Workshop on Unique Chips and Systems, UCAS 2009.

64. David Beals, Jason Lee, Rabi Mahapatra and Nikhil Gupta, "Verification of COTS System on Chip for Safety Critical Applications," to appear in the Proceedings of 10th Workshop on Microprocessor Test and Verification, Austin, December 2009.

65. H. Yu* and R. Mahapatra, “A Power- and Memory-Efficient Hashing for Packet Processing”, to appear as poster paper in IPDPS 2009.

66. Y. Kim* and R. Mahapatra, "Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture", Proceedings of 15th Reconfigurable Architecture Workshop, IPDPS 2008, pp.1-8.

67. J. D. Lee* and R. Mahapatra, "Distributed Test Vector Storage for Safety-Critical NoC-based Systems", to appear in Proceedings of IEEE Workshop on UCAS-4, 2008.

68. H. Yu*, R. N. Mahapatra, U. Lee; "Power-saving Hybrid CAMs for Parallel Lookups", Poster Paper in Proceedings of ICNP 2008, pp.1-2.

69. Heeyeol Yu*, Rabi Mahapatra, "A Pipelined Indexing Hash Table using Bloom and Fingerprint Filters for IP Lookup", Poster paper in Proceedings of SIGCOMM 2008, pp.463-464.

70. J. D. Lee*, P. Bhojwani* and R. Mahapatra, "On-Line Health Monitoring via Statistical Clustering of On-Chip Communication", Workshop on Diagnostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, ACM/IEEE DATE 2007.

71. S. P. Mohanty, E. Kougianos, and R. Mahapatra, “A Comparative Analysis of Gate Leakage and Performance of High-K Nanoscale CMOS Logic Gates,” in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 31-38, 2007.

72. P. Bhojwani*, R. Singhal*, G. Choi, R. Mahapatra, "Forward Error Correction for On-chip Interconnection Networks", Proceedings of International Workshop on Unique Chips and Systems (UCAS-II) 2006.

Mahapatra Vitae

August 30, 2010

73. A. Biswas* and R. Mahapatra," Managing Confidence and Reliability in Complex Software

Systems with an Adaptive System Monitor", NSF Workshop on High-Confidence Software Platforms for Cyber-Physical Systems (HCSP-CPS), Virginia, Nov 2006.

74. M. Nolan* and R. Mahapatra, "A TDM Test Scheduling Method for Network-on-Chip Systems," to be presented in IEEE International Workshop on Microprocessor Verification & Testing (MTV) 2005.

75. H. Kim*, E. J. Kim and R. Mahapatra, "Power Management in RAID Server Disk System Using Multiple Idle States", Proceedings of International Workshop on Unique Chips and Systems (UCAS) 2005.

76. N. Goyal* and R. Mahapatra "Energy Characterization of CRAMFS for Embedded Systems", International Workshop on Software Support for Portable Storage (IWSSPS), March 2005.

77. N Subramanian*, Sunil Pandita* and Rabi Mahapatra, “Co-Design of Reactive Embedded System for Motion Control in Hostile Environment”, accepted for presentation in 8th IAPR workshop on Machine Vision Applications, Japan, December 2002. (Acceptance rate 66%)

78. K. Pramaod* and Rabi Mahapatra, “PAP: Power Aware Partitioning of Reconfigurable Systems”, HPCA Workshop on SSRS, Anaheim, CA, Feb. 8, 2003.

79. Debashis Mohanty*, Rabi Mahapatra and Gwan Choi, “A Design Space Exploration Framework in Multiprocessor SoC Codesign”, Proceedings of Workshop on RTSS Embedded Systems, Dec 3, 2001.

80. R. N. Mahapatra and B. K. Kar*, "A Systolic Design of Benes and Data Manipulator Network for VLSI Implementation", Third Intl. Workshop on VLSI System Design, pp.275-282, Jan.1990

81. L. K. Dash*, R. N. Mahapatra and B. N. Chatterji, "An Efficient Hardware Scheme for Computing Histogram", Intl. Seminar on Frontiers in Imaging, Trivandrum, July 1990.

82. R. N. Mahapatra and J. Majumdar*, "Modeling FCT Algorithm on MBCC Multiprocessors", Indo-US Workshop, Pune, Dec. 1993.

83. C. R. Tripathy*, R. N. Mahapatra and R. B. Misra, "Reliability Evaluation of MIN by Network Decomposition", First Intl. Workshop on Parallel Processing, Bangalore, pp.228-233, Dec. 1994.

84. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Design of Multiprocessor Based Image Tracker", IEEE Conf. on Microprocessor Application on Industrial Instrumentation Systems, Bhubaneswar, August 1994.

85. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, "Modeling of Wavelet Transform on Multistage Interconnection Network", Second Australian Conf. on Parallel and Real-Time Systems, Perth, September 1995.

86. R. N. Mahapatra, B. K. Das*, V. A. Kumar* and B. N. Chatterji, "Performance of 2D IFCT Algorithm on Multiprocessors", Proc. Workshop on Parallel Processing, BARC, Bombay, Feb.1990.

87. C. R. Tripathy*, R. B. Misra and R. N. Mahapatra, "An efficient method to evaluate reliability of multistage interconnection networks", Proc. Natl. Sem. on Information Technology, Itanagar, India, pp. 1-7, 1993.

F. Technical Reports

Mahapatra Vitae

August 30, 2010

1. Biswas, A., Mohan, S., Panigrahy, J., Mahapatra, R., "Intelligent Semantic Technologies for

Distributed Search Networks", Technical Report, Department of Computer Science, Texas A&M University, US, July 2008

2. John Wisinger* and Rabi Mahapatra, “FPGA Based Image Processing with the Curvelet Transform”, Technical Report # TR-CS-2003-01-0

3. Rabi N Mahapatra and Brian Murray*, “GEARS: Graphics Embedded Accelerated Rendering Systems: Development of an Embedded 3D Graphic Processor”, Technical Report # TR-CS-2002-05-1

4. Vinod Raman* Pankaj Bhagwat* and Rabi Mahapatra, “An Efficient Implementation of IS-95 CDMA Reverse Link Transceiver: A Codesign Approach”, TR# TR-CS-2002-05-2

5. Rajesh Prathipati* and Rabi Mahapatra, “A Three Step Approach For Low Power Static Scheduling Of Real-Time Embedded Systems” Technical Report # TR-CS-2002-06-0

6. Di Wu* and Rabi Mahapatra, “Multiprocessor Based Voltage Scaling: A Low-Power Technique”, Technical Report # TR-CS-2002-06-1

7. Raman Senthil Kumar*, Bhamy Madhava Shenoy* and Rabi Mahapatra, “Optimizing Power at the Physical Layer in a Wireless Ad Hoc Network”, TR# TR-CS-2002-06-2

8. Narayanan Swaminathan* and Rabi Mahapatra, “Communication Architecture Synthesis of Packet-Switched Network-on-Chip”, Technical Report # TR-CS-2002-08-0

9. Sunil Bhosekar* and Rabi Mahapatra, “Estimating Cache & TLB Power in Embedded Processor Using Complete Machine Simulation”, Technical Report # TR-CS-2001-08-0

Grants & Contracts Top

A. External Research Grants

Collaborative Research: CCLI (Exploratory): Introduction of Nanoelectronics Courses in Undergraduate Computer Science and Computer Engineering Curricula, NSF, 2010-2013

Safety net validation for Microprocessors and SoCs, DoT/AVSI, PI, 2009-2010.

Evaluation of Multi-Core COTS Microprocessors for Safety-Critical Applications, Rockwell Collins, PI 2009.

Exploring Semantic Routed Network for Cyber Infrastructures, NSF, PI: Mahapatra, March 2008- February 2010.

Microprocessor Evaluation, DoT–FAA, PI, Dec 2008 – April 2009.

A Comprehensive Methodology for Early Power-performance Estimation of Nano-CMOS Digital Systems, NSF, Co-PI, (PI: Mohanty, UNT), September 2007-August 2011.

Design of Robust and Energy Efficient Cyber-Physical Systems, NSF, Co-PI (PI: Bhattacharya), September 2007 – August 2009. NSF

Safety Analysis Framework of Microprocessors and SoCs in Avionics. Sponsors: FAA and AVSI (BAE, Boeing, GE Aviation, Honeywell, Lockheed Martin, Hamilton Sundstrand), PI, August 2007 – July 2008.

Low-Power Embedded Systems for Wireless Devices (Gift), Nokia, 2007-8

Power-aware Resource Management in Densely Packaged Distributed Real-Time Embedded Systems, NSF, PI: Mahapatra, Co-PI: Bettati, September 2005- August 2007.

Mahapatra Vitae

August 30, 2010

Research on Microprocessor Evaluation for Avionics, DoT (FAA), PI: Mahapatra, August 2004-Dec 2006.

Geostationary Imaging Fourier Transform Spectrometer (GIFTS) Star Tracker System, NASA, PI: Mahapatra, 3 grad students, Aug 2002- July 2003, Co-PI. M. Jacox, Commercial Space Center)

Research on Embedded Systems, Champion Innovation, PI: Mahapatra, September – December 2004.

Codesign Research & Lab activities, Ford Motor Company, PI: Mahapatra, Year 2001-2003,

Embedded System Research & Development, IBM, PI: Mahapatra, 2000,

Reconfigurable System Lab Design & Research, Xilinx Corp, PI: Mahapatra, Year 2002-03, Device and hardware donations.

Architecture Evaluation using Commercial Workloads, Investigator: Mahapatra (PI: Laxmi Bhuyan), Texas Advanced Technology Program, Grad Students 2, Jan. 2000 through Dec. 2001.

B. Infrastructure Grants (external)

Real-Time Linux OS from Montavista, Software & Tools of value $25K, Fall 2002

Academic Partnership Award, PI: Mahapatra, National Instruments, in the form of Hardware and Software, $145,800, Fall 1999.

Senior Design Laboratory Building Educational Equipment and Resources, PI: Mahapatra, Xilinx Corp. 65K, 1997-99.

Microprocessor System Design Lab Developments, PI: Mahapatra, Motorola Semiconductor Inc., Hardware/Firmware, $20K, Fall 1999.

Senior Design Projects using WinCE Devices, PI: Mahapatra, Microsoft Corp., Software and Devices, $20K, Fall 1999.

C. Infrastructure Gant (Internal)

Embedded Network System Lab, Texas A&M University, Co-PIs: Mahapatra, Liu and walker, $47,000.00, 1999.

Student Supervision Top

I am the primary advisor of all of the following students, with the exception of those students co-chaired by an ECE faculty member, who are co-advised. I have not listed students for which I was a courtesy co-chair. I have served as a member of a more than 30 M.S. and Ph.D. advisory committees, which are not listed.

Doctor of Philosophy

Amar Rasheed, PhD, Computer Engineering, Texas A&M

Amitava Biswas, PhD, Computer Engineering, Texas A&M

Yoonjin Kim, PhD, Computer Engineering, Texas A&M Thesis Topic: Design of Efficient Course grained Reconfigurable Architecture Thesis Defense Date: March 2009 Status: to join Samsung after graduation in May 2009.

Mahapatra Vitae

August 30, 2010

John Yu, PhD, Computer Science, Texas A&M Thesis Topic: Efficient Hashing Schemes for Some Packet Processing Applications Thesis Defense Date: December 2008. Status: Employed as Post doctoral fellow, Univ. of California, Riverside, CA.

Rohit Singhal, PhD, Computer Engineering, Texas A&M Thesis: Reliable and Low-power On-chip Interconnection (Co-Chair: G Choi, ECE) Thesis Defense Date: May 2007, Status: Employed Integrated Design Technology (IDT), Atlanta, GA

Praveen Bhojwani, PhD, Computer Engineering, Texas A&M Thesis: Communication Synthesis of Network on Chip Thesis Defense Date: December 2007, Status: Employed at Sun Micro Systems, CA

Di Wu, PhD, Computer Engineering, Texas A&M Thesis Title: Layer Assignment in Deep Sub-micron Technology (Co-Chair: J. Hu, ECE) Thesis Defense Date: July 2006, Status: Employed at Cadence, CA

B. K. Das, PhD, Computer Engineering, IIT Kharagpur Thesis Title: Modeling of Some Image Processing Transforms for Multiprocessor Architectures Thesis Defense Date: December 1995. (Co-Chair: B. N. Chatterji, ECE, IIT Kharagpur) Status: Employed as Joint Director, Defense Research Lab, India

Sudipta Mahapatra, PhD in Computer Engineering, IIT Kharagpur Thesis Title: Parallel Formulation of Artificial Neural Network Algorithms for Multiprocessors". Thesis Defense Date: December 1996, Status; Employed as Asst. Professor, IIT, Kharagpur, India.

C. R. Tripathy, PhD in Electrical Engineering, IIT Kharagpur Thesis Title: Dependability Analysis of Parallel Computer Interconnection Networks, (Co-Chair: R. B. Misra, EE Department, IIT Kharagpur) Graduation Date: December 1996. Status: Employed as Professor and Director/Principal, VSS Univ. of Technology, India.

Ranjani Sridharan, PhD Candidate, Computer Science, Texas A&M, January 2004 – present

Mark Nolen, PhD Candidate, Computer Engineering(ECE), Texas A&M, September 2003 – present (Co-Chair: G. Choi)

Jason D Lee, PhD Candidate, Computer Science, Texas A&M, September 2005 – present

Suniel Mohan, PhD Candidate, Computer Science, Texas A&M, September 2007 – present

Nikhil Gupta, PhD Candidate, Computer Science, Texas A&M, September 2007 – present

Suman K Mandal, PhD Candidate, Computer Science, Texas A&M, September 2007 – present

Aalap Tripathy, PhD Student

Kun Bian, PhD. Student

Mahapatra Vitae

August 30, 2010

Master of Science

Jaganath Panigrahi, Computer Science, Texas A&M, August 2009 Thesis Topic: Automatic Translation of Text to Concept Tree Status: Juniper, CA

Javier Jose, Computer Science, Texas A&M, August 2009 Thesis Topic: Real-time Multi-threaded Embedded System Architectures Status: Waiting to graduate and join PhD program at Texas A&M

Adam Burke, Computer Engineering, Texas A&M, December 2009 Thesis Title: Power saving in Consumer Electronics Systems Status: Employed at TEES and Entrepreneur

Seraj Ahmad, Computer Science, Texas A&M, May 2006 Thesis Title: Towards Efficient on-chip Logic Minimization Status: Employed at Magma Semiconductors, San Jose, CA

Jason Surprise, Computer Science, Texas A&M, December 2004 Thesis: An Energy efficient TCAM Enhanced Cache Architecture Status: Employed at Raytheon, Fort Worth, TX

Nitesh Goyal, Computer Science, Texas A&M, December 2004 Thesis: Macro-modeling and Energy Efficiency studies of File Management in Embedded Systems with Flash Memory. Status; Employed at Amazon, Seattle, WA

Anuj Kumar, Computer Science, Texas A&M, August 2004 Thesis: Increasing TLB Reach using TCAM Cells Status: Employed at Cisco, San Jose, CA

Subrata Acharya, Computer Science, Texas A&M, August 2004 Thesis: A Dynamic Slack Management Technique for Real-time Distributed Embedded Systems. Status: Employed at: Univ of Maryland after finishing PhD at Univ of Pittsburgh

Anand Rajaram, Computer Engineering, Texas A&M, August 2004 Thesis: Analysis and Optimization of VLSI Clock Distribution Network for Skew Variability Reduction (Co-Chair: Jiang Hu, ECE) Status: Employed at Texas Instruments, Dallas, TX

Junyi Ling, Computer Engineering, Texas A&M University, May 2004 Thesis: GPUs: A Case Study in Application Specific Processors Status: Employed at Pixar animation Studios, San Francisco, CA

V. C. Ravikumar, Computer Science, Texas A&M, May 2004 Thesis: Energy and Storage Efficient IP-Lookup Architecture (Co-Chair: J. C. Liu) Status: Employed at Hewlett Packard(HP), San Jose, CA

Rajesh Prathipati, Computer Science, Texas A&M, May 2004

Mahapatra Vitae

August 30, 2010

Thesis: Energy Efficient Scheduling Techniques for Real-time Embedded Systems Status: Employed as Software professional in India

Praveen Bhojwani, Computer Science, Texas A&M, December 2003 Thesis: Mapping Multimode System Communication to a Network-on-Chip. Status: Joined TAMU (PhD) and now at Sun Microsystems, San Jose, CA

Siddharth Choudhury, Computer Science, Texas A&M, August 2003 Thesis: Macro-modeling and Characterization of Filesystem EnergyConsumption for Diskless Embedded Systems. Status: Graduate Student at UC Irvine (PhD)

Pramod Vijay Kapagantula, Computer Engineering, Texas A&M, May 2003 Thesis: PAP- Power-aware Partitioning Framework for HW-SW Co-design Status: Employed as Software Designer, Bangalore, India

John Wisinger, Computer Science, Texas A&M, December 2002 Thesis: FPGA based Image Processing Accelerator Status: Employed as Consultant to NASA outsourcing Company at Conroe, TX

Narayan Swaminathan, Computer Engineering, Texas A&M, August 2002 Thesis: Communication Synthesis of on-chip Network Status: Employed at Texas Instruments, Houston, TX

Brian Murray, Computer Engineering, Texas A&M, May 2002 Thesis: Development of an Embedded 3-D Graphic Processor Status: Employed at Freescale, Austin, TX

Sunil Bhosekar, Computer Engineering, Texas A&M, December 2001 Thesis: Architecture-Level Power Estimation & Optimization using Complete Simulator Status: Employed at National Semiconductors, Dallas, TX

Rahul Katoria, Computer Engineering, Texas A&M, December 2001 Thesis: A Power-Aware Partitioning of HW-SW Codesign , (Co-Chair with TC Wang) Status: Employed at Intel Corp. CA

Srikant Kasturi, Computer Engineering, Texas A&M, December 2001 Thesis: An Optimized Datalink Layer, (Co-Chair with N. Reddy) Status: Employed atTexas Instruments, Houston, TX

Teaching Top

A. Courses Taught: All the courses taught at Texas A&M University. The courses offered at IIT Kharagpur are not listed.

ENGR 111B Introduction to Electrical and Computer Engineering, Fall 2005, Texas A&M (with N. Reddy and V. Sarin)

CPSC 312 Computer Organization, Spring 2007 – Fall 2008, Texas A&M

Mahapatra Vitae

August 30, 2010

CPSC 321 Computer Architecture, Summers 1997-98, Spring 1999, Spring 2004, Fall 2006, Texas A&M

CPSC 689/617 Embedded System Codesign, Spring 2002 – present, Texas A&M

CPSC 614 Computer Architecture, Summer 2005, Texas A&M

CPSC 462 Microcomputer Systems, Spring 1997, Summer 1997, Spring 1998, Summer 1998, Fall 1998, Summer 1999, Fall 1999, Summer 2000, Texas A&M

ENGR 112 Foundations of Engineering II, Spring 1999, Texas A&M

CPSC 489 Embedded Systems, Fall 2000, Texas A&M

CPSC 483 Computer System Design, Fall 1997, Fall 1998, Summer 1999, Fall 1999, Fall 2000 – Fall 2003, Fall 2004, Fall 2005, Texas A&M

CPSC 691 Research, 2001 - present, Texas A&M

CPSC 685 Special Topics, Spring 2003 - present, Texas A&M

CPSC 485 Problems, Summer 1998 - Fall 2004, Texas A&M

B. The new courses created: CPSC 312, CPSC 617, CPSC 489

C. The courses overhauled/redesigned: CPSC 321, CPSC 462, CPSC 483

D. Undergraduates (Mentoring students through research)

Stephen Hansen: REU Fellow 2004, University Research Fellow 2004, listed as CRA outstanding undergraduate in 2004.

Allen Parish: University Research Fellow 2004.

Amarachi Okrie: Undergraduate research student - helped her to write proposals to win grants to support her research during summer 2002 and subsequently from NSF to join in graduate program at Stanford.

E. Teaching improvements

Attended an online class on “Virtual Instructor Certificate Program”, Fall 2007.

Attended seminar on Teaching Excellency, at Center for Teaching Excellence in 1997.

Professional Activities Top

A. Editorial Activities

Associate Editor, ACM Transactions on Embedded Computing, 2008 – present

Editorial Board, International Journal on Information and Communication Technology 2006 – present

B. Conference Committee Activities

This list includes participation in conference organizing committees and acting as a session moderator. Conference refereeing is not included. I review 40-50 papers per year as an individual referee or as a member of a program committee.

Steering Committee Chair, Intl. Conf. on Information Technology 2004, 2005.

Mahapatra Vitae

August 30, 2010

Program Chair, IEEE Workshop on Embedded System Codesign (ESCODES 2002), September 24, San Jose, CA.

Program Chair, International Conference on Information Technology, CIT98.

Vice-General Chair, International Conference on Information Technology, CIT 1999, 2000

Program Committee, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'09)

Program Committee, ACM/IEEE Intl Conference on CASES 2009

Program Committee, IEEE Great Lake Symposium on VLSI (GLSVLSI'09)

Program Committee, 7th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2009)

Program Committee, Intl Workshop on Unique Chip and Sytems (UCAS'09, 08, 07, 06)

Program Committee, IEEE Intl Real-Time System Symposium (RTSS 2008).

Program Committee, International Conference on Embedded Software and Systems, 2007

Program Committee, Design Automation Conference (DAC) 2005, 2006, 2007

Program Committee, Intl. Workshop on Software Support for Portable Systems, 2006

Program Committee, IFIP International Conference on Embedded and Ubiquitous Computing (EUC) 2006.

Program Committee, IEEE Second Workshop on High Performance, Fault Adaptive, Large Scale Embedded Real-Time Systems (FALSE) 2005. 2006

Program Committee, International Workshop on Embedded Real-Time Systems Implementation (ERTSI) 2004, 2005.

Program Committee, International Conference on Parallel Processing (ICPP) 2004,

Program Committee, International Conference on Parallel & Distributed Systems (ICPADS) 2004,

Program Committee, First International Workshop on Network of Embedded Computing (NEC) 2004.

Program Committee, Intl. Workshop on Large Scale Real-Time Embedded System (LARTES) 2003.

Program Committee, IEEE Workshop on Large Scale Real-Time and Embedded Systems, December 2002.

Program Committee, IEEE RTSS Embedded Systems Workshop 2001,

Program Committee, PDPTA 97, 98, PDPTA99, Image Science System Technology (CISST99),

Program Committee, Advanced Computing (ADCOMP97 and ADCOMP98).

Publication Chair, Intl. Conference on Advanced Computing, ADCOM 01

Mahapatra Vitae

August 30, 2010

Industrial Chair, Intl. Workshop on Real-time Embedded Systems, 2001

Session Chair, IEEE Intl Symposium on Low Power Electronics and Design, Aug 2008

Session Chair, ACM/IEEE Conference on VLSI Design, January 2006.

Session Chair, IEEE Real-Time Application Symposium (RTAS), December 2002.

Session Chair, IEEE Real-Time Systems Symposium (RTSS), September 2002.

Session Chair, IEEE Intl Conf on Advanced Computing and Communication (ADCOM), 2000, 2002.

Session Chair, Parallel and Distributed Processing and Applications 1997, 1999.

Session Chair, International Conference in Information Technology, 2002.

C. University and Department Services

University Committee

Vice-Chair, CAFRT Preliminary Screening committee, Texas A&M, 2009-10

Senator, Faculty Senate, Texas A&M Univ., 2006-9

Senator, Research Executive Committee, Texas A&M Univ., 2008-9

Senator, Planning Committee, Texas A&M University, 2008-9

Senator, CAFRT Committee, Texas A&M Univ. 2007-2009

Department Committee

Undergraduate Advisory Committee, Dept. of Computer Science 2008

Graduate Admission Committee, Dept. of Computer Science 1999, 2000, 2008

Undergraduate Award Committee, Dept. of Computer Science, 2008

Coordinator, ABET, Computer Science Department 2006-2008

Member, Graduate Admission and Award Committee, CS Department, 2003-7

Member, Undergraduate Curriculum, Computer Science Dept, 2007

Member, ABET Preparation Committee, 2002

Member, Colloquium Committee, Computer Science Department, 2002

Member, Faculty and Staff Award Committee, CS Department, 2002

Member, Graduate Admission and Award Committee, CS Department, 2002

Member, Graduate Advisory Committee, CS Department, 2001, 2002

Member, Faculty & Staff Award Committee, 2001

Computer service committee of Computer science department Since Sept 1998- 2001

D. Invited Talks

Colloquium Speaker at University of Memphis, March 2010.

Workshop on Research and Teaching for VSSUT, Jan 2010

Keynote speaker: Intl conference on IT and Communication, India, January 9 2010

Panelist, “Evaluation of SoC and Microprocessors for Avionics”, Conference on Complex Electronics Hardware, organized by DoT-FAA, Denver, Aug. 2008.

SafetyNet of COTS Microprocessors and SoCs, Invited Talk at DoT sponsored Conference on Complex Hardware and Software, New Orleans, August, 2007.

Dynamic Slack Management for Low-power and Reliability in Embedded Systems, Invited Talk, Institute of Technology & Engineering Research , Bhubaneswar, India, July

Mahapatra Vitae

August 30, 2010

2007.

Microprocessor Evaluation for Avionics, Invited Talk, National conference on Complex Hardware and Software, Atlanta, July 2006.

Cyber Physical System – Issues and Challenges, Keynote, Intl. Conf on Information Technology, December 23, 2006, India

High-confidence Real-time Distributed Embedded Systems, Golden Jubilee Memorial Lecture, UCE, Jan 08, 2006.

Brighten up Your Cache Architecture with Blind Bits, Intel Research Lab, Santa Clara, CA; November 2004.

M-Trie for on-chip Logic Minimization, Router Architecture Group at CISCO, CA, November 2004.

Exploiting slacks in distributed embedded systems, Graduate Seminar in computer Science, Texas A&M University, September 2004.

Energy efficient File System Management for Embedded Systems, IBM Austin, February 2004.

TCAM based Router Architecture for IP lookup”, Department of Computer Science, University of California, Riverside, November 21, 2003.

Departmental seminar, “A Comprehensive Codesign Framework for Embedded Systems”, Faculty & graduate Students, Computer Science, University of Maryland at Baltimore County, Baltimore, MD, May 2001.

Hardware-Software Codesign for Embedded Systems, Department of Electrical Engineering, Oklahoma State University, Hartford University, and Michigan Tech University, April 2001.

Design Challenges in Embedded Systems, KIIT Deemed University, India, June 2000.

Departmental Seminar, "Reconfigurable Computing: A case for Digital Signal Processing", Faculty & Students, ECE Dept., Utah State University, Logan, UT, December 99.

Departmental Seminar, "Trends on Reconfigurable Computing", Faculty & Students, CS Dept., University of South West Texas, San Marcus, TX, June 1999.

E. Other Reviewing Activities

NSF Panelist: 1999 – present (CISE, ITR, CNS, CRC, etc.)

SERC proposals 1999, 2000

Intl. project proposals from UK, Canada and UK

Intl. Journals: IEEE Transactions on Computers, TPDS, Networking, TVLSI, TOADES, Circuits and Systems, ACM Transactions on Embedded Systems, Journal od Computers and Communication, Parallel Computing, JPDC etc.

Honors, Awards and Membership Top

Distinguished Visitor, IEEE Computer Society, North America, 2005-2007.

Ford Fellow 2001

BOYS- CAST Fellow

Senior-member IEEE.

International Outreach Top

Mahapatra Vitae

August 30, 2010

Founder and Chairman: Bhubaneswar Institute of Technology (BIT) in India

I have founded an academic institute called BIT, a non-profit organization in India during 2006. BIT has been established to produce high quality undergraduate students in the area of Computing and electrical engineering as most institutions (except IITs and NITs) lack good quality academic programs very much compatible to top ranking US universities. In 2008, BIT has received approvals to run its programs from the State and Federal Governments. I am currently holding the position of the Chairman in the Governing Body. The other members of the BIT Governing Body are:

Chairman, Computer Science Department, Univ. of California, Davis, USA

Chairman, Computer Science Department, Univ. of California, Riverside, USA

Director, National Institute of Technology, Rourkela, India

Chief Technology Officer, Wipro Info Tech, Bangalore, India

Secretary of Information Technology, Government of Orissa, India

Director, IIIT, Bhubaneswar, India BIT is going to have academic collaboration with several good ranking universities in US for student and faculty exchanges soon.