1. clippers shunt positive clippers - · pdf fileec & ld lab - 10csl38 2015 - 16 dept. of...

EC amp LD LAB - 10CSL38 2015 - 16

Dept of ISE CIT Gubbi 1

1 Clippers Shunt Positive clippers

a) To remove +ve peak above Vr level

Circuit diagram Waveform Transfer Characteristics

b) To remove +ve peak above some level (VR + Vγ)

Circuit diagram Waveform Transfer Characteristics

Design

1 To remove +ve peak above some level say (+3v)

Solution Vo= VR + Vγ

Vo= +3V then

VR = Vo ndash Vγ

VR = 3V ndash 07V (cut in voltage of diode)

VR = 23V

EC amp LD LAB - 10CSL38 2015 - 16


Experiment No 01 Date ________________

CLIPPERS amp CLAMPERS

AIM

a Design and construct a suitable circuit and demonstrate the working of positive

clippers double-ended clippers and positive clampers using diodes

b Demonstrate the working of the above circuits using a simulation package

Apparatus

Sl No Particulars Specification Quantity

1 Diode BY 127 02

2 Resistors 1 K 100 K 01 01

3 Capacitor 1f 01

4 Functional Generator 01

5 Multi-meter CRO amp Probes 01 Set

6 Base Board and Wires 01 Set

CLIPPERS

Theory

Clipper is a circuit which removes a part of the input signal with out distorting the

remaining part of the waveform It may be positive or negative part of an input signal

Clipping circuits is also known as limiters amplitude selectors or slicers This kind of

processing is useful for signal shaping circuit protection and communication

Based on working clippers circuits are classified as

1 Positive clipper one which removes positive part of signal

2 Negative clipper one which removes negative part of signal

Based on diode arrangement clipper circuit are classified as

1 Series Clipper

2 Shunt Clipper

EC amp LD LAB - 10CSL38 2015 - 16


c) To remove +ve peak above some level (say +3 v) amp -ve peak above some level (say -3v)

Circuit diagram Waveform Transfer characteristics

EC amp LD LAB - 10CSL38 2015 - 16


Procedure

1 Before making connections components are checked for good working conditions

2 Make the connections as shown in the circuit diagram

3 Using a signal generator apply a sine wave input Vi whose amplitude is greater than the

clipping level is applied to the circuit

4 Output waveform V0 is observed on the CRO Record the amplitude and time period from

the waveforms

5 For transfer characteristics the input voltage is given to the channel 2 output voltage is

given to the channel 1 and XY plotter is pressed

6 Clipped voltage is measured and verified with the designed values

Results

SL

No Clipper type Output (Theoretical)

Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Shunt positive

(without biasing)

2 Shunt positive

(with biasing)

3 Shunt positive

(with biasing)

4 Double ended

(without biasing)

5 Double ended

(with biasing)

6 Double ended

(with biasing)

EC amp LD LAB - 10CSL38 2015 - 16


2 Clampers

a) Positive peak clamped at reference voltage (Vr) level

Circuit diagram Waveform

b) Negative peak clamped to Vr level

Circuit diagram Wave form

Design

RL Cgtgt T

Assume T = 1 ms let RL C = 100 T then RL C = 100 ms

Let R1 = 100 K C = 1 f

EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory

Clamper adds a DC voltage to the AC level of input signal Sometimes it is necessary

to add the DC level to the AC output signal The circuits which are used to add DC level as

per the requirements to the AC output signal are called clamper circuits The capacitor diode

and resistance are the three basic elements of a clamper circuit The clamper circuits are also

called DC restorer or DC inserter circuits

Depending upon the positive DC or negative DC shift introduced in the output

waveform the clampers are classified as

a Positive clampers

b Negative clampers

A negative clamper is a circuit which adds a negative level to the AC output The

output waveform consists of a capacitor C ideal diode D and the load resistance RL During

the +ve cycle of the ip voltage Vi the capacitor gets charged through forward biased diode

bdquoD‟ up to the maximum value Vm of the ip signal Vi In the ndashve half cycle the diode D will

be remains reverse biased and the capacitor will be discharging through the resistance RL

In positive clamper by charging the orientation of the diode in the negative the +ve

clamper circuit can be achieved

During negative half cycle of the ip voltage Vi the diode D gets forward biased and

almost instantaneously the capacitor C gets charged In the positive half cycle the diode D is

reverse biased the capacitor starts discharging through RL

Both +ve amp -ve clampers are widely used for instance in television receivers to

change the reference level of video signals clampers are also used in radar and

communication circuits

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure

1 Components are checked for their good working conditions

2 Connections are made as shown in the circuit diagram

3 A square wave input Vi is applied through ASG

4 Keeping the ACDC knob of the CRO in DC position Output wave form V0 is observed

on the CRO

5 Clamped voltage is measured and verified with the designed values

Results

SL

No Clamper type Output (Theoretical)

Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive

(without biasing) 07 V

2 Negative


EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram RC - Coupled Amplifier

( a )

Design Given VCE = 5 V and IC = 2 mA Assume = 100

VCC = 2VCE = 2 X 5 = 10 V

Let VRE = 10 VCC = 1 V

RE = VRE ( IC + IB )

IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470

Apply KVL to collector loop

VCC ndash IC RC ndash VCE ndash VE = 0

RC = ( VCC ndash VCE ndash VE ) IC = ( 10 ndash 5 ndash 1 ) 2 m

RC = 2 k Choose RC = 18 k

Let IR1 = 10 IB = 10 X 20 A = 200 A

VR2 = VBE + VE = 06 + 1 = 16 V( Since transistor is silicon make VBE = 06 V )

R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k

R1 = ( VCC ndash VR2 ) IR1 = ( 10 ndash 16 ) 200 A

R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz

CE = 33 F Choose CE = 47 F

Choose CC1 = CC2 = 01 F

C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16



RC ndash COUPLED CE AMPLIFIER

AIM

a Design and construct a suitable circuit and determine the frequency response input

impedance output impedance and bandwidth of a CE amplifier

b Design and build the CE amplifier circuit using a simulation package and determine

the voltage gain for two different values of supply voltage and for two different values

of emitter resistance

Apparatus

Theory

An amplifier is a circuit which increases the voltage current or power of ip signal

where the frequency is maintained constant from op to ip signal The common collector or

emitter follower circuit has high ip impedance Typically it is 200K to 300K A single

stage emitter follower has ip impedance up to 800K The ip impedance of circuit can be

improved by direct coupling two stages of emitter follower amplifier CE amplifier provides

current in turn voltage amplification The ratio of Collector current to base current is noted as

the current amplification factor and is denoted as bdquo‟ie[ = ICIB] is very large

RC-Coupled amplifier is employed as voltage amplifier and where non-linear

distortion is less because it has an excellent audio frequency over a wide range of

frequencies Circuit contain voltage divider resistor [R1 amp R2]

R1 R2 and RC are selected in such a way that transistor operates in active region Re

is used for stabilization of operating point Coupling capacitor is used to block dc current

The emitter by-pass capacitor Ce is connected to avoid negative feedback

Input signal increases base current in turn collector current increases [ie Ic = Ib]

Hence output voltage is large compared to input voltage which is known as amplification


1 Transistor SL 100 01

2 Resistors as per design

3 Capacitors 47 f 01f 01 02

4 DRB 01

5 Multimeter + CRO Probes 01 Set

6 Base Board + Wires 01 Set

EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV

f in Hz Vo in Volts Av = (Vo Vi) Av db = 20 log (Vo Vi)

Simulation Results

Sl NO Vi in Volts Vo in Volts Av = (VoVi) Av in db Av in db using Bode plotter

EC amp LD LAB - 10CSL38 2015 - 16


Procedure

1 Components Equipment are tested for their good working condition


3 By keeping the voltage knobs in minimum position and current knob in maximum

position switch on the power supply

4 By disconnecting the AC source measure the quiescent point (VCE and IC = VRC RC)

I) To plot the frequency response

1 The input frequency is kept in the mid-band region (around 10 kHz) and the input voltage

is adjusted to a convenient value in ASG so that the output waveform is distortion less

and this value of input voltage must be kept constant throughout the experiment

2 Frequency of the input signal is varied from 10Hz to its max Value 10MHz in steps and

at each step corresponding output voltage Vo is noted down

3 All the readings are tabulated and a graph of gain in db vs frequency in Hz is plotted on a

semi log sheet

4 3db bandwidth is determined from the frequency response curve

II) To measure input impedance (Zi)

1 Connections are made as shown in the circuit diagram (c)

2 The input frequency is kept in the mid-band region with all knobs of DRB in the Zero

position the output voltage falls to half of the initial output voltage

3 The value of DRB is recorded which is equal to input impedance Zi of the amplifier +

signal generator resistance 50

Therefore Zi = DRB Value ndash Audio Signal Generator Resistance (50)

[Note Zi lt R1 | | R2]

III) To measure output impedance (Zo)

1 Connections are made as shown in the circuit diagram (d)

2 In the mid-band frequency region (where the gain is constant) with DRB in its max

Value the output voltage is measured

3 The DRB is varied till the output voltage falls to half the initial value

4 The value of DRB is recorded which is equal to the output impedance Zo of the amplifier

[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)

Input impedance Output impedance

(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16


IV) To find the Gain Bandwidth Product (GBW)

1 Gain Bandwidth Product = Max gain (without db) X bandwidth (Figure of merit)

= Avm X (f2 ndash f1) Hz

Results

1 Quiescent point VCE = ____ V IC = _____ mA

2 Maximum Gain Av=helliphelliphellip

3 Input Impedance Zi = helliphellipΩ

4 Output Impedance Zo = helliphellipΩ

5 Bandwidth BW= helliphellipHz

6 Figure of Merit FM (GBW) helliphellip

EC amp LD LAB - 10CSL38 2015 - 16


MOSFET Circuit Diagram

Tabular Column

Transfer Characteristics

VDS1 = _____________ V VDS1 = _____________ V

VGS in Volt ID in mA VGS in Volt ID in mA

G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16



STATIC CHARACTERISTICS OF MOSFET

AIM

a Design and construct a suitable circuit and determine the drain characteristics and

transconductance characteristics of an enhancement-mode MOSFET

Apparatus

Sl No Particulars Range Quantity

1 MOSFET ( IRF 540 ) - 1

2 Milliammeter 0-20200mA 1

3 Multimeter - 1

4 Sping board amp Connecting wires - few

Theory

A MOSFET is a voltage controlled device and requires a only a small input current

The switching speed of MOSFET is very high and the switching time s are of the order of

nanoseconds It has very high input impedance and works at very high switching frequency

MOSFETs are of two types namely Enhancement type and Depletion type Each type

are subdivided into two types namely p-channel and n-channel IRF 540 is an n-channel

enhancement MOSFET An n-channel enhancement MOSFET has N substrate with p-

impurities on other side A thin layer of metal oxide is deposited over the left side of the

channel A metallic gate is deposited over the silicon di oxide layer which is an insulator

Hence gate is insulated from the channel and for this reason MOSFET is sometimes called

insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column

Drain Characteristics

VGS1 = _____________ V VGS1 = _____________ V

VDS in Volt ID in mA VDS in Volt ID in mA

Ideal Graph

Transfer Characteristics Drain Characteristics

ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1

Constant resistance region

Constant current region

EC amp LD LAB - 10CSL38 2015 - 16


Procedure


1 Check the components Equipment for their working condition


3 Set VDS to some convenient voltage (say 02 V)

4 Increase VGS gradually and note down the corresponding changes in drain current ID

5 Repeat the above step for different value of VDS (say 03 V)

6 A graph of VGS Vs ID is plotted and from the graph Trans conductance is calculated

Output Characteristics

1 Set VGS to some convenient voltage greater than threshold voltage VT

2 Increase VDS gradually and note down the corresponding changes in drain current ID

3 Repeat the above step for different value of VGS

4 A graph of VDS Vs ID is plotted and from the graph drain resistance is calculated

Results

Transconductance gm = ID VGS = ____________ mho

Drain Resistance RD = VDS ID = ____________

EC amp LD LAB - 10CSL38 2015 - 16


CMOS Inverter Circuit Diagram

The left hand part of the above circuit shows the connection of a CMOS inverter

XLA1 stands for Logical Analyzer

The right hand part shows the wave forms of a CMOS

If the PMOS is ON NMOS is OFF and If NMOS is ON PMOS is OFF

If VGS = +ve NMOS is ON For VGS = 0 or ndashve NMOS is OFF

If VGS = -ve PMOS is ON For VGS = 0 or +ve PMOS is OFF

EC amp LD LAB - 10CSL38 2015 - 16


b) Design and build CMOS inverter using a simulation package and verify its truth table

CMOS INVERTER

A CMOS gate a building block of a digital IC is composed of an n-channel (NMOS)

and p-channel (PMOS) metal-oxide-semiconductor field effect transistors (MOSFETs) In

the circuit diagram the PMOS device appears in the upper region (connected to a dc bias

VCC logic 1) and the NMOS device appears in the lower region (connected to the ground

potential GND logic 0)

For operation the input Vin connected to the Gate terminals of both NMOS and

PMOS turns ON one device type and turns OFF the other device type The ONOFF

behavior of a MOSFET device depends on whether the voltage difference between Gate and

Source Vgs is greater or less than the threshold voltage VT which is a property intrinsic to

the device1 (ie device structure and material property) When a MOSFET device is ON its

channel region (the tall rectangle in the middle of the transistor symbol the left-hand-side

diagram) is filled with charge carriers (blue for electrons and red for holes) and thus that

device electrically connects (or short circuits) the output Vout to the high voltage VCC or to

low voltage GND

For the CMOS inverter Vout is connected to the VCC (ie logic 1) if the PMOS is

ON and the NMOS is OFF Vout is connected to the GND (ie logic 0) if the PMOS is

OFF and the NMOS is ON Since the transistor ONOFF behavior is controlled by the input

voltage Vin the output Vout is determined by the Inverter gate and the input

EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram (With reference) Circuit Diagram (Without reference)

With Reference Wave forms Transfer characteristics

Without Reference Wave forms Transfer characteristics

EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM

a Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values

and demonstrate its working

b Design and implement a Schmitt trigger using Op-Amp using a simulation package

for two sets of UTP and LTP values and demonstrate its working

Apparatus


1 OP AMP 741 1

2 Resistors As per design 1

3 signal generator - 1

4 CRO with probes - 1 set

5 DC power supply - 1

6 Spring board and wires - 1 set

Procedure



3 A sinusoidal input whose amplitude is greater than the magnitude of the UTP amp LTP is

applied a square wave output is obtained and observed on the CRO

4 UTP amp LTP points are noted

5 To obtain transfer characteristics input is applied to channel A and output to channel B

6 UTP amp LTP are measured on the transfer characteristics also and thus verified

Note The amplitude of the input voltage should be greater than the magnitude of UTP amp

LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R

Design With Reference

Let given UTP = 6V LTP= -2V Assume Vsat = 12 V

R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1

V R R 1satUTP - LTP = 8 = 2 R = 2RR +R R 2

[eqn 2]

Assume R2 = 1K then R1 = 2 K

Substitute R1 and R2 in eqn1 and calculate VR VR = 3V

Similarly design for UTP = +4 +8 2 and ndash2 LTP = -4 +2 -4 and ndash4

Design With out Reference

Let given UTP =4V LTP=-4V Assume Vsat = 12 V

R 1

1 2

V RUTP + LTP = 0 = 2

R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference

Sl No UTP(TH) LTP(TH) Hardware Software

UTP(Prac) LTP(Prac) UTP(Prac) LTP(Prac)



EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram Wave forms

Design

Given f0 = 1 Khz

Relation between R1 and R2 is

R2 = 116 R1

Let R1= 10 kΩ Then R2 = 116 kΩ

To calculate R

Formula to be used 2RC

1f0

Required f0 = 1 Khz Assume C = 01microf then R= 5 kΩ

EC amp LD LAB - 10CSL38 2015 - 16



OP AMP RELAXATION OSCILLATOR

AIM

a Design and construct a rectangular waveform generator (Op-Amp relaxation

oscillator) for given frequency and demonstrate its working

b Design and implement a rectangular waveform generator (Op-Amp relaxation

oscillator) using a simulation package and demonstrate the change in frequency when

all resistor values are doubled

Apparatus

Sl No Particulars Range Qty

1 IC microA 741 01

2 Resisters As per Design -

3 Capacitors As per Design -

4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY

A relaxation oscillator is a circuit that repeatedly alternates between two states at

with a period that depends on the charging of a capacitor The capacitor voltage may change

exponentially when charged or discharged through a resistor from a constant voltage or

linearly when charged or discharged through a constant current source With exponential

charging the timing is expressed in terms of time constants RC

PROCEDURE


2 Make connections as shown in circuit diagram

3 Check the output at pin 6 of op Amp

4 Measure the frequency of the output and compare with the given value

Result

Sl No f0 (Theoretical) f0 (pract) HW f0 (pract) simulation Remarks

EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram

Astable Multivibrator Wave Form

Design

Let Time period T required be 1msec and duty cycle D = 60 = 06

Capacitor charging time = tc = 069RA C ---------- (1)

Capacitor discharging time = td = 069 RB C ---------- (2)

But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2

Choose C = 001microf

R2 = 59k

Choose RB=56 k (+330)

From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16



ASTABLE MULTIVIBRATOR

AIM

Design and implement an astable multivibrator circuit using 555 timer for a given

frequency and duty cycle

Apparatus


1 555 timer -- 1

2 Power Supply -- -

3 Resistors As per design -

4 Capacitors As per design -

5 CRO and patch cords -- 1 set

Procedure

a) Check the components Equipment for their working condition

b) Rig up the circuit as shown in the diagram

c) Observe the out put wave form note down tc amp td

d) And calculate the duty cycle

e) Compare the theoretical value with practical value

Result

Sl No F(Theoretical) D(Theoretical) F(Practical) D(Practical)

EC amp LD LAB - 10CSL38 2015 - 16


Function Table

INPUTS OUTPUT Comments

A2 A1 A0 EN Q Q

X X X H H H If En pin is at logical high value then

irrespective of input output will be 1

L L L L D0 D0 If En pin is at logical zero value then

if input is 0 0 0 then output will be D0

L L H L D1 1D If En pin is at logical zero value then


L H L L D2 2D If En pin is at logical zero value then


L H H L D3 3D If En pin is at logical zero value then


H L L L D4 4D If En pin is at logical zero value then


H L H L D5 5D If En pin is at logical zero value then


H H L L D6 6D If En pin is at logical zero value then


H H H L D7 7D If En pin is at logical zero value then


EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM

a Given a 4-variable logic expression simplify it using Entered Variable Map and

realize the simplified logic expression using 81 multiplexer IC

Apparatus

SI NO Particulars Specification Quantity

1 Multiplexer IC IC 74151 1

2 Trainer Kit ---- 1

3 Patch cords ---- 20

Theory

A multiplexer or simply ldquomuxrdquo is a device that selects between a number of input

signals In its simplest form a multiplexer will have two input signals 1 control input and 1

output The number of inputs is generally a multiple of 2 (2 4 8 16 etc) the number of

outputs is 1 and n control inputs are used to select one of the data inputs The multiplexer

output value is same as that of the selected data input

In other words the multiplexer works like the input selector of a home music system

Only one input is selected at a time and the selected input is transmitted to the single output

While on the music system the selection of the input is made manually the multiplexer

chooses its input based on a binary number the address input

Multiplexers are used in building digital semiconductors such as CPUs and graphics

controllers They are also used in communications the telephone network is an example of a

very large virtual mux built from many smaller discrete ones

EC amp LD LAB - 10CSL38 2015 - 16


Consider a 4 Variable expression as

f(w x y z) = sum (2457101114) + sum‟ d (89121315)

Let bdquoz‟ be map entered variable

Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)

If function F equals 0 for both values of MEV

enter 0 in appropriate cell on MEV map 1 0 0 0 1 0

2 0 0 1 0 1

Z (D1)

If function F complements to the values of MEV

then enter complement of MEV 3 0 0 1 1 0

4 0 1 0 0 1 1 (D2)

If function equals 1 for both values of MEV

enter 1 5 0 1 0 1 1

6 0 1 1 0 0 Z (D3) If function equals to MEV value the enter MEV

7 0 1 1 1 1

8 1 0 0 0 X X (D4) If both function values are X then enter 0 or 1

9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure

1 Verify all components and patch cords for there good working condition

2 Make the connection as shown in the circuit diagram

3 Give supply to the trainer kit

4 Provide input data to circuit via switches and verify the truth table

EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs

1 Write the Verilog VHDL code for a 2 Input AND gate Simulate and verify its working

Entity And1 is

Port (A B IN STD_LOGIC

C OUT STD_LOGIC)

End And1

Architecture Behavioral of And1 is

Begin

C lt= A AND B

End Behavioral

NOTE write the VHDL code for remaining basic and universal gates Simulate and realize

the output

2 Write the Verilog VHDL code for a half adder Simulate and verify its working

Entity Half_adder is


SUM CARRY OUT STD_LOGIC)

End Half_adder

Architecture Behavioral of Half_adder is

Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


b Design and develop the Verilog VHDL code for an 81 Multiplexer IC Simulate and

verify its working

Entity MUX is

Port( sel IN STD_LOGIC_VECTOR(2 DOWNTO 0)

A B C D E F G H IN STD_LOGIC

Z OUT STD_LOGIC)

End MUX

Architecture Behavioral of MUX is

Begin

Process (sel A B C D E F G H)

Begin

Case sel is

When ldquo000rdquo =gt Z lt= A

When ldquo001rdquo =gt Z lt= B

When ldquo010rdquo =gt Z lt= C

When ldquo011rdquo =gt Z lt= D

When ldquo100rdquo =gt Z lt= E

When ldquo101rdquo =gt Z lt= F

When ldquo110rdquo =gt Z lt= G

When ldquo111rdquo =gt Z lt= H

When others =gt NULL

End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram

JK FLIP-FLOP TRUTH TABLE

J K Clk Q Q

0 0 Posndash edge No Change

0 1 Posndash edge 0 1


1 1 Posndash edge Toggle

X X Neg-edge No Change

EC amp LD LAB - 10CSL38 2015 - 16



MS ndash JK FLIP FLOP

AIM

a Realize a J-K Master Slave Flip-Flop using NAND gates and verify its truth table

Apparatus

SI No Particulars Specification Quantity

1 3 input Nand IC 7410 01

2 Input Nand IC 7400 02

3 Trainer kit --- 01

4 Patch cords --- 20

Theory

JK flip-flop provides the solution for SR flip-flop problem Compared to SR flip-flop

JK flip-flop has two new connections from the Q and Q outputs back to the original input

gates JK flip-flop behaves like the SR flip-flop except for input condition 1 and 1 Its output

toggles for every clock pulse input unlike SR flip-flop Although JK flip-flop circuit is an

improvement on the clocked SR flip-flop it still suffers from timing problems called race

This problem can be solved by Master-slave flip-flop

The Master-slave JK flip-flop is basically two JK bitable flip-flops connected together

in a series configuration with the outputs form Q and Q‟ from the slave flip-flop being fed

back to the inputs of the Master with the outputs of the Master flip-flop being connected to

the two inputs of the slave flip-flop The circuit accepts input data when the clock signal is

ldquoHIGHrdquo and passes the data to the output on the falling-edge of the clock signal In other

words the Master-Slave JK flip-flop is a ldquoSynchronousrdquo device as it only passes data with

the timing of the clock signal

Procedure

1 Verify all the components and patch cords for there good working condition

2 Make connection as shown in the circuit diagram



Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16


b Write the Verilog VHDL code for D FF with positive-edge triggering Simulate and verify

its working

Entity DFF is

Port (D CLK IN STD_LOGIC

Q OUT STD_LOGIC)

End DFF

Architecture Behavioral of DFF is

Begin

Process (CLK)

Begin

If (CLK‟event and CLK = bdquo1‟) then

Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram of Mod ndash 8 counter

DESIGN FOR MOD 8 UP COUNTER

Present State Next state Flip flop inputs

QC QB QA QC+1 QB+1 QA+1 KC JC KB JB KA JA

0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM

a Design and implement a mod-n (nlt8) synchronous up counter using J-K Flip-Flop

ICs and demonstrate its working

Apparatus

SlNo Particulars RangeSpecification Qty

1 JK flip-flop IC 7476 2


3 2 input And IC 7408 1

4 Digital IC trainer kit --- 1


Theory

In digital logic and computing a counter is a device which stores (and sometimes

displays) the number of times a particular event or process has occurred often in relationship

to a clock signal

A synchronous counter is one whose output bits change sate simultaneously Such a

counter circuit can be built from JK flip-flop by connecting all the clock inputs together so

that each and every flip-flop receives the exact same clock pulse at the exact same time

By examining the four-bit binary count sequence it noticed that just before a bit

toggles all preceding bits are high That is a synchronous up-counter can be implemented

by toggling the bit when all of the less significant bits are at a logic high state For example

bit 1 toggles when bit 0 is logic high bit 2 toggles when both bit 1 and bit 0 are logic high

bit 3 toggles when bit 2 bit 1 and bit 0 are all high and so on

IC 7476 contains 2 JK flip-flops with preset and clear signals

Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


Mod-5 Circuit Diagram

EC amp LD LAB - 10CSL38 2015 - 16


b Design and develop the Verilog VHDL code for mod-8 up counter Simulate and verify

its working

Entity Mod8 is

Port (CLK CLR IN STD_LOGIC

Q INOUT STD_LOGIC_VECTOR (2 DOWNTO 0))

End Mod8

Architecture Behavioral of Mod8 is

Begin

Process (CLK)

Begin

If (CLK‟event and CLK = ‟1‟) then

If (CLR = bdquo1‟) then

Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495

Mode-0 for serial shifting of data

Mode-1 for parallel loading of data

Clk 1 is used for right shifting of data

Clk 2 is used for left shifting of data and for parallel

loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM

a Design and implement a ring counter using 4-bit shift register and demonstrate its

working

Apparatus

SlNo Particulars Specification Qty

1 IC 7495 7404 11

2 Digital IC trainer kit - 1

3 Patch cords - 20

Theory

A ring counter is a counter where the output of one flip-flop connects directly into the

input of another to produce a particular output pattern The ability to load the flip-flops to

particular state permits a repeatable output pattern Typically a pattern consisting of a single 1

bit is circulated so the state repeats every N clock cycles if N flip-flops are used It can be

used as a cycle counter of N states

A Johnson counter (or switch tail ring counter twisted-ring counter walking-ring

counter) is a modified ring counter where the output from the last stage is inverted and fed

back as input to the first stage A pattern of bits equal in length to twice the length of the shift

register thus circulates indefinitely These counters find specialist applications including

those similar to the decade counter digital to analogue conversion etc

IC 7495 is a 4-bit shift register with parallel inputsoutput serial output with rightleft

shifting Pin 6 decides the mode if it is at low then it will act as a serial shifter and if it is at

high then it will load the data parallel Shifting left requires external connection of QB to A

QC to B and QD to C serial date is entered at input D

Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Johnson Counter Truth table for Johnson Counter

Johnson Counter (switched tail counter)

Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16


b Design and develop the Verilog VHDL code for switched tail (Johnson) counter

Simulate and verify its working

Entity Johnson is

Port (CLK IN STD_LOGIC

Q INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) = ldquo0000rdquo)

End Johnson

Architecture Behavioral of Johnson is

Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)

For i in 2 downto 0 loop

Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS

R01 R02 R91 R92 QD QC QB QA

H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM

Design and implement an asynchronous counter using decade counter IC to count up

from 0 to n (nlt=9) and demonstrate its working

Apparatus


1 Decade counter IC 7490 1



Theory

In asynchronous counter a clock signal is provided for one flip-flop and its output is

provided as clock source for next flip-flop The output of asynchronous counter is not

synchronized with clock signal

The 7490 is an asynchronous decade counter able to count from 0 to 9 cyclically and

that is its natural mode To make 7490 to work in normal mode the pin numbers 2 3 6 and 7

should hold at Low state QA QB QC QD are 4 output pins which gives the binary value of

the decimal count Pin 14 is Clock input

Pin 2 and 3 Set inputs They held to Low to activate 7490 IC as decade counter At

any instant of time if they provide High signal then the output will hold at Low state until

Pin 2 and 3 brought to Low voltage

Pin 6 and 7 Clear inputs At any instant of time if they provide High signal then the

output will hold at High state until Pin 6 and 7 brought to Low voltage

Procedure


2 Connect the reset terminals to high and set terminals to low and observer the output

3 And now make connection as shown in the circuit diagram

4 Give supply to the trainer kit and verify the truth table

Result

EC amp LD LAB - 10CSL38 2015 - 16


7490 as a Decade counter

Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V

Where the D0 D1 D2 D3 take the value 0 or 1 Rf is feed back resistor Vref if reference

voltage

Tabulation

Binary Inputs Theoritical Values(V) Practical Values(V)

D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation

Digital input (10)10 = (1010)2 in binary that means D0 = 0 D1 = 1 D2 = 0 D3 = 1

R = 1 KΩ Rf = 2 KΩ Vref = 5V by substituting this values in above equation we get

V2561016

1018041201

16

5

K1

K2V0

Similarly find out for all the possible input combinations and verify them

EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM

Design and construct a 4-bit R-2R ladder DA converter using OpAmp Determine its

accuracy and resolution

Apparatus


1 Resistors 1 KΩ 2 kΩ 36

2 Op-Amp IC microA 741 1

3 Trainer kit --- 1

4 Spring board amp connecting wires ---- 1 set

5 CRO amp probes or Multimeter ---- 1

Theory

An R-2R ladder is a digital to analog converter It uses only two different resistor

values throughout the circuit because of this it provides more precision than the scaled

resistor approach to DAC The weighting factors can be obtained by a thevenin analysis of

each input point

Procedure


2 Make connection as shown in the circuit diagram And give supply to the trainer kit

Provide input data to circuit via switches and verify the truth table

Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES

1 Stephen Brown Zvonko Vranesic Fundamentals of Digital Logic Design With

VHDL 2nd

edition TATA McGraw Hill 2005

2 Fundamentals of Digital Logic with Verilog Design Stephen Brown Zvonko

Vranesic TMH 2006

3 Jacob Millman Christos Halkias Chetan D Parikh Millman‟s Integrated Electronics

Analog and Digital Circuits and Systems 2nd

Edition Tata McGraw Hill 2010

4 R D Sudhaker Samuel Electronic Circuits Sanguine-Pearson 2010

5 Electronic Principles Albert Malvino amp David J Bates 7th

Edition

6 Electronic Devices and Circuit Theory Robert L Boylestad Louis Nashelsky

9th

Edition

7 Anil K Maini Varsha Agarwal Electronic Devices and Circuits Wiley 2009

8 Donald P Leach Albert Paul Malvino amp Goutam Saha Digital Principles and

Applications 7th


9 M Morris Mano Digital Logic and Computer Design 10th

Edition Pearson Education

10 R D Sudhaker Samuel Illustrative Approach to Logic Design Sanguine- Pearson

2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS

CLIPPERS AND CLAMPERS

1 Define p-n junction

2 Mention the different types of diodes

3 Explain the V-I characteristics of diode

4 Define a Clipping Circuit

5 Mention the different types of clipping circuits

6 Compare Series and Shunt Clipper

7 Mention the applications of clipper circuits

8 Define Clamping Circuit

9 What are the different types of clamping circuits

10 Define positive and negative clamping

11 Mention the applications of clamping circuits

12 What could be the voltage across the capacitor

13 What is the importance of C amp RL in the clamping circuit

RC COUPLED CE AMPLIFIER

1 Define Quiescent Point

2 State different region of operating transistor

3 What are different configurations of operating the transistor

4 Compare common base common emitter and common collector configuration of

transistor

5 Define Amplifier Mention different types of amplifiers

6 Define

7 Define bdquoEarly Effect‟ of transistor

8 Name different type of amplifier based on coupling

9 What are the factors that affect the stability of a transistor

10 Define Biasing Mention its different types

11 What are the reasons for the reduction in gain at low and high frequency

12 What is the importance of emitter-by-pass capacitor

MOSFET 1 Define MOSFET

2 What are the different types of MOSFET

3 Differentiate between enhancement mode and depletion mode MOSFET

4 Bring out the differences between MOSFET JFET and UJT

5 Explain the working of a CMOS Inverter

SCHMITT TRIGGER 1 What is Schmitt Trigger

2 Explain the working of Schmitt trigger

3 Define the term UTP and LTP

4 Define Dead band or Dead zone

5 Mention the applications of Schmitt Trigger

RELAXATION OSCILLATOR 1 Why this circuit is named as Relaxation oscillator

2 What is an oscillator

3 What are the different types of oscillators

EC amp LD LAB - 10CSL38 2015 - 16


4 Explain the working of the relaxation oscillator


1 Define a multivibrator

2 What are the different types of Multivibrators

3 Explain the working of astable multivibrator

4 Define duty cycle

5 What is the necessity of the diode in the circuit shown of a astable multivibrator

6 Explain the operation of a 555 timer IC

MULTIPLEXER

1 What is a multiplexer

2 What is the advantage of using VEM Technique

3 What is the importance of Enable Pin

4 Differentiate between a MUX and a Decoder

5 What is the importance of select line in a MUX

6 How to decide the number of Select lines for any MUX

FLIP FLOPS

1 Differentiate between a latch and a Flip-Flop

2 What are the different types of flip-flops Explain by showing the truth table

3 What is Race-around problem How can you rectify it

4 Differentiate between Sequential and Combinational circuits

5 Explain the working of a MS-JK flip-flop

6 What are the difference between +ve edge triggered and ndashve edge triggered circuit

7 What is a counter

8 Differentiate between synchronous and asynchronous counters

9 What types of flip-flops can be used to implement the memory elements of a counter

10 Explain the use of PRESET and CLEAR pins in flip-flop

SHIFT REGISTERS AND COUNTERS

1 What are registers

2 What are shift registers

3 What are the different types of shift registers

4 Differentiate between SIOP PISO PIPO and SISO

5 Differentiate between a Ring counter and Johnson counter

6 Why it is called as decade counter

7 Explain the pins of 7490 IC

8 Difference between BCD and Binary counter

9 What is the maximum count of a BCD counter

10 Mention the steps in designing a counter

11 Identify the internal components of IC 7490

R-2R LADDER

1 What is ADC What is DAC

2 Mention the types of DAC

3 What is the resolution of DAC

4 What is the advantage of using R-2R over weighted resistor method

5 Which is the fastest ADC Why

6 Mention the types of ADC

7 Give some examples of monolithic ADC and DAC

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127

Diodes must be connected the correct way round the diagram may be labeled a or +

for anode and k or - for cathode (yes it really is k not c for cathode) The cathode is

marked by a line painted on the body Diodes are labeled with their code in small print you

may need a magnifying glass to read this on small signal diodes

Testing a diode with a DIGITAL Multimeter

Digital Multimeter has a special setting for testing a diode usually labeled with the diode

symbol

Connect the red (+) lead to the anode and the black (-) to the cathode The diode should

conduct and the meter will display a value (usually the voltage across the diode in mV

1000mV = 1V)

Reverse the connections The diode should NOT conduct this way so the meter will

display off the scale (usually blank except for a 1 on the left)

2 TRANSISTOR

Testing a transistor with a Multimeter

Set a digital Multimeter to diode test and as described above for testing a diode

Test each pair of leads both ways (six tests in total)

The base-emitter (BE) junction should behave like a diode and conduct one way only

The base-collector (BC) junction should behave like a diode and conduct one way only

The collector-emitter (CE) should not conduct either way

Testing an NPN transistor

EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor

There are two types of standard transistors NPN and PNP with different circuit

symbols The letters refer to the layers of semiconductor material used to make the transistor

Most transistors used today are NPN because this is the easiest type to make from silicon

SL 100 is an NPN transistor

3 MOSFET

Metal Oxide Semiconductor Field Effect Transistor

Testing a MOSFET

This testing procedure is for use with a digital Multimeter in

the diode test-range with a minimum of 33 volt over dut

(diode-under-test) If your multi-meter is less than that it will

not do the test Check your meter manual for the specs

Connect the Source of the MosFet to the meters negative (-)

lead

1) Hold the MosFet by the case or the tab but dont touch the metal parts of the test probes

with any of the other MosFets terminals until needed Do NOT allow a MOSFET to

come in contact with your clothes plastic or plastic products etc because of the high

static voltages it can generate

2) First touch the meter positive lead onto the MosFets Gate

3) Now move the positive probe to the Drain You should get a low reading The MosFets

internal capacitance on the gate has now been charged up by the meter and the device is

turned-on

4) With the meter positive still connected to the drain touch a finger between source and

gate (and drain if you like it does not matter at this stage) The gate will be discharged

through your finger and the meter reading should go high indicating a non-conductive

device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16


4 OP AMP(OPERATIONAL AMPLIFIER)

Where

V+ non-inverting input

Vminus inverting input

Vout output

VS+ positive power supply (sometimes also VDD VCC or VCC + )

VSminus negative power supply (sometimes also VSS VEE or VCC minus )

5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C

INTRODUCTION TO MULTISIM

NI Multisim (formerly MultiSIM) is an electronic schematic capture and simulation

program which is part of a suite of circuit design programs along with NI Ultiboard

Multisim is one of the few circuit design programs to employ the original Berkeley

SPICE based software simulation Multisim was originally created by a company named

Electronics Workbench which is now a division of National Instruments Multisim includes

microcontroller simulation (formerly known as MultiMCU) as well as integrated import and

export features to the Printed Circuit Board layout software in the suite NI Ultiboard

Multisim is widely used in academia and industry for circuits‟ education electronic

schematic design and SPICE simulation

Steps to Proceed

Step 1 Open Multisim

Step 2 Place Components

Step 3 Wire Components

Step 4 Place a Simulation Source

Step 5 Place Measurement Instruments

Step 6 Run a Simulation

INTRODUCTION TO XILINX

Xilinx ISE

is a software tool produced by Xilinx for synthesis and analysis

of HDL designs which enables the developer to synthesize (compile) their designs

perform timing analysis examine RTL diagrams simulate a designs reaction to different

stimuli and configure the target device with the programmer

ModelSim is a verification and simulation tool for VHDL Verilog System Verilog

and mixed language designs

EC amp LD LAB - 10CSL38 2015 - 16


INTRODUCTION TO VHDL

HDL (Hardware Description Language) based design has established itself as the

modern approach to design of digital systems with VHDL (VHSIC Hardware Description

Language) and Verilog HDL being the two dominant HDLs Numerous universities thus

introduce their students to VHDL (or Verilog) The problem is that VHDL is complex due to

its generality Introducing students to the language first and then showing them how to

design digital systems with the language tends to confuse students The language issues tend

to distract them from the understanding of digital components And the synthesis subset

issues of the language add to the confusion

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware

Description Language In the mid-1980‟s the US Department of Defense and the IEEE

sponsored the development of this hardware description language with the goal to develop

very high-speed integrated circuit It has become now one of industry‟s standard languages

used to describe digital systems The other widely used hardware description language is

Verilog Both are powerful languages that allow you to describe and simulate complex digital

systems A third HDL language is ABEL (Advanced Boolean Equation Language) which

was specifically designed for Programmable Logic Devices (PLD) ABEL is less powerful

than the other two languages and is less popular in industry This tutorial deals with VHDL

as described by the IEEE standard 1076-1993

Although these languages look similar as conventional programming languages there

are some important differences A hardware description language is inherently parallel ie

commands which correspond to logic gates are executed (computed) in parallel as soon as a

new input arrives A HDL program mimics the behavior of a physical usually digital system

It also allows incorporation of timing specifications (gate delays) as well as to describe a

system as an interconnection of different components

EC amp LD LAB - 10CSL38 2015 - 16



CLIPPERS amp CLAMPERS

AIM

a Design and construct a suitable circuit and demonstrate the working of positive

clippers double-ended clippers and positive clampers using diodes

b Demonstrate the working of the above circuits using a simulation package

Apparatus


1 Diode BY 127 02

2 Resistors 1 K 100 K 01 01

3 Capacitor 1f 01

4 Functional Generator 01

5 Multi-meter CRO amp Probes 01 Set

6 Base Board and Wires 01 Set

CLIPPERS

Theory

Clipper is a circuit which removes a part of the input signal with out distorting the

remaining part of the waveform It may be positive or negative part of an input signal

Clipping circuits is also known as limiters amplitude selectors or slicers This kind of

processing is useful for signal shaping circuit protection and communication

Based on working clippers circuits are classified as

1 Positive clipper one which removes positive part of signal

2 Negative clipper one which removes negative part of signal

Based on diode arrangement clipper circuit are classified as

1 Series Clipper

2 Shunt Clipper

EC amp LD LAB - 10CSL38 2015 - 16




EC amp LD LAB - 10CSL38 2015 - 16


Procedure






the waveforms




Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Shunt positive

(without biasing)

2 Shunt positive

(with biasing)

3 Shunt positive

(with biasing)

4 Double ended

(without biasing)

5 Double ended

(with biasing)

6 Double ended

(with biasing)

EC amp LD LAB - 10CSL38 2015 - 16


2 Clampers





Design

RL Cgtgt T


Let R1 = 100 K C = 1 f

EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory








a Positive clampers

b Negative clampers














EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




EC amp LD LAB - 10CSL38 2015 - 16


Procedure






the waveforms




Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Shunt positive

(without biasing)

2 Shunt positive

(with biasing)

3 Shunt positive

(with biasing)

4 Double ended

(without biasing)

5 Double ended

(with biasing)

6 Double ended

(with biasing)

EC amp LD LAB - 10CSL38 2015 - 16


2 Clampers





Design

RL Cgtgt T


Let R1 = 100 K C = 1 f

EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory








a Positive clampers

b Negative clampers














EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Procedure






the waveforms




Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Shunt positive

(without biasing)

2 Shunt positive

(with biasing)

3 Shunt positive

(with biasing)

4 Double ended

(without biasing)

5 Double ended

(with biasing)

6 Double ended

(with biasing)

EC amp LD LAB - 10CSL38 2015 - 16


2 Clampers





Design

RL Cgtgt T


Let R1 = 100 K C = 1 f

EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory








a Positive clampers

b Negative clampers














EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


2 Clampers





Design

RL Cgtgt T


Let R1 = 100 K C = 1 f

EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory








a Positive clampers

b Negative clampers














EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


CLAMPERS

Theory








a Positive clampers

b Negative clampers














EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Procedure





on the CRO


Results

SL


Output (Practical)

Hardware

Output (Practical)

Software Remarks

1 Positive


2 Negative


EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



( a )


VCC = 2VCE = 2 X 5 = 10 V



IB = IC = 2 mA 100 = 20 A

RE = 1 ( 2 m + 20 ) = 495

Choose RE = 470





Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR2 ( IR1 ndash IB ) = 16 ( 200 A - 20 A )

R2 = 88 k Choose R2 = 82 k


R1 = 42 K Choose R1 = 47 k

XCE lt lt RE

XCE = RE 10

1 ( 2 f CE ) = 470 10 Let f = 100 Hz



C

B

E

SL100

or

CL100

EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus

Theory




















4 DRB 01



EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Tabular Column

Vi = mV


Simulation Results


EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Procedure













semi log sheet
















[Note Zo lt Rd]

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

Frequency response

(b)


(c) (d)

EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16





Results







EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



Tabular Column


VDS1 = _____________ V VDS1 = _____________ V


G D S

IRF 540

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 MOSFET ( IRF 540 ) - 1


3 Multimeter - 1


Theory










insulated gate FET

EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


ID

VGS

ID in mA

VDS1

VDS2

Tabular Column


VGS1 = _____________ V VGS1 = _____________ V


Ideal Graph


ID in mA

VT VGS in V

VDS2 gt VDS1

VDS in V

VGS1

VGS2 ID VDS

VGS2 gt VGS1



EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Procedure













Results



EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16









EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



CMOS INVERTER














low voltage GND





EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16





EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



SCHMITT TRIGGER

AIM





Apparatus


1 OP AMP 741 1






Procedure









LTP level

EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Formulas to be used

R 1 2

1 2 1 2

V R RUTP= +V

satR +R R +R



R 1 1 2 2R

1 2 1 1

V R R +R RUTP + LTP = 4 = 2 V = 2 = 2 1+

R +R R R

[eqn 1]

22

1 2

1 2 1


[eqn 2]






R 1

1 2


R +R [eqn 3]

Eqn 3 = 0

22

1 2

1 2 1


[eqn 4]



R 1 2

1 2 1 2

V R RLTP= - V

satR +R R +R

EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Results

1 With Reference

2 Without Reference





EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



Design

Given f0 = 1 Khz


R2 = 116 R1


To calculate R


1f0


EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




AIM






Apparatus


1 IC microA 741 01



4 Diode BY 127 01

5 POT or DRB 20k 01

THEORY






PROCEDURE





Result


EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Circuit Diagram


Design




But d

tc

tT and any

dt

ct

ct

dutycycle

Then T

ct

D

1msec

ct

06D

06msecc

t and 04msecd

t

From (2) CR06904 2


R2 = 59k


From (1) 06= 069 R1 C

RA = 86k

EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




AIM



Apparatus


1 555 timer -- 1

2 Power Supply -- -




Procedure






Result


EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Function Table


A2 A1 A0 EN Q Q



















EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



MULTIPLEXER

AIM



Apparatus





Theory













EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



f(w x y z) = sum (2457101114) + sum‟ d (89121315)


Decimal

Value

Inputs MEV Output

F

Entry in

MEV Map

Comments

W X Y Z

0 0 0 0 0 0 0 (D0)



2 0 0 1 0 1

Z (D1)



4 0 1 0 0 1 1 (D2)


enter 1 5 0 1 0 1 1


7 0 1 1 1 1


9 1 0 0 1 X

10 1 0 1 0 1 1 (D5)


enter 1 11 1 0 1 1 1


13 1 1 0 1 X

14 1 1 1 0 1 1 (D7)


enter 1 15 1 1 1 1 X

EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Procedure





EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Sample Programs


Entity And1 is


C OUT STD_LOGIC)

End And1


Begin

C lt= A AND B

End Behavioral


the output





End Half_adder


Begin

SUM lt= A XOR B

CARRY lt= A AND B

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



verify its working

Entity MUX is



Z OUT STD_LOGIC)

End MUX


Begin


Begin

Case sel is










End Case

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Circuit diagram


J K Clk Q Q






EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




AIM


Apparatus






Theory














Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


PIN DETAILS OF ICs

EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity DFF is


Q OUT STD_LOGIC)

End DFF


Begin

Process (CLK)

Begin


Q lt= D

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16






0 0 0 0 0 1 X 0 X 0 X 1

0 0 1 0 1 0 X 0 X 1 1 X

0 1 0 0 1 1 X 0 0 X X 1

0 1 1 1 0 0 X 1 1 X 1 X

1 0 0 1 0 1 0 X X 0 X 1

1 0 1 1 1 0 0 X X 1 1 X

1 1 0 1 1 1 0 X 0 X X 1

1 1 1 0 0 0 1 X 1 X 1 X

Design

EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



SYNCHRONOUS COUNTER

AIM



Apparatus







Theory



to a clock signal










Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



its working

Entity Mod8 is



End Mod8


Begin

Process (CLK)

Begin



Q lt= ldquo000rdquo

Else Q lt= Q + 1

End if

End if

End Process

End Behavioral

EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Pin diagram

OPERATION OF 7495





loading of data

STATE TABLE

Ring counter

Clk QA QB QC QD

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 1 0 0 0

6 Repeats

EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



RING COUNTER

AIM


working

Apparatus


1 IC 7495 7404 11


3 Patch cords - 20

Theory















Procedure





EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




Clk QA QB QC QD

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

8 0 0 0 0

9 1 0 0 0

10 Repeats

EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16




Entity Johnson is



End Johnson


Begin

Process (CLK)

Begin


Q (0) lt= NOT Q (3)


Q (i + 1) lt= Q (i)

End Loop

End if

End Process

End Behavioral

Result

EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


PIN DIAGRAM

FUNCTIONAL TABLE

INPUTS OUTPUTS


H H L X L L L L

H H X L L L L L

L X H H H L L H

X L H H H L L H

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



DECADE COUNTER

AIM



Apparatus





Theory













Procedure





Result

EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



Truth table

Clk QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

REPEATS

EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


WORKSHEET

EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


FORMULA

3

D82

D41

D20

D16

refV

R

fR

0V


voltage

Tabulation


D3 D2 D1 D0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Circuit Diagram

Calculation



V2561016

1018041201

16

5

K1

K2V0


EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



R-2R LADDER NETWORK

AIM



Apparatus




3 Trainer kit --- 1



Theory




each input point

Procedure




Result

EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


REFERENCES


VHDL 2nd



Vranesic TMH 2006






Edition


9th

Edition



Applications 7th





2010

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash A

VIVA QUESTIONS




















transistor


6 Define




















EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16







4 Define duty cycle



MULTIPLEXER







FLIP FLOPS







7 What is a counter
















R-2R LADDER








EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash B

COMPONENT DETAILS

1 DIODE BY 127







symbol



1000mV = 1V)



2 TRANSISTOR








EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


Types of transistor





3 MOSFET


Testing a MOSFET






lead








turned-on




device

IR F540

G D S

EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



Where



Vout output



5 555 TIMER

EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16


ANNEXURE ndash C











Steps to Proceed








Xilinx ISE







EC amp LD LAB - 10CSL38 2015 - 16



























EC amp LD LAB - 10CSL38 2015 - 16



























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