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AN1692APPLICATION NOTE®

STIL02 DEVICE USED IN DISCONTINOUSPOWER FACTOR CORRECTION

March 2003 - Ed: 1

B. PERON

CONTENT

n INTRODUCTIONn DESIGN SPECIFICATIONn FUNCTIONAL DESCRIPTIONn SELECTION OF THE POWER COMPONENTSn STIL DRIVER CIRCUITn CONCLUSIONn APPENDIX 1: PART LIST OF THE

DEMOBOARDn APPENDIX 2: SCHEMATIC OF THE

DEMOBOARDn APPENDIX 3: PRINTED CIRCUIT BOARD

LAYOUTn REFERENCE

1. INTRODUCTION

During the cold start of the off-line converter, highcurrent due to the charging of the bulk capacitorcan increase to several times the nominal currentof the system. This inrush current can damagedevices in series such as the fuse and the bridgediodes. Moreover it induces a voltage drop(brownout) on the AC line that can affect theoperation of any equipment connected on thesame line.

Several circuits can reduce this inrush current,each one presenting different benefits, but alsosome drawbacks. The technical article referencedTA301 [3] describes and compares thesecommon solutions. It also introduces the STILcomponent developed in the ASD™ (Applicationspecific Device) planar technology developed bySTMicroelectronics. The STIL substantiallyimproves the inrush current function.

While AN1600 [2] gives methods andrecommendations to implement this component,this document presents a practical design with theSTIL used in a Power Factor Corrector working inthe discontinuous (critical) mode.

The functional description, the choice of the powerfront-end components and the STIL driver circuitare described. The results obtained with thedemoboard V1.0 are presented, including thecapability to manage the AC line brownout as wellas compatibility of the STIL with the IEC61000-4-5.

2. DESIGN SPECIFICATIONS

The target specifications are as follows:

n PFC working in the critical moden Maximum output power Pout(max) = 85Wn Universal mains input AC voltage Vin(RMS) =

85VRMS to 264Vrms, 60/50Hzn DC regulated output voltage Vout = 400Vn Peak inrush current lower than 30A at the nomi-

nal mains voltage and at Tamb = 25°Cn Time responsiveness of the brownout AC line

test lower than 20msn IEC61000-4-5 compatibility up to 2kV

To meet these specifications, we used a dedicatedPFC controller; the L6561 [4] fromSTMicroelectronics. For a detailed explanation onthe controller operation, the reader may refer to thesection of the datasheet of the L6561corresponding to the power factor corrector.

In order to determine the components around theSTIL, the application note AN1600 and thedatasheet of the STIL02 [1] were used asreferences.

AN1692 - APPLICATION NOTE

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3. FUNCTIONAL DESCRIPTION

The component values are given in the nextsection. The figure 8 at the end of this documentgives the complete schematic of the demoboardwith the PFC where the STIL component has beenimplemented.Figure 1 below shows a front-end circuit, whichhas been simplified for a better understanding.

DriverSTIL02R1

R2

R4 (NTC)Pt1

Pt2

BRIDGE

Fig. 1: STIL concept implemented in the PFC.

INRUSH1

INRUSH2

V8-V0

START UP TIME OF TH

VOUT=300V

Fig. 2: Inrush current at Vin = 230VRMS.

At cold start, the two unidirectional power switchesof the STIL are opened. The inrush current flowsthrough the diodes of the bridge and the externalinrush power impedance R4. As soon as the PFCconverter turns on, the auxiliary power supplycoupled with the main inductor, provides theenergy required to close the two power switches ofthe STIL.Thus, in the steady state, the mains current isrectified by the STIL and the two bottom bridgediodes.It can be noted that the inrush current can belimited even during the AC line brownout. Actually,when the current from the mains disappears,capacitor C3 is not recharged, and so, its voltagedecreases. As soon as the pilot current becomeslower than the triggering current value, the internalpower switches of the STIL open. Thus, when thepower mains reappears, the same cold start phasereoccurs and then the inrush current is reduced bythe R4 resistor. In this paper, this phase will called"management of the AC line brownout".

4. SELECTION OF THE POWER COMPONENTS

4.1. Power NTC (R 4)

The inrush current function made with the HalfControlled Rectified Bridge (HCRB) configuration

(see: TA301) allows a NTC to be used to limit thepeak current. This NTC is shorted by the STILduring the steady state. Thus, its internaltemperature does not rise and, the inrush currentcan be limited even during brownout phases (nothermal constant). Moreover, the NTC is moresuitable than the power resistor because its powerdensity is higher.However, the ambient temperature must remainlow enough to keep its equivalent resistance valuesufficiently high to limit the inrush current.The peak current value at the cold start can becalculated by:

RV

Iin RMS

peak

4

2=

⋅(max)( )

Where:

V(mains)(max) = 230VRMS; Ipeak = 30A

Then : R4 = 10 ΩThe figure 2 below shows the peak currentmeasured in the demo-board with a power NTC of10 Ω at Tamb = 25°C.

These waveforms are measured using linksinrush1 and inrush 2 connected in the demo-boardPCB (see figure 8).

4.2. STIL device selection

Average output current (Iout(av))

With an active boost PFC, the current flowingthrough the power switches of the STIL can beconsidered as a sinusoidal waveform. With thedesign specification, we can calculate:

IP

Vout AV

out

in RMS

( )(max)(max)

( )(min)

=⋅ ⋅⋅ ⋅

2 2

π η


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Iout(AV)(max) = 1.12A, with an efficiency η = 0.8

The STIL02 is suitable for the demo-board [1]since it is specified for an average current equal to2A. The STIL04 would also fit with its averagecurrent of 4A, but it would be oversized.

The maximum power losses can be evaluatedusing the method highlighted in application noteAN1600. Therefore a Iout(peak) = 1.76A.

Typ. value@ Tj=150°C

Max. value@ Tj=150°C

VT0 0.65V 0.78V

Rd 0.095Ω 0.112Ω

The total losses can be calculated by:

( )P V I

R Itot T out AV

d out AV= ⋅ +⋅ ⋅

0

2

8( )

( ) π

Typ. value@ Tj=150°C

Max. value@ Tj=150°C

Ptot 0.875W 1.05W

Thus, the heatsink of the STIL can be chosen inorder to keep within the specified junctiontemperature range.

RT T

Pth j amb

j amb

tot

( )max

(max)

− ≤−

Then: Rth(c-amb) ≤ 119°C/W

Where: Tjmax=150°C, Tamb=25°C, Ptot(max)=1.05W

As a matter of fact, no heatsink is necessary on thedemoboard because the intrinsic thermalresistance of the STIL package is lower than119°C/W (Rth(j-amb) = 60°C/W).

Repetitive peak forward voltage (VDout)

In the steady state, the power switches of the STILare always closed or blocked by the reversevoltage. However, at cold start or during the ACline brownout, a forward voltage appears acrossthe STIL. The maximum forward voltage value(VD) is given by the oscillations made by the mainspeak voltage rise step to the mechanical bouncesassociated to the inductor and capacitor of themains filter.Even in the worst case (Vin(max) = ⋅264 2 and with0.1 for the damping factor), the maximumrepetitive forward voltage (VDout) of 700V at Tj=0°Ccannot be reached (see the datasheet ).

V2-V3

VOUT=400V

V1-V3

VMAINS=300VVL-VOUT

VN-VOUT

Fig. 3: FTOa and surge current at 2kV.

Repetitive peak reverse voltage (VROUT)

In normal operation, the two bottom diodes of thebridge and the two unidirectional current switchesof the STIL rectify the AC line current.

In order to estimate the repetitive peak reversevoltage (VRRM), the first pass comes from thereverse voltage during the steady state (VR =400V). Nevertheless, for a short time, a fasttransient voltage (FTOa) occurs across the STILwhich can be higher than the nominal statevoltage. In fact, this voltage is given byIEC61000-4-5 standard applied to the front-endcircuit in the "a" configuration (see AN1600) and itis defined by:

FTOa V V R ICout Cout Eq surgeI surge= + + ⋅∆ ( ) ( )( )

Thus, we can check that the FTOa voltage acrossthe STIL is lower that VRout specified in thedatasheet (700V@Tj = 0°C).

Table 1 gives the FTOa voltage versus the chokewave level and Figure 3 shows the correspondingshape at 2kV. The STIL02 is compatible with thistransient voltage since the FTOa is lower thanVRout.

However, if the FTOa tends towards VRout duringthis test (configuration "a"), a varistor isrecommended before the mains filter in order toreduce the surge current flowing though REQ andthe bulk capacitor, as shown by the applicationnote AN1600.


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Over-current stress

Over-current stress can occur in two cases:

n During the AC line brownout.n During a lighting surge (IEC61000-4-5).

Over-current due to the AC line brownout

The PFC and the adapted auxiliary power supplyas defined by figure 1, the AC line brownout ismanaged and then no over-current occurs in theSTIL as show figure 6 and figure 7.

Over-current due to a lighting surge

As for the fast transient voltage (FTOa), themaximum over-current flowing through the STILoccurs during the "a" configuration (see AN1600).Its peak amplitude depends on the surroundingcomponents such as the mains filter and the shockwave level.

In order to check if the peak current valuecorresponding to 2kV is compatible with the STILcurrent specified (500A for 8/20µs shape-STIL02),we would slowly increase the amplitude of thespike voltage of the combine waveform up toobtain 500A. Table 1 below gives the peak currentmeasured flowing thought the STIL in thedemoboard versus the shock wave level.

Table 1: FTOa voltage and peak current versuschoke wave level.

SpikeVoltage 0.5kV 1kV 1.5kV 2kV

Ipeak 23A 120A 210A 300A

FTOa 441V 553V 611V 694V

It should be noted that the measured current doesnot exceed 500A, even at 2kV for the spikevoltage.

Therefore, the STIL02 is compatible with level(2KV) since the peak current measured at 300A islower than the guaranteed 500A and the VRout

voltage is higher than the FTOa measurement offigure 3.

4.3. Bridge diodes

Average output current (Iout(av))

Only the two bottom bridge diodes work during thesteady state. Thus, the average current is thesame as for the STIL, that is to say Iout(av)(max) =1.12A. Therefore, the bridge diodes must have an

average current higher than 1.12A. For example,4A bridge diodes are suitable for the demoboard.

Over-current stress

The bridge does not carry significant inrush currentsince it is limited by the NTC at the cold start andduring the AC line brownout. Thus, the bridgediodes must only withstand the inrush current of30A during ¼ of the mains period (5ms),worst-case scenario. Therefore, parameter I²t ofthe bridge must be higher than 2.25 A²s. The diodebridges used in the demoboard are compatiblesince their I²t parameters (60A²s) are higher than2.25A²s.

However, during the lighting surge, the currentcorresponding to the "a" configuration(worst-case) also flows through the two bottombridge diodes. Therefore, the bridge must alsowithstand these surge currents.

Although, the bridge is not specified for thisparameter, the I²t parameter can be used tocompare the bridge with the STIL since this onehas been guaranteed against such an over-currentstress.

Thus bridges diodes with an I²t value higher thanthe STIL (21A²s) can be used.

Repetitive peak reverse voltage (VRRM)

In the "b" configuration test (see AN1600), thepower switches integrated in the STIL turn on aftera short time tr in spite of a pilot constant currentfrom the auxiliary power supply. Therefore, the twopower switches remain opened during a short timeand then, a voltage called Vddyn rises quicklyacross the silicon components that should beclosed. Thus, this voltage is added to the outputvoltage (Vcout) to create a second fast transientvoltage FTOb that is applied across the bridgediodes.

Other experimental measurements must beperformed to check that this voltage rating of thebridge VRRM-BR remains above FTOb.

The figure 4 shows this fast transient voltage in thedemo board at 2kV.


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V0-V2

FTOB=500VV3-V2

VMAINS=300V

VGND-VL

VOUT-VL

VDDYN=160V

Fig. 4: FTOb in the "b" configutation at 2kV.

In the demoboard, FTOa is higher than FTOb.

Therefore, the bridge diodes used are compatiblewith 2kV since the I²t parameter is higher than theI²t guaranteed by the STIL and the bridge VRRM-BR

voltage (800V) is higher than the FTOa measured(694V) as shown on figure 3.

The same rationale should be applied for choosinganother diode bridge.

4.4. Input fuse

The input fuse must be opened only during severecurrent overloads, without browning out during thetransient inrush current, the normal operation(85VRMS / 85W) and during the lighting surgedefined by the standard (300A/8/20µs). The fusechosen for this demoboard has a continuouscurrent rating of 6.3A.

4.5. Mains filter

In the discontinuous mode, the EMI filter is placedbetween the mains and the PFC circuit. Thedesign of this filter is not described here, but werecommend to plug the differential filter without X2and Y2 capacitors just before the STIL and thebridge diode as shown on figure 8 (see AN1600).

Figure 5 shows performance of this mains filter forthe maximum output power. The limit is defined bythe EN55022 standard.

NAME:STIL02CN

Fig. 5: Average measurements are compatiblewith the EN55022 standard.

5. STIL DRIVER CIRCUIT

The schematic driver circuit proposed in figure 1provides the constant output voltage dedicated forthe internal STIL driver. It remains constant evenwhen the input mains voltage changes. Thischaracteristic allows the constant current for thepilot driver of the STIL to be provided whatever thevalue of the mains voltage.

Moreover, It offers the possibility to manage theAC line cycling or the brownout test. Actually, assoon as, the mains voltage disappears, the currentvariation in the main coil disappears too. Thereforethe magnetic flux and the voltage across thewinding drop and the capacitor C3 voltage drops.When it becomes lower than the triggering pilotcurrent of the STIL, the power switches turn off.The description of the driver circuit is highlighted inapplication note AN1600. In order to define thevalue of the PFC environmental components, wealso suggest to refer to the L6561 application note.Thus, with the datasheet of the STIL and thedesign specification, we obtain:

n Vout = 400Vn Vin(min) = 85VRMS x 2n Pout(max) = 85Wn Efficiency = 0.8n L = 850µHn n1 = 90 turnsn t(dead) = 1ms (measured)n Fs(max) = 350kHz (measured)n Ipt1(max) = Ipt2(max) = 10mA @ Tj = 0°Cn Vpt(max) = VD(pt1) = 1Vn VD1 = VD2 = 0.7V


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Calculation of n2

With the rule given in application note AN1600, wecan determine the number of the auxiliarywindings for the coil:

n nV

k V

kV

out

ptD2

11

8 2

12= ⋅

⋅ ⋅−

+ ⋅

. (max)

With k = 5 to reduce the ripple voltage across thecapacitor C3 then:

n2 2 62= .

In the EDT core, it is possible to realize either ½ or1 turn. Therefore, we can take 3 turns.

Calculation of C1 and C2 capacitances values

This PFC works on the universal mains, then:

( )C or C

L k I I P

V

pt pt out

in

1 2

1 24≥

⋅ ⋅ ⋅ + ⋅(max) (max) (max)

(min)

2 2

1

12⋅ ⋅ ⋅ −

η n

nV Vout D

C1 = C2 = 210nF

However, due to the dispersion of this kind ofcapacitor (+/-20%), we can take C1 = C2 = 330nF.

Calculation of R3

The R3 resistance value should be low enough toguarantee the charge of capacitors C1 and C2 forthe long and the short duty cycles even at themaximal switching frequency Fs(max). The basicmathematical expression of the frequency for thetransient mode PFC gives an infinite number ofswitching frequencies at Vin(min) and at Pout(min).

In practice, of course it goes high but, for lowoutput power and near the zero mains voltage, itreaches a limit Fs(max). This limit is defined byresonant phase between the intrinsic siliconcapacitors and the mains coil.

Ultimately, Fs(max) is defined by measurement onthe demoboard in the previous conditions.

At 10W and near zero of the sinusoid mains, weget a Fs(max) of 350kHz, which led to the choice ofR3 as follows:

RC FS pratical

3

1

0 13

≤⋅ ⋅

.

(max)( )

Therefore R3 = 0.33 Ω

Calculation of R1 & R2

The rule given in application note AN1600 allowsR1 and R2 to be calculated.

R R

nn

V Vk

Vout D pt

2 1

2

1

12

4 11

2

= ≤

⋅ ⋅ − ⋅

⋅ −

− ⋅ (max)

(max) (max)I Ipt pt1 2+

R1 = R2 = 854 Ω

In the E12 family, we can take: R1 = R2 = 820 Ω

Calculation of C3

C3 provides the energy required when the PFCdoes not work during a short period of time (about1ms) near the zero voltage of the sinusoid (seeAN1600).

( )C

I I t k

nn

V V

pt pt dead

out D

3

1 2

2

1

12

≥+ ⋅ ⋅

⋅ − ⋅

(max) (max)

− C 1

2

C F3 8 2> µ.

Most power supply specifications require that theinrush current limitation remains active after abrownout event. This means that the switches ofthe STIL should be opened when the mainscurrent recovers.

Thanks to the circuit of figure 1, when the mainsdisappear, the voltage across the auxiliary powersupply drops down and the driver circuit turns off.

The bulk capacitor C3 must be low enough to openthe switches before the end of the brownoutperiod. This condition is given for t(brownout) = 20ms(see the design specification):

Ct

RCbrownout

3

1

12

3 2≤

⋅⋅

−( )

( ); C F3 16< µ

A capacitor C3 equal to 10µF is appropriate torespect the t(dead) and t(brownout) conditions.

The figure 6 shows voltage and current waveformsfor the brownout test of 20ms. The voltage acrossC3 falls down to zero before the mains voltagereappears.


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INRUSH2

INRUSH1

IOUT

I(NTC)

VPEAK(MAINS)=311V

STIL ON

Fig. 6: The driver circuit manages the brownoutsince the STIL becomes opened before 20msbrownout time.

INRUSH2

INRUSH1

IOUT

I(NTC)

VPEAK(MAINS)=311V

STIL ON

Fig. 7: Limitation of the inrush current for thebrownout test of 50ms.

However, up to the "critical time" (see figure 6),even if the driver circuit manages the brownout fora time equal to 20ms, there is no risk of inrushcurrent (critical time > t(brownout)). Actually, the bulkvoltage capacitor remains higher than the peakmains voltage and therefore the STIL is alwaysopened (OFF).

The figure 7 shows the waveform when thebrownout test time is higher than 30ms(t(brownout)>critical time). In this case, the inrushcurrent is actually reduced by the NTC.Nevertheless, the undocking of the ULVO of thePFC controller must be dimensioned for the criticaltime. This condition is given by the powerconsumption of the controller circuit and by thecapacitor defining its supply.

6. CONCLUSION

This paper describes a practical design of PFC inthe discontinous mode (critical mode) using aSTIL02 component. A demoboard highlights theperformance of this component and in particularthe compatibility to manage the brownout AC linecycling and the compatibility with the IEC1000-4-5standard.


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Name Value Power tol pakage

R1 820R 0.25 5% 1206

R2 820R 0.25 5% 1206

R3 0.33R 0.125 5% 1206

R4 10R NTC 9.5mm

R5 120k 0.25 5% 1206

R6 120k 0.25 5% 1206

R7 100R 0.25 5% 1206

R8 180k 0.125 1.00% 1206

R9 330k 0.125 1% 1206

R10 620k 0.25 2.00% 1206

R11 47k 0.25 5% 1206

R12 180k 0.125 1.00% 1206

R13 620k 0.25 2.00% 1206

R14 330k 0.125 1% 1206

R15 10R 0.25 5% 1206

R16 10k 0.25 5% 1206

R17 12k 0.25 1% 1206

R18 1.5R 0.25 5% 1206

R19 1.5R 0.25 5% 1206

R20 1.5R 0.25 5% 1206

R21 12k 0.25 1% 1206

R22 330R 0.125 1% 1206

R23 1.5R 0.25 5% 1206

C1 330nF / 1206 (X7R)

C2 330nF / 1206 (X7R)

C3 10µF / tantal

C4 15nF / 806 (X7R)

C5 1µF / 1206 (X7R)

C6 1µF / 400V

C7 68µF / chimical 450V

C8 22µF / tantal

C9 10nF / 806 (XR7)

C10 220nF / X2

C11 470nF / X2

C12 2.2nF Y2

C13 2.2nF Y2

C14 2.2nF Y2

C15 2.2nF Y2

APPENDIX 1: PART LIST OF THE DEMOBOARD


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Name Value Power tol pakage

D1 TMBAT49 Melf

D2 TMBAT49 Melf

D3 STTH1L06 DO-41

D4 TMBAT49 Melf

D5 S3M / SMC

D6 BZV55-C15 500mW SOD-80C

Bridge 4A/800V GBU

STIL STIL02-PL5 PL5

Fuse MCF03C 6.3A

supp fuse 5229

capot fuse 5201

M1 STP8NC50FP TO-220FP

IC1 L6561 minidip

TRANSFO1 transfo

Connect 2 inputs (+400V,0V)

Connect 3 inputs (mains(L1),Mains(L2),earth))

L5 1.17mH 1.17mH/1.2A

L6 PLA10A1821R7R02

heatsink 175-649 TO-220

9*Picot1 picot 2.8*0.8mm V0,V1,V2,V3,V4,V5,V6,V7,V8

10*Picot2 picot 6.3*0.8mm Inrush1,Inrush2,Inrush3,Iplt,Ivar

10*faston faston(1.5-2.5mm)

Transfo: Core THOMSON-CSF B1ET2910A (ETD 29x16x10mm) or equivalent (OREGA473201A8)

Gap 1.25mm for toatal primary inductance of 0.85mH

(n1) Primary 90T of litz wire 10x0.2mm:

Secondary (n1) 7T of 0.15mm;

Secondary (n2) 3T of 0.15mm

APPENDIX 1: PART LIST OF THE DEMOBOARD (con't)


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APPENDIX 2: SCHEMATIC OF THE DEMOBOARD

STIL demoboard (discontinuous PFC working in the critical mode).


11/12

APPENDIX 3: PRINTED CIRCUIT BOARD LAYOUT

Top view.

Bottom view.


12/12

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences ofuse of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted byimplication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject tochange without notice. This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 2003 STMicroelectronics - Printed in Italy - All rights reserved.

STMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany

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http://www.st.com

REFERENCES

[1] Datasheet STIL02-PL5 STMicroelectronics October 2002 Ed:3A

[2] Application note AN1600 STMicroelectronics: STIL: INRUSH CURRENT LIMITATION DEVICE FOROFF LINE POWER CONVERTER: October 2002 Ed:2 by B.PERON

[3] Technical article TA301 STMicroelectronics: STIL A NEW COMPONENT FAMILY FOR INRUSHCURRENT LIMITATION CIRCUIT (ICLC) October 2002 Ed:1 by I-BIMBAUD and B.PERON

[4] Datasheet L6561 STMicroelectronics October 2002

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