1

Zvi Kohavi and Niraj K. Jha

Testing of Combinational CircuitsTesting of Combinational Circuits

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Fault ModelsFault Models

Defects -> Faults -> Errors -> Failures

Fault models: modeling of multiple defects as single faults at a higher level of abstraction• Significantly reduces test derivation burden

• Faults may change internal logic values or voltage/current levels or the temporal behavior of the circuit

• Most common levels of fault abstraction: structural and switch-level

Structural fault models: these ensure that the interconnections in a given circuit structure are fault-free and able to carry both 0 and 1 signals

• Stuck-at fault model: a line is stuck-at 0 (s-a-0) or stuck-at 1 (s-a-1) if it remains fixed at a low or high voltage, respectively, assuming positive logic

– The most successful fault model in IC history

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Stuck-at Fault ModelStuck-at Fault ModelA stuck-at fault does not necessarily imply that the line is shorted to ground or power supply

• It may model many cuts or shorts internal or external to a logic gate• E.g., a cut on the stem of a fanout may result in a s-a-0 fault on all its fanout branches

– However, a cut on just one fanout branch may result in a s-a-0 fault on just that fanout branch– Hence, stuck-at faults on fanout stems and branches have to be considered separately

Types of stuck-at faults: • Single: occurs on only one line of the circuit• Multiple: simultaneously occurs on many lines• A circuit with k lines: has 2k single stuck-at faults, but 3k-1 multiple stuck-at faults• Thus, explicitly targeting multiple stuck-at faults is impractical

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Stuck-at Fault Model (Contd.)Stuck-at Fault Model (Contd.)

Example: Consider above circuit• To test for c1 s-a-0: one possible test vector is (1,1,0,1)

• Multiple (c1 s-a-0, c2 s-a-0, x3 s-a-1) fault: also detected by (1,1,0,1)

Stuck-at fault model also useful for future nanotechnologies: e.g., RTD- HFET based MOBILEs

x1x2

fx3x4 c2

c1

x1

Clk

T

w1 w2

-w3

f

x2

x3

1

2

3

4

5

6

8

7

Fault site

Equivalent fault

12345678

cutshort

x1 s-a-0

x1 s-a-0

x1 s-a-0

x3 s-a-0

x2 s-a-1

f s-a-0 or f s-a-1f s-a-1f s-a-0

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Switch-level Fault ModelsSwitch-level Fault Models

Switch-level fault models: deal with faults in transistors and interconnects in switch-level description of the circuit

Stuck-open fault model: refers to a permanently non-conducting transistor

Example: Defect d1 causes a stuck-open fault

• Exhaustive testing not enough: Test sequence {(0,0), (0,1), (1,0), (1,1)} does not give any error and hence does not detect d1

• Two-pattern tests needed to detect d1: {(0,0), (1,0)}

– Initialization vector: (0,0)

– Test vector: (1,0)

• Test sequence to detect all four stuck-open faults: {(0,0), (0,1), (0,0), (1,0)}

Q3

Vdd

x1

Vss

x2

Q1 Q2

Q4

xd1

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Stuck-on Fault ModelStuck-on Fault Model

Stuck-on fault model: refers to a permanently conducting transistor

Example: defect d2 causes a stuck-on fault

• Vector (1,1): in the presence of d2, Q1, Q2, and Q4 conduct, resulting in some intermediate value at the output

– If this maps to value 1 at the output: the fault is detected, else not

• Now suppose, a stuck-on fault in Q2 is present: only possible test is (1,0)

– In the presence of this fault: again Q1, Q2, and Q4 conduct

– This time, we need value 0 at the output for detection• Thus, by monitoring the output logic values: only one of these faults will be

detected

• IDDQ testing needed: measures the current drawn

Vdd

f

Vss

Q3 Q4

Q1

Q2

d2

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The Bridging Fault ModelThe Bridging Fault Model

Bridging faults: shorts between interconnects• BF: <c1,c2>

• For some vectors, conducting path from Vdd to Vss created: (1,1,0), (0,0,1), (0,1,1), (1,0,1)

• These vectors cause opposite logic values on c1 and c2 in the fault-free case: an intermediate voltage in the presence of the fault

• IDDQ testing needed

Types of BFs: feedback and non-feedbackVdd

x1c1

Vss

x2

Vdd

f

VssVdd

x3 c2

Vss

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Delay Fault ModelsDelay Fault Models

Delay faults: adversely impact the signal propagation delays, causing an incorrect value to be latched at the output

• Transition faults: defined for a logic gate whose output has a lumped delay fault that delays its 0 -> 1 or 1 -> 0 transition by more than the system clock period

• Path delay faults: when a path from a primary input to a circuit output is slow to propagate a 0 -> 1 or 1 -> 0 transition

• Path delay fault model more general of the two: models the cumulative effect of delay variations of gates and wires along the path

– However, because the number of paths in a circuit can be very large: it takes much more time to generate and apply tests

• Two-pattern tests needed: because of the need to propagate transitions

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Delay Fault Models (Contd.)Delay Fault Models (Contd.)

Example: In the circuit below• Path shown in bold: may have a path delay fault

• Consider G3: if a 0 -> 1 (1 -> 0) transition through every path going through G3 is significantly delayed, then G3 is said to have a slow-to-rise (slow-to-fall) transition fault

x1x2

f1G1

x5x4

c1

f2G5

G3

G2x3

x4G4

c3c2

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Structural TestingStructural Testing

Structural testing: detection of faults on the interconnects in the circuit structure

Test generation time: the time it takes to generate a test set for the targeted faults on a computer

Test application time: the time it takes to apply the test vectors to the circuit under test

Fault coverage: percentage of all targeted faults that are actually detected by the derived test set

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Path SensitizationPath Sensitization

Path sensitization: activating a path through the fault site from the primary inputs to a circuit output in order to detect the fault

Example: Sensitized path to detect A s-a-1• Other faults also detected: s-a-0 at m, n, and p and s-a-1 at q

• A s-a-0 detected by complementary values on the sensitized path• One-dimensional path sensitization: the above two vectors detect all single stuck-at faults along the path

Fault activation: at the fault site, assign a value complementary to the fault

Error propagation: Sensitize a path from the primary inputs to a circuit output through the fault site

Line justification or consistency: determine the primary input values that produce all the necessary signal values specified in above two steps

pm1

A nq

0010 1

01 01 0 1

0

1

1

1

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Path Sensitization (Contd.)Path Sensitization (Contd.)

Example: test for c1 s-a-1

• Assign 0 to c1

• Choose a path to be sensitized: through G5, G7, and G9

– Make side-inputs of G5 and G9 0

• Justify 0’s at lines c2 and c7 at the primary inputs

– To make c7 = 0: x3 = x4 = 0

– To make c2 = 0: (x1,x2) = (0,0) or (0,1) or (1,0)

– To make c1 = 0: x5 = 1

• Thus, test vector: (0,0,0,0,1)

• Other faults detected: c3 or c5 s-a-1, c6 or f2 or x5 s-a-0

x1x2

f1

f2

x3

x4c4

c3s-a-1

c6c5

x5c7

c1

c2

G1

G9

G8

G7G5

G6G4

G3

G2x

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ImplicationImplication

Implication: given the logic value on some line, determine the logic values uniquely implied at other lines• Backward and forward

Example: Implication of c7 = 0

• Backward: x3 = c4 = 0

• Forward: f1 = 0

Backtrack: Various path sensitization choices may exist: (G4,G6,G9), (G4,G6,G8)

• When one choice leads to a conflict: backtrack and choose another path

x1x2

f1

f2

x3

x4c4

c3s-a-1

c6c5

x5c7

c1

c2

G1

G9

G8

G7G5

G6G4

G3

G2x

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Fault CollapsingFault Collapsing

Fault collapsing: reduction of the list of faults that needs to be targeted without giving up fault coverage

Redundant (or untestable) fault: fault-free and faulty truth tables are identical

Fully testable (or irredundant) circuits: in which all single stuck-at faults are testable

Fault equivalence: two faults are equivalent if their truth tables are identical• For an n-input primitive gate: n+1 stuck-at faults are equivalent

– All s-a-0 faults at the inputs and output of an AND gate

– All s-a-1 faults at the inputs and output of an OR gate

– All s-a-0 faults at the inputs and s-a-1 fault at the output of a NAND gate

– All s-a-1 faults at the inputs and s-a-0 fault at the output of a NOR gate

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Fault Collapsing (Contd.)Fault Collapsing (Contd.)

Equivalence fault collapsing: reduces 2n+2 single stuck-at faults to n+2• AND gate: n+1 s-a-1 faults and any s-a-0 fault on the n+1 lines

Fault dominance: Fault x dominates fault y if the set of all vectors that detect x is a superset of the set of all vectors that detect y

Dominance fault collapsing: removal of the dominating fault from the fault list• AND gate with inputs a, b, and output f: Tf/1 = {(0,0), (0,1), (1,0)}, Ta/1 = {(0,1)} and

Tb/1 = {(1,0)}

• Thus, f s-a-1 dominates a s-a-1 or b s-a-1• Dominance fault collapsing reduces the fault list to size n+1 for an n-input gate

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Fault Collapsing TheoremFault Collapsing Theorem

Theorem 1: A test set that detects all single stuck-at faults at all primary inputs and fanout branches of an irredundant combinational circuit detects all single stuck-at faults in it

• Primary inputs and fanout branches: checkpoints

Corollary: A test set that detects all single stuck-at faults at all primary inputs of a fanout-free combinational circuit detects all single stuck-at faults in it

Example: Checkpoints: x1, x2, x3, x4, c1, c2, c4, c5

• No. of faults reduces from 24 to 16• Further reduction:

– x1 s-a-0 and c1 s-a-0 equivalent: remove one

– x3 s-a-0 and c2 s-a-0 equivalent: remove one

– x4 s-a-0 and c5 s-a-0 equivalent: remove one

– c4 s-a-0 equivalent to c3 s-a-0 which dominates

x1 s-a-1 and c1 s-a-1: remove c4 s-a-0

– No. of faults further reduced from 16 to 12c3x1

x3

x2

f2

f1

x4

c2

c5

c4

c1

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DD-algorithm-algorithm

D-algorithm: generalization of the one-dimensional path sensitization• Can simultaneously sensitize multiple paths when necessary• Error symbol D: composite value that represents a 1 on a line in the fault-free circuit and 0

in the faulty circuit• D’: denotes the complementary situation• Five-valued algebra: {0,1, ,D,D’}• D and D’ behave like any Boolean variable:

– D + 0 = D, DD’ = 0, D + D’ = 1, DD = D + D = D, etc.

Singular cover: compacted truth table• Rows: singular cubes

Propagation D-cubes: minimal conditions for error propagation through a gate

a

(a) NAND gate.

b f

0 0 1a b f

1 1 0 1 0 1 0 1 1

D 1 Da b f

D D D 1 D D

a b f

(d) Propagation D-cubes.

(c) Singular cover.(b) Truth table.

0 1

00

1 11

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DD-intersection-intersection

D-intersection: process of combining different cubes using following rules

• D-intersection of cubes C1 and C2:

– Same value in each position where C1 and C2 have identical values

– If the value is unknown in one cube: it denotes the value of the other cube in that position

– If C1 and C2 have known, but different, values in any position: their intersection is null, i.e., leads to a conflict

Example: Let C1 = 0 1 D, C2 = 1 D’ D, and C3 = 0 0 D’ 1

• C1 C2 = 0 1 D’ D

• C1 C3 = null

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Primitive Primitive DD-cube of a Fault (PDCF) and -cube of a Fault (PDCF) and Test CubeTest Cube

PDCF: minimal condition for fault detection

Example: for a NAND gate• 1 1 D’ is a PDCF for output f s-a-1• 0 D and 0 D are PDCFs for f s-a-0

Test cube: collection of all circuit signals set to a particular value from the five-valued algebra in order to derive a test vector

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DD-algorithm Steps-algorithm Steps

1. PDCF selection: select a PDCF for the targeted fault as the initial test cube and place the gate output with D or D’ on the D-frontier

2. Implication: perform backward and forward implication of the values assigned in Step 1. In case of conflict, backtrack

3. D-drive: intersect current test cube with a propagation D-cube of a gate whose input is on the D-frontier. Backtrack when necessary

4. Implication of D-drive: perform implication of the values assigned in Step 3. Repeat D-drive and its implication until an error signal reaches a circuit output

5. Line justification: For any gate G whose output is specified as 1 or 0, but inputs are not yet justified, perform line justification by intersecting the current test cube with a singular test cube of G

6. Implication of line justification: perform implication of the values assigned in Step 5. Repeat line justification and its implication until all specified values have been justified. Backtrack as necessary

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DD-algorithm Example-algorithm Example

Example: derive a test vector for the s-a-0 fault shown

c3

x1

x3

x2

s-a-0

f

G1

c2

c1

G3G4

G2

x

c4

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IIDDQDDQ Testing Testing

IDDQ testing: detection of faults through supply current monitoring

• Specially suited to CMOS where quiescent supply current is normally low• Error effects no longer have to be propagated to circuit outputs

– Faults just have to be activated

Test generation for bridging faults (BFs): target BFs between two nodes only• Since, even if a BF involves multiple nodes, activating a BF between any two of these nodes will activate a path

from Vdd to Vss

• In absence of layout information: consider all two-node BFs • When layout given: consider two-node BFs on adjacent nodes only

Conditions for detecting BFs: let P(r) denote the value of node r on application of P to the fault-free circuit• To detect non-feedback BF <r1,r2>: P(r1) and P(r2) must have opposite values

– This is an optimistic condition for detecting a feedback BF

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Fault Collapsing: First MethodFault Collapsing: First Method

1. Suppose for every input vector P: P(r1) = P(r2)

• Then <r1,r2> is redundant

2. If set of vectors T detects BFs between r1 and nodes in set R:

• Then T will also detect the BFs between r2 and nodes in R

• Hence, every BF involving r2 can be replaced with a corresponding BF involving r1

Example: Node c1 is the root of a tree of inverters and buffers

• Since P(c1) = P(c4) = P(c5) = P(c6) and P(c2) = P(c3) for every P:

– Just consider <c1,c2> and ignore BFs involving nodes c3, c4, c5, c6 among themselves and with other nodes

c1

x5

c4

c3

c2 x4

f3

x3

x2

x1 f2

f1c5

c6

c7

c8 G2

G1

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Fault Collapsing: Second MethodFault Collapsing: Second Method

Consider a set of nodes S s.t. each node in S has the same fanin nodes and realizes the same function:

• Then a BF between any pair of nodes in S is redundant

Example: condition satisfied for f1 and f2

• Thus, only BFs involving either f1 or f2, but not both, need to be targeted

• Similarly, BFs involving internal nodes of either G1 or G2, but not both, need to be targeted

c1

x5

c4

c3

c2 x4

f3

x3

x2

x1 f2

f1c5

c6

c7

c8 G2

G1

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Test Generation for BFsTest Generation for BFs

Test generation: using a stuck-at fault test generator on a transformed circuit

• For <c1,c2>, where c1 and c2 are gate outputs: insert an EXCLUSIVE-OR gate G with inputs c1 and c2

– Target stuck-at fault: s-a-0 at the output of G

• For <c1,c2> involving two internal nodes of a gate: place opposite values on c1 and c2

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Test Generation ExampleTest Generation Example

Example: For the BF shown:• c3 = 0 and c5 = 1:

– (c1 = 1) and (x4 = x5 = 0): gate G1

• c3 = 1 and c5 = 0:

– (x1 = 1, c1 = 0) and (x4 = 1 or x5 = 1): gate G2

• Target: s-a-0 fault at the output of G

Vdd

x4

f2

Vss

x5

Vdd

x2 c1

Vss

x3

Vdd

x1 f1

Vss

c3

c2

c5

c4

c1

x5

x4

x1x3

x2

x5 G

G2

G1

x4

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Delay Fault TestingDelay Fault Testing

Underlying assumption: gate propagation delays are fixed and independent of input values

• Not entirely accurate: but suffices and keeps test generation tractable

Clocking schemes: variable clock or rated clock• Variable clock: test generation easier,

test application more difficult• Rated clock: test generation more difficult,

test application easier

Inputclock

Inpu

t lat

ches

Combinationalcircuit

t1

(a) Circuit under test.

Out

put l

atch

es

P1

Outputclock

t3t2

(b) Variable clock.

P2P1

t0 t3t2t1

(c) Rated clock.

P0

P2

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Basic DefinitionsBasic Definitions

Controlling input value: uniquely determines output value independent of other input values• Else, non-controlling value

Example: controlling value for OR or NOR: 1

controlling value for AND or NAND: 0

Path R: sequence g0g1…gr, where g0 is a primary input, g1g2…gr-1 are gate outputs, and gr is a circuit output

• On-input of R: connection between two gates along R• Side-input of R: any connection to a gate along R other than its on-input

Two path delay faults (or logical paths): for each physical path R depending on the direction of signal transition along R

• If desired transition at g0 is rising (falling): R ( R)

• Alternatively, if desired transition at gr is rising (falling): R (R )

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Classification of Path Delay FaultsClassification of Path Delay Faults

Two main types of path delay faults: non-robustly testable and robustly testable

(P1,P2) is a non-robust test: if and only if

• It launches the desired logic transition at the primary input of the path, and

• All side-inputs of the path settle to non-controlling values under P2

Example: Application of {(0,1),(1,1)}• Non-robust test for: x1c1c2f

• Cannot guarantee detection: if observation point is t2, this test is invalidated since correct value 0 obtained for the second vector even in the presence of the fault

– Can happen if fault x1c2f is also present

x1x2

f

c3

c2

c1 G3

G4

G2

G1

S1 t4

t3

t2

t1

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Robust TestRobust Test

A robust test can detect the targeted fault independently of the delays in the rest of the circuit: it must satisfy

• The conditions for non-robust tests, and• Whenever the logic transition at an on-input is from a non-controlling

value to a controlling value, each corresponding side-input should maintain a steady non-controlling value

Example: Application of {(0,0),(1,0)}• Robust test for: x1c2f

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Validatable Non-robust TestValidatable Non-robust Test

A non-robust test may be invalidated by other path delay faults: however, if the invalidating path delay faults are robustly testable, then the non-robust test is called validatable

Example: the rising transition at f just after t2 corresponds to x1c2f , which has a robust test {(0,0),(1,0)}

• If the circuit passed this test: then the observation time can only be t3 or t4 when {(0,1),(1,1)} is applied

• In both cases: the test is valid

• Thus, {(0,1),(1,1)} is a validatable non-robust test for x1c1c2f

– Because either the path delay fault is caught if the observation time is t3 or the circuit is free of this fault if the observation time is t4

x1x2

f

c3

c2

c1 G3

G4

G2

G1

S1 t4

t3

t2

t1

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Test Generation for Path Delay FaultsTest Generation for Path Delay Faults

Five-valued system and covering relationship:

U1

XX S0 S1

U1

XX

U0

S1

S0

(a) Five-valued system.

U0

(b) Covering relationship.

t2 t3

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Implication TablesImplication Tables

S0 U0 S1 U1

(a) AND table.

S0

U0

S1

U1

S0

x2x1

S0

S0

S0

S0

U0

U0

U0

S0

U0

S1

U1

S0

U0

U1

U1

U0 XX XXS0XX

S0

U0

XX

XX

XX

XX S0 U0 S1 U1

(b) OR table.

S0

U0

S1

U1

U0

x2x1

S0

S1

U1

U0

U0

S1

U1

S1

S1

S1

S1

U1

U1

S1

U1

XX S1 U1XXXX

XX

XX

XX

S1

U1

XX x1

U0

S0

S1

U1

XX

(c) NOT table.

f

XX

U0

S0

U1

S1

x1x1 fx1fx2fx2

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Test Generation for Robustly Testable Test Generation for Robustly Testable PDFsPDFs

In deriving two-pattern tests for PDFs: U0 and U1 are interpreted in two different ways• U0 (U1) on an on-input is interpreted as a 1->0 (0->1) transition

• U0 and U1 on other lines have the conventional interpretation: signals with final value 0 (1)

(P1,P2) robustly tests a PDF if and only if:

• It launches the desired transition at the input of the path, and

• The side-inputs have values covered by the following table

– Such side-inputs are called robust

Example: Robust side-inputs

U0

S0

S1

U1

Falling(U0)

On-inputtransition

AND or NAND

Gate type

Rising(U1)

OR or NOR

x1x2 S1U1

x1x2

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Robust Test Generation ExampleRobust Test Generation Example

Example: Suppose the bold path with a rising transition at its input needs to be tested

• Two-pattern test: {(0, ,0,0, ), (0, ,1,0,0)}

f

x1x2

x3

x5

x4

c1

S0

U0x1

U0U0

U0S1

U1

S0

S0U1

XX

c4

c3c2

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Test Generation for Non-robustly Testable Test Generation for Non-robustly Testable PDFsPDFs

Relax conditions as follows:

Example: Non-robust side-inputs

A non-robustly testable PDF has at least one non-robust side-input• To reduce the chance of test invalidation: reduce the number of non-robust side-inputs• Slack: the amount of time by which the non-controlling value on the side-input becomes stable before the on-input

becomes stable• If slacks of all side-inputs are positive: no test invalidation can occur• Aim of test generation: maximize the slack of non-robust side-inputs

U0

U0

U1

U1

Falling(U0)

On-inputtransition

AND or NAND

Gate type

Rising(U1)

OR or NOR

x1x2

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Making Non-robust Tests ValidatableMaking Non-robust Tests Validatable

Make non-robust tests with minimal number of non-robust side-inputs and maximal slack validatable when possible:

• If two-pattern test P has don’t cares: specify them to minimize the number of transitions at the primary input

– E.g., specify U1 as 11– Specify U0 as 00– Specify XX as 00 or 11

• After Pnew is obtained this way: check for the non-robust side-inputs that need to be robustly tested to validate Pnew

– If these identified logical paths are indeed robustly testable: then the non-robust Pnew is validatable

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Test Generation for Transition FaultsTest Generation for Transition Faults

(P1,P2) is a slow-to-rise transition test at output gi of some gate in a circuit if it satisfies:

• gi(P1) = 0, and

• gi(P2) = 1 and a path is sensitized from gi to some circuit output under P2

– Thus, P2 is simply a s-a-0 test for gi

(P1,P2) is a slow-to-fall transition test at output gi if:

• gi(P1) = 1, and

• P2 is a s-a-1 test for gi

To reduce the possibility of test invalidation: choose P1 and P2 that differ in only one bit whenever possible

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Transition Fault Testing ExampleTransition Fault Testing Example

Example: Test for a slow-to-rise transition fault at c3

• P1 must make c3 = 0: ( , ,0, , )

• P2 must make c3 =1 and sensitize any path from c3 to f: (0, ,1,1,1)

• A possible two-pattern test: {(0,0,0,1,1), (0,0,1,1,1)}

x1

x2

f

c1

x3

x4

c4

c3

c2

c6

c5

x5

40

At-speed Test GenerationAt-speed Test Generation

At-speed tests: rated clock tests

Under the assumption that the delay fault (either PDF or TF) does not cause the delay of the path to exceed two clock cycles:

• A variable clock two-pattern test (P1,P2) can be converted to: a rated clock three-pattern test (P1,P1,P2)

– Signal values are guaranteed to stabilize when the first vector is left unchanged for two clock cycles

Generalization: under the assumption that the delay fault does not cause the delay of the path to exceed n clock cycles:

• Derive an (n+1)-pattern test: where P1 is replicated n times

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Synthesis for TestabilitySynthesis for Testability

Incorporate testability considerations: during synthesis itself• Synthesis for full testability: remove all redundancies from the circuit s.t. it becomes fully testable• Synthesis for easy testability: aimed at reducing test generation and applications times and increasing fault

coverage

Synthesis of two-level circuits for stuck-at fault testability:• Two-level circuits: frequently the starting point for further logic optimization• An AND-OR or NAND-NAND circuit based on an irredundant sum of products: fully testable for all single stuck-at

faults• A single stuck-at fault test set: also detects all multiple stuck-at faults in the circuit• The same results hold: for an OR-AND or NOR-NOR two-level circuit derived from an irredundant product of sums

Example: Two-level circuit for f = x1x2 + x2x3

• {(0,1,0), (0,1,1), (1,0,1), (1,1,0)} detects all

single stuck-at faults in it (hence, also all

multiple stuck-at faults)

x1x2

x3

f

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Transformations to Preserve Single Transformations to Preserve Single Stuck-at Fault TestabilityStuck-at Fault Testability

Logic transformations: to convert an initial single stuck-at fault testable circuit to a final circuit which is also single stuck-at fault testable

Algebraic divisor: single-cube or multiple-cube

Example: For f = x1x2x3 + x1x2x4 + x5

• g1 = x1x2 is a single-cube algebraic divisor

• g2 = x2x3 + x2x4 is a multiple-cube algebraic divisor

• If we express f as x1g2 + x5: g2 is said to be algebraically resubstituted in f

By identifying algebraic divisors common to two or more expressions and resubstituting them: can convert a two-level circuit into a multi-level circuit (see Chapter 6)

• Complements of the divisors can also be resubstituted

43

DefinitionsDefinitions

A Boolean expression is cube-free: if the only cube dividing f evenly is 1• A cube-free expression must have more than one cube

Example: x1x2 + x3 is cube-free, but x1x2 + x1x3 and x1x2x3 are not

Double-cube divisor: cube-free multiple-cube divisor having exactly two cubes

Example: For f = x1x4 + x2x4 + x3x4

• Double-cube divisors: {x1 + x2, x1 + x3, x2 + x3}

44

MethodologyMethodology

Obtain multi-level circuit using only: single-cube divisors, double-cube divisors, and their complements

• Complements obtained using: only De Morgan’s theorem• Boolean reductions: (a + a = a; a + a’ = 1; a.a = a; a.a’ = 0) not used• Furthermore, for simplicity: use only two-literal single-cube divisors and double-cube divisors with at

most two literals in each of the two cubes and at most three variables

Single-cube extraction: extract cubes common to two or more cubes• Create the common part as an intermediate node

Example: From f = x1x2A1 + x1x2A2 + … + x1x2An

• Extract cube C = x1x2

• Substitute to obtain CA1 + CA2 + … + CAn

45

Methodology (Contd.)Methodology (Contd.)

Double-cube extraction: extract a double-cube from a single-output sum-of- products expression AC + BC to obtain C(A+B)

Dual expression extraction: transform a sum-of-products expression f as follows:• f = x1A1 + x2A1 + x1’x2’A2 to M = x1 + x2 and f = MA1 + M’A2

• f = x1x2’A1 + x1’x2A1 + x1’x2’A2 + x1x2A2 to M = x1x2’ + x1’x2 and f = MA1 + M’A2

• f = x1x2A1 + x2’x3A1 + x1’x2A2 + x2’x3’A2 to M = x1x2 + x2’x3 and f = MA1 + M’A2

At each step of the synthesis process: the method greedily selects and extracts a double-cube divisor jointly with its dual expression or a single-cube divisor that results in the greatest literal-count reduction

• If above transformations applied to a single-output irredundant sum of products: single stuck-at testability is preserved

• If circuit C1 is transformed to circuit C2: single stuck-at test set of C1 is guaranteed to detect all single stuck-at faults in C2

– Such transformations called test set preserving

46

Transformations to Preserve Multiple Transformations to Preserve Multiple Stuck-at Fault TestabilityStuck-at Fault Testability

If algebraic factorization without complement is applied to a single-output two-level circuit based on an irredundant sum of products: then the resultant multi-level circuit is testable for all multiple stuck-at faults using the single stuck-at fault test set of the two-level circuit

• Divisors need not be limited to single-cube and double-cube divisors

Even though general algebraic factorization preserves multiple stuck-at testability: it does not preserve single stuck-at fault testability

• Because in a single stuck-at fault testable circuit, a multiple stuck-at fault may be redundant: after algebraic factorization, it may become single redundant stuck-at fault

Example: If we replace G1 and G2 with a single gate, corresponding to factoring a single cube: s-a-0 or s-a-1 at the output of H is not testable

x4x2

x5

G1

(a) Testable circuit.

x3

x1

f

x6

(b) Circuit with untestable fault.

x7

G2MUX

x4

x2

x5

H

x3

x1

f

x6x7

MUX

47

Redundancy Identification and RemovalRedundancy Identification and Removal

Unintentional redundancies: due to sub-optimal logic synthesis• Negative impact: larger chip area and delay than necessary

Detecting redundancies: computationally intensive• Test generation algorithms declare a fault redundant: if they fail to generate a test vector for it• Presence of a redundant fault may:

– invalidate the test for another fault, or – make a detectable fault redundant, or– make a redundant fault detectable– Thus, not possible to remove all redundancies in a single pass

Redundancy identification and removal methods:• Indirect: byproduct of test generation; thus, computationally expensive• Direct: can identify redundancies without the search process involved in test generation

– Static: analyze circuit structure and perform value implications– Dynamic: work with indirect methods, without requiring test generation– Don’t-care based: functional extraction and logic minimization

48

Indirect MethodIndirect Method

If a complete test generation method fails to generate a test for k s-a-0 (s-a-1): then k can be connected to 0 (1) without changing the function implemented by the circuit

• Then reduce circuit by:

– Simplifying gates connected to constant values

– Replacing a single-input AND/OR (NAND/NOR) by a direct connection (inverter)

– Deleting all gates that do not fan out to any circuit output

Simplification rules:1. If input s-a-0 of an AND (NAND) gate is redundant: remove gate and replace with 0 (1)

2. If input s-a-1 of an OR (NOR) gate is redundant: remove gate and replace with 1 (0)

3. If input s-a-1 of an AND (NAND) gate is redundant: remove input

4. If input s-a-0 of an OR (NOR) gate is redundant: remove input

49

Indirect Method (Contd.)Indirect Method (Contd.)

Example: Redundant faults in circuit (a): • s-a-0: x1, x3, c1

• s-a-1: x1, x3, c1, c2, c3

• If none of these faults present: c4 s-a-1 detected by (1,0,1,1)

– However, presence of x1 s-a-0 makes c4 s-a-1 redundant

• Targeting x1 s-a-0 for removal: obtain circuit (b) in first pass

• Do test generation for all the faults again: find both x2 s-a-1 faults to be redundant

– Removing either one: makes the other one detectable– Targeting either: arrive at circuit (c) in the second pass

x1

x2 f

G1

x3

x4

c4

c3

c2

c1

G3G2

(a) Initial circuit.

x2

x2

x4

f

(b) First pass.

x2x4

f

(c) Second pass.

G5G4

50

Interesting Use of Indirect MethodInteresting Use of Indirect Method

Deliberately add redundancies to an irredundant circuit: to create yet more redundancies which, upon removal, yield a more optimized circuit

Mandatory assignments: value assignments to some lines that must be satisfied by any test vector for the given fault

• Control assignments

• Observation assignments

• If these assignments are simultaneously satisfiable: then the fault is redundant

• Using this approach: add redundant connections (with or without inversions) to maximize redundancies elsewhere

• Target these other redundancies for removal

51

Indirect Method ExampleIndirect Method Example

Example: Consider c1 s-a-0 in circuit (a) (ignore dashed connection)

• Mandatory control assignment: c1 = 1

• Mandatory observation assignment: c2 = 0

• These assignments imply: x1’ = 1, x3 = 1, x2 = 0

– These imply: c3 = 1, c4 = 0, f2 = 1

• Since c3 = 1: with dashed connection – no effect of c1 s-a-0 at f1

• Thus, c1 s-a-0 becomes redundant

• Verify that adding the connection does not change the input/output behavior of the circuit: in order to test for s-a-0 on it

– Mandatory control assignment: c3 = 1

– Mandatory observation assignments: c1 = 0, c2 = 0

– Assignments not jointly satisfiable:

thus, connection redundant• After adding connection: simplify

logic because c1 s-a-0 is now

redundant• Of course, dashed connection

no longer redundant

x1

x2

f1x3

x2

c1

f2

x3

x2

x1

x3

x1

(a) Original circuit.

x2

f1

x2

f2

x3

x2

x1

x3

x1

(b) Final circuit.

c4

c3

c2

52

Static Direct MethodStatic Direct Method

Static methods are very fast, as they don’t need exhaustive search:• However, they are not able to identify all redundancies• Useful as a preprocessing step to an indirect method

Use an illegal combination of values to identify redundancies:• Suppose values v1, v2, and v3 cannot simultaneously occur on lines c1, c2, and c3

– Then faults for which this illegal combination is mandatory are redundant• First find faults for which each condition is individually mandatory

• Scivj: denotes the set of faults that must have value vj on line ci for detection

• The faults requiring the above illegal combination for detection are in: Sc1v1 Sc2

v2 Sc3v3

• Use uncontrollability and unobservability analysis to find these faults

53

Uncontrollability and UnobservabilityUncontrollability and Unobservability

Uncontrollability status 0u (1u): line cannot be controlled to 0 (1)

Propagation rules: uncontrollability status propagated forward and backward

If a gate input cannot be set to its non-controlling value: then all other inputs become unobservable• Unobservability status: can be propagated backward from gate output to all its inputs

• Marking of a fanout stem as unobservable: requires satisfaction of special conditions

• Redundant faults identified as those: that cannot be activated [s-a-0 (s-a-1) faults on lines with 1u (0u)] or propagated (both faults on unobservable lines)

1u

1u

1u 1u

1u0u

0u(1u)0u0u

0u0u

0u(1u)

0u(1u)

1u(0u)0u(1u)

54

Extension of MethodExtension of Method

Method can be extended based on arbitrary illegal value combinations:1. Form a list L of all fanout stems and reconvergent inputs

2. For each line c in L, find implications of c = 0u (1u) to determine all uncontrollable and unobservable lines: let F0 (F1) be the set of corresponding faults

3. The redundant faults are in the set F0 F1: reason is that such faults simultaneously require c to be 0 and 1, which is not possible

Example: For circuit (a), L = {x1, x2, c6, c7}

• Target c6

• c6 = 0u does not imply uncontrollability or unobservability of any other line: F0 = {c6 s-a-1}

• c6 = 1u implies: x3 = c5 = c1 = c3 = x1 = x2 = c2 = c4 = c7 = f = 1u

• Since c6 = 1u (c7 = 1u): error propagating to c7 (c6) due to any fault cannot propagate to f

• Hence, F1 = {s-a-0 on c6, x3, c5, c1, c3, x1, x2, c2, c4, c7, f and s-a-1 on c6, x3, c5, c1, c3, c7, c2, c4}

• Since F0 F1 = {c6 s-a-1}: c6 s-a-1

is redundant. This yields circuit (b)

x1

x2 fx3

c4

c3

c2

c1

(a) Initial circuit.

x1x2

f

(b) Final circuit.

c6

c7

c5

55

Dynamic Direct MethodDynamic Direct Method

Dynamic method: also does not require exhaustive search• It requires a test generator to first identify a redundant fault

• Thereafter, such a method identifies additional redundant faults

• It can remove identified redundancies in just one pass of test generation

– However, it cannot guarantee a single stuck-at fault testable circuit at the end of the process

• It also takes advantage of uncontrollability and unobservability analysis

Region of a redundant fault: subcircuit that can be removed because of it

Level of a gate: max. level of any gate fanin + 1• Assume primary inputs to be at level 0

When region of a redundant fault r1 is contained within the region of another redundant fault r2: it is preferable to target r2 first

• Target the faults at higher levels first in test generation

56

Dynamic Direct Method (Contd.)Dynamic Direct Method (Contd.)

Once a redundant fault has been removed: we need to identify the newly created redundancies• These are faults that would have been detectable had the removal not occurred

Theorem: Let A be an output of a redundant region R and G be the gate fed by A. Let c be the controlling value and i the inversion of G (0 for a non-inverting gate and 1 for an inverting one). Assume that the combination consisting of c’ values on the remaining inputs of G and c i value on its output was feasible (legal) in the old circuit. Then this combination is illegal as a result of removal.

Once an illegal combination of values is identified:• Uncontrollability/unobservability analysis: can identify the newly created redundancies• Note that the uncontrollability status can be propagated forward and backward everywhere except through

gate G• Of all the newly created redundancies: only the highest-level fault is removed

+

57

Dynamic Method ExampleDynamic Method Example

Example: suppose in circuit (a), the test generator has identified x1 s-a-0 as redundant

• Region R of this fault: just gate G1

• This region feeds gate G2: whose controlling value is 1 and inversion 0

• Combination (c2 = 0, c3 = 1) was legal in the old circuit

– However, once R is removed: this combination becomes illegal

• Translate illegal combination to: c2 = 0u, c3 = 1u

• 0u on c2 can be propagated backward:

– Sc20 = {s-a-1 on c2, x2, c4}

• 1u on c3 can be propagated forward: recognizing that the side-inputs of G3 become unobservable

– Sc31 = {s-a-0 on c3, f, c4, x4, and s-a-1 on c4, x4}

• Since Sc20 Sc3

1 = {c4 s-a-1}: c4 s-a-1 is newly redundant

• After removing this fault: we directly obtain circuit (b) in one pass– Earlier indirect method

required two passes

x1

x2 f

G1

x3

x4

c4

c3

c2

c1

G3G2

(a) Initial circuit.

x2x4

f

(b) Second pass.

G5

58

Don’t Care Based Direct MethodDon’t Care Based Direct Method

A multi-level circuit consists of an interconnection of various logic blocks:• Even if these blocks are individually irredundant: the multi-level circuit can still

contain redundancies

Satisfiability don’t care set: vectors that cannot be fed to embedded blocks

Observability don’t care set: vectors for which the block output are not observable at the circuit output

Use these sets to resynthesize the logic blocks: such that the multi-level circuit has fewer redundancies

59

Don’t Care Based Method (Contd.)Don’t Care Based Method (Contd.)

Let the Boolean variable corresponding to node j, for j = 1, 2, …, p, of the multi-level circuit be fj and the logic representation of fj be Fj

• Satisfiability don’t care set, DSAT, is common to all nodes:

DSAT = DSATj, for j = 1 to p

DSATj = fj Fj

• DSATj can be interpreted to mean that since fj = Fj, condition fj Fj is a don’t care

Let the set of circuit outputs be PO:• Observability don’t care set, DOBSj, for each node j:

DOBSj = DOBSij, for i in PO

DOBSij = [(Fi)fj (Fi)fj’]’

• DOBSj corresponds to a set of values at the primary inputs under which all the circuit outputs are insensitive to value fj that node j takes on

+

+

60

Don’t Care Based Method ExampleDon’t Care Based Method Example

Example: Even though each block in circuit (a) is individually redundant, the circuit can be checked to be redundant

• Since f3 = f1f2x1’x4’ + x1x3:

– DOBS1 = [(f2x1’x4’ + x1x3) (x1x3)]’ = f2’ + x1 + x4

• Hence, f1 = x1x2 + x3 can be simplified to just x3: since x1 is in DOBS1, which includes x1x2 in f1

– Interpretation: x1x2 term in f1 is not observable at output f3

• Similarly, DOBS2 = f1’ + x1 + x4

– Hence, f2 = x4 + x5 can be simplified to just x5 since x4 is in DOBS2

• Using simplified equations f1 = x3 and f2 = x5:

– DSAT1 = f1x3’ + f1’x3 and DSAT2 = f2x5’ + f2’x5

• Hence, f3 can be simplified w.r.t. the don’t cares in DSAT1 + DSAT2

– f3 = f1f2x4’ + x1x3 since the consensus of x1x3 and f1x3’ is x1f1 which simplifies f1f2x1’x4’ to f1f2x4’

+

x1

x4

f1

x4

x3

f2x5

x2

x1

x3

x1

(a) Original circuit.

f3x1

x4

x3

x5

x3

(b) Final circuit.

f3

f1

f2

11

x1x2

0

1

00 01 11 10

Simplified f1 = x3.

1

x4

0

1

0 1

Simplified f2 = x5.

61

Synthesis for Delay Fault TestabilitySynthesis for Delay Fault Testability

Robustly path delay fault testable circuit: if robust two-pattern tests exist for every path delay fault in it

Two-level circuits: use tautology checking• A function is a tautology: if it is 1 for all input vectors• Suppose we want to test a path starting with literal l going through AND gate G and the OR gate:

– Both path delay faults through this literal are robustly testable: if and only if after making the side-inputs of G equal to 1, the output values of the remaining AND gates can be made 0 using some combination without using l or l’

– Thus, we can first make the side-inputs of G 1, delete l and l’ from the remaining products, and then delete G from the corresponding sum of products

» If the remaining switching expression becomes a tautology: then the path is not robustly testable, else it is

62

Two-level Circuit ExampleTwo-level Circuit Example

Example: Circuit implements f = x1x2 + x1x3’ + x1’x3

• Suppose we want to robustly test the rising transition shown in circuit (a)

• We first enable side-input x2 = 1

• We then delete G1, literal x1 from G2 and x1’ from G3

– Thus obtaining fred = x3’ + x3 = 1

• Since fred is a tautology, the path is not robustly testable

– The partial assignment shown in circuit (a), which is required for robust testability, is not satisfiable

• Now suppose we want to robustly test the path shown in circuit (b)

– After making x1 = 1: we obtain fred = x3’ which can be made 0 by making x3 = 1

– Thus, robust two-pattern test: {(1,0,1), (1,1,1)}

x1

f

x3

x2

x1

x3

x1

(a) Untestable fault.

U1G1

S0

S0

U1

U0

U1

U1

G4

G3

G2

x1

f

x3

x2

x1

x3

x1

(b) Testable fault.

S1G1

S0

S0

U1

S0

S1

U1

G4

G3

G2

S1

S0

63

Two-level Circuits (Contd.)Two-level Circuits (Contd.)

Necessary condition for robust path delay fault testability: implementation should be based on an irredundant sum of products

• Unfortunately, not sufficient: as we just saw

Robust testability for transition faults: verify that for both rising and falling transitions, at least one path through each gate is robustly testable

• Using an irredundant sum of products: neither necessary nor sufficient for transition fault testability

Example: Circuit implements f1 = x1 + x2 + x1’x2’x3

• Not an irredundant sum of products: yet the slow-to-rise and slow-to-fall transition faults at the output of both G1 and G2 are robustly testable

• Consider f2 = x1x3 + x1x2 + x1’x2’ + x3x4 + x3’x4’

– Even though it is irredundant: transition faults at the output of the first AND gate are not robustly testable since neither of the paths from x1 and x3 is robustly testable

x1

x2 f1

x3

x1

x2

G2

G1

64

Multi-level CircuitsMulti-level Circuits

Shannon’s decomposition: can be used to obtain a robust path delay fault testable circuit which is also completely testable for all combinations of multiple stuck-at faults and stuck-open faults

Shannon’s decomposition: f(x1,x2, …,xn) = xifxi + xi’fxi’

• If f is binate in xi: then the decomposed circuit is robustly testable if the subcircuits for the two cofactors are robustly testable

• If subcircuits are not robustly testable after one decomposition: apply decomposition recursively to the cofactors until robustly testable subcircuits are obtained

– Guaranteed to terminate in n-2 steps: since that will yield a two-variable cofactor that is guaranteed to be robustly testable

– One can also stop when a unate cofactor is obtained: also guaranteed to be robustly testable

– Actually, most binate cofactors are robustly testable too

x1 Subcircuitfor fx xi

f

c1

xi

i

Subcircuitfor fx

ic2

c4

c3xixn

x i-1

x1

xixn

x i-1

65

Shannon’s Decomposition (Contd.)Shannon’s Decomposition (Contd.)

Heuristic 1 for choosing the binate variable to target first for decomposition: choose the one that appears the most number of times in complemented or uncomplemented form in the sum of products

Heuristic 2: choose a variable that leads to robust untestability in a maximum number of gates

Example: Consider f2 = x1x3 + x1x2 + x1’x2’ + x3x4 + x3’x4’

• Robustly untestable literals: x1 and x3 in the first AND gate

• Using either heuristic: we can choose either x1 or x3

• Choosing x1:

f2 = x1(x2 + x3 + x4’) + x1’(x2’ + x3x4 + x3’x4’)

• Since the two cofactors are robustly testable: so is the decomposed circuit for f2

66

Algebraic FactorizationAlgebraic Factorization

Given a robustly path delay fault testable circuit: algebraic factorization with a constrained use of complement maintains its robust path delay fault testability

• Robust test set is also preserved after factorization

Main problem with the approach: frequently, two-level circuits based on irredundant sum of products, which are starting points for synthesis, are not robustly testable

• For f1 = x1x2 + x1x3’ + x1’x3: no irredundant sum of products leads to robust testability

• For f2 = x1x2’ + x1’x2 + x1x3’ + x1’x3: literal x1 in x1x2’ is not robustly testable

– However, f2 has another realization: x1x2’ + x1’x3 + x2x3’, which is robustly testable

67

Algebraic Factorization (Contd.)Algebraic Factorization (Contd.)

Heuristic: bias the two-level logic synthesizer towards robustly testable implementations, whenever possible

Relatively essential vertex of a prime implicant in a sum of products: minterm that is not contained in any other prime implicant in the sum of products

• Heuristic tries to maximize the number of relatively essential vertices in the prime implicant: that are just one bit different from some vertex in the OFF-set of the function

– Increases the probability of meeting the necessary and sufficient conditions for robust path delay fault testability

68

Algebraic Factorization (Contd.)Algebraic Factorization (Contd.)

Surprisingly, algebraic factorization does not main robust transition fault testability

Example: Circuit (a) is robustly testable• But after algebraic factorization: circuit (b) is not since no path through G3 is

robustly testable• To preserve robust testability: use a constrained form of algebraic factorization

– Each cube in each factor should have at least one path through it: which is robustly testable

– Thus, if we had used x1’x3 or x2’x3 as a factor instead of x1’x2’: robust testability would have been maintained

x1

x2 f1

x3

(a) Robustly testable.

x1

x2

f1

(b) Non-robustly testable.

x1

x2

x3

x1

x2

G3

G2

G1

69

Targeted Algebraic FactorizationTargeted Algebraic Factorization

Useful in obtaining a robustly testable multi-level circuit in the vast majority of cases where the original two-level circuit is not robustly testable

• Main idea: First convert the two-level circuit, which is not robustly testable, into an intermediate circuit (typically, with three or four levels) which is

• Then algebraic factorization with a constrained use of complement can be used as before

Consider the irredundant sum of products • Suppose that

– (a) in each term in f, all literals in Mj are robustly testable

– (b) each literal in set {x1,x2, …,xn} is robustly testable in at least one product term in f, and

– (c) the other literals in f are not necessarily robustly testable

• Then literals x1, x2, …, xn are robustly testable when factored out:

70

Targeted Algebraic Factorization (Contd.)Targeted Algebraic Factorization (Contd.)

Example: Consider the irredundant sum of products f1 = x1x2x3* + x1*x3x4 + x1’x2’x4 + x3’x4’, where starred literals are not robustly testable

• Using the synthesis rule: we obtain f1 = x1x3(x2 + x4) + x1’x2’x4 + x3’x4’, which is robustly testable

Example: Consider f2 = x1x2*M1 + x1*x2M2 + x1*x2*M3 + x1*M4 + N1

• Using synthesis rule once: f2 = x1x2(M1 + M2 + M3) + x1*M4 + N1

• Using it again: f2 = x1{x2(M1 + M2 + M3) + M4} + N1, where both x1 and x2 are now robustly testable

When the synthesis rule is not successful with the sum of products for f: it is frequently successful with f’

Repeated Shannon’s decomposition is not area-efficient: whereas area- efficient algebraic factorization cannot guarantee robust testability

• Apply targeted algebraic factorization: when applicable, to Shannon cofactors

71

Test Generation for NanotechnologiesTest Generation for Nanotechnologies

Test generation for a threshold gate that implements f(x1,x2, …,xn):

• xi s-a-0: activated by xi = 1

• In the fault-free case:

– Moving wi to the RHS:

• When the fault is present:

72

Test Generation for Nanotechnologies Test Generation for Nanotechnologies (Contd.)(Contd.)

A test vector can be found for xi s-a-0 by finding an assignment on the input variables with xi = 1: such that Eqs. (8-3) and (8-6) or Eqs. (8-4) or (8-5) are satisfied

• Similar analysis for xi s-a-1: now Eqs. (8-3) and (8-4) [(8-5) and (8-6)] refer to the faulty (fault-free) cases

Theorem: To find test vectors for xi s-a-0 and xi s-a-1 in a threshold gate implementation of f(x1,x2, …,xn), we must find an assignment of values to the remaining input variables such that one of the following inequalities is satisfied:

If an assignment exists, then along with xi = 1 (xi = 0), it is a test vector. If an assignment does not exist, then both faults are redundant

73

Test Generation for Nanotechnologies Test Generation for Nanotechnologies (Contd.)(Contd.)

Example: Consider a threshold gate that realizes f(x1,x2,x3) = x1x2 + x1x3 with weight-threshold vector <2,1,1; 3>

PDCF for x1 s-a-0: 101D, 110D, 111D

Propagation D-cubes: substituting D for x1, we get Dx2 + Dx3

• Thus, {D10D, D01D, D11D} and {D’10D’ , D’01D’ , D’11D’ } are propagation D-cubes

74

DD-algorithm Example-algorithm Example

Example: Test for x1 s-a-1

• PDCF in gate G1: 0000D’

• Error propagated using the propagation D-cube shown

• Justification of 1 needed on c2 by applying the relevant singular cube to gate G3

1

f1x3

x2

x1

x4

22

12

c1

1

f2x6

x5

x7

-1

12 2

x9

x10

1

11 3

D

x8G1

1

21 2

G4

G2

G3

0

0

00

0

c2

1

1

D

c3

0

75

Redundancy RemovalRedundancy Removal

Fault-free threshold gate and its faulty representations:

Example: redundancy removal for c1 s-a-0 (s-a-1)

x2

x1

xn

wn

w1w2

(a) Fault-free.

T f x3

x2

xn

wn

w2w3

(c) x1 s-a-1.

T - w1

fx3

x2

xn

wn

w2w3

(b) x1 s-a-0.

T f

f2

c1f1T1

x4

x5

w6

w4w5 T2

x6

w9

w7w8 T3

x7

x2

x1

x3

w3

w1w2

x6

x7

w9

w7

x4

x5

w6

w4

x6

x7

w9

w7

x4

x5

w6

w4

T3 -w8

T2 -w5

T3

T2

f2

f1

f2

f1T1

(a) Fault-free. (b) c1 s-a-0. (c) c1 s-a-1.