webinar on recent advancements and research opportunities

Webinaron

"Recent advancements and Research opportunitiesin Network-on-Chip(NoC) Architectures“

at NCET, Bengaluru

Dr.Bheemappa HIIIT,Sricity

[email protected]

Agenda1. Introduction

2. What is Network on chip architectures?

3. Recent advancements in Network-on-Chip(NoC)

Architectures

4. Research opportunities

in Network-on-Chip(NoC) Architectures

5/23/2021Webinar on Recent advancements and Research opportunities in Network-on-Chip(NoC) Architecture at

NCET,Bangalore

IIIT-S

Introduction

Webinar on Recent advancements and Research opportunities in Network-on-Chip(NoC) Architecture at NCET,Bangalore5/23/2021

• Interconnection Networks Domains• LAN,WAN,SANs

• OCNs(on-chip interconnects)

• Components of on chip• CPU, Memory, Input/Output ports

and secondary storage etc,radio

modems and graphics processing

unit (GPU)

• On-chip Interconnection Types

• Point-to-Point

• Shared bus

• Network-on-Chip

Where Is Interconnect Used?


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• To connect components

• Examples

• Processors and processor

• Processors and memories (banks)

• Processors and caches (banks)

• Caches and caches

• I/O device


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• Interconnects affects the scalability performance and energy efficiency of the

system.

• How fast can processors, caches, and memory communicate?

• How much energy is spent on communication?

Bus Pros

• Low cost

• Easier to Implement

• Flexible

Bus cons ()

• Electrical performance degrades with growth

• Bandwidth is limited and shared by all units attached.

5/23/2021

Webinar on Recent advancements and Research opportunities in Network-on-Chip(NoC) Architecture at NCET,Bangalore

Introduction I/O

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• On-chip Interconnection Types

Technology Trend: Towards ever larger chip multiprocessors (CMPs)


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• Bus based interconnect does not scale bus significantly.

• Reduces the its speed the shared bus cannot support the bandwidth demand

• As the number of processing elements increases, performance degrades

dramatically.

• Hence, they are not considered appropriate for systems of more than about 10

nodes[1]

1L. Benini and G. D. Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer,vol. 35, pp. 70–78, 2002

Technology Trend: Towards ever larger chip multiprocessors (CMPs)


NCET,Bangalore

• Bus based interconnect does not scale bus significantly.

• Reduces the its speed the shared bus cannot support the bandwidth

demand

• As the number of processing elements increases, performance

degrades dramatically.

• Hence, they are not considered appropriate for systems of more than about

10 nodes[1]

1L. Benini and G. D. Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer,vol. 35, pp. 70–78, 2002

Network on Chip

What is Network on chip architectures?


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Network on chip architectures


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• Network-on-Chip (NoC) is an emerging

paradigm for on chip communications for

SoC (Networking method to on-chip

communications)

• On-Chip Networks (OCN or NoCs)• scalability

• Efficient multiplexing of communication

• Buses replaced with Networked

architectures

• Higher bandwidth

• Energy efficiency

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R R R

R R R

R R RPEPEPE


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• Topology

• How to connect the nodes

• Routing

• Which path should a message take

• Series of road segments from source to destination

• Flow Control

• When does the message have to stop/proceed

• Traffic signals at end of each road segment

• Router Microarchitecture

• How to build the routers

• Design of traffic intersection (number of lanes, algorithm for turning

red/green)

NoC Basics

Recent advancements in

Network-on-Chip(NoC) Architectures


NCET,Bangalore

NoC Simulators


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Topology Overview


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• Topology is often the first step in

network design • Direct and Indirect Topology

• Significant impact on network cost

performance

• Determines implementation complexity,

i.e., cost

• Number of routers and links

• router degree (i.e., ports)

• Ease of layout

Mesh

Torus

2D-NoCTopology performance assessment


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NCET,Bangalore

3D- NoC


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• Conventional 2D-NoC: Not suitable for future large-scale systems.

• Planar substrate restrict space of implementable network

• High latency and high energy consumption.

• 3D-IC technology is an opportunity to reduce the on-chip communication delay

and energy through layer stacking.

• Combining the NoC structure with the benefits of the 3D integration

• Vertical Communication is achieved using Through Silicon Via (TSV). A via

that goes through the silicon substrate

Routing Basics


NCET,Bangalore

• Routing involves selecting a path from a source node to a destination

node in a particular topology.

• A well-designed routing algorithm => Reducing the number of hops

and the overall latency.

• Possible routing algorithms.

• Ring : binary decision

• Greedy: shortest direction around the ring

• Uniform random: Randomly pick a direction for each packet,

• Weighted random: weight the short direction

• Adaptive: Send the packet in the direction for which the local

channel has the lowest loads usage

Flow Control


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• – Flow control determines how a network’s resources, are allocated to packets

traversing the network.

• Messages are divided into packets for the allocation of control state and

into flow control digits (flits) for the allocation of channel bandwidth and

buffer capacity.

• Flow control methods

• Store-and-forward

• Wormhole Flow Control

Research opportunities

in Network-on-Chip(NoC) Architectures


NCET,Bangalore


NCET,Bangalore

Design of effective topology

Routing Algorithm

Flow control Mechanism

Low Power Router design

Adopting technology Trend

Research Areas

Power , performance and costResult

NoC Evaluation metrics :

1 Network Latency (cycles)2. Energy 2. Cost

Research Areas


NCET,Bangalore

• Architectural characterization

• Design space exploration

• 2D and 3D design Space

• Design of low latency, low power Router for on chip communication

• Effective routing algorithms for NOC architecture

• Develop standard benchmarks and evaluation methods.

• Design power and performance optimal application specific NoC.

• Design new cycle accurate simulator

• considering accurate wire delay and micro architectural

characteristics in cycle accurate simulators.

3D-NoC


NCET,Bangalore

• Minimize number of interlayer links (eg:TSVs) across 3D layers

• Design of innovative 3D topologies.

• Hybrid 3D interconnection paradigm

• Application specific NoC design has issue of assigning

processors and switches to specific location on the layers.

• Innovative mechanism for fair distribution of resources in 3D

NoCs.

• Detailed consideration of architectural and router

microarchitectural design parameters to optimize power

performance and cost of 3D NoCs architecture.

Thank you.


NCET,Bangalore


NCET,Bangalore

1. Agarwal, N., Krishna, T., Peh, L., and Jha, N. K. (2009). GARNET: A detailed on-chip network model inside a full-

system simulator. In IEEE

2. International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009,

Boston, Massachusetts, USA, Proceedings, pages 33–42.

3. Catania, V., Mineo, A., Monteleone, S., Palesi, M., and Patti, D. (2015). Noxim: An open, extensible and cycle-

accurate network on chip simulator. In 2015 IEEE 26th International Conference on Application-specific Systems,

Architectures and Processors (ASAP), pages 162–163.

4. Catania, V., Mineo, A., Monteleone, S., Palesi, M., and Patti, D. (2016). Cycle-accurate network on chip simulation

with noxim. ACM Trans. Model. Comput. Simul., 27(1):4:1–4:25.

5. Effiong, C., Lapotre, V., Gamati e, A., Sassatelli, G., Todri-Sanial, A., and Latif, K. (2015). On the performance

exploration of 3d nocs with resistive-open tsvs. In VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium

on, pages 579–584. IEEE.

6. R. W. (2009). Compact modelling of through-silicon vias (tsvs) in three-dimensional (3-d) integrated circuits.

Performance Analysis of Systems and Software (ISPASS), pages 86–96.

7. Joseph, J. M., Blochwitz, C., Pionteck, T., and GarcÃa-Ortiz, A. (2015). Area and power savings via buffer

reorganization in asymmetric

8. 3d-nocs for heterogeneous 3d-socs. In Nordic Circuits and Systems Conference (NORCAS): NORCHIP International

Symposium on System-on-Chip (SoC), 2015, pages 1–4.

9. Computer Architecture: A Quantitative Approach 5th Edition, Appendix F (4th Edition, Appendix E)

10. Tota andMario R. Casu, “Networks-on-Chip,” presentation. enini, “Networks on chip,” presentation,

.tlc.polito.it/~nordio/seminars/2006_05_05_Casu.ppt

References

http://www.tlc.polito.it/~nordio/seminars/2006_05_05_Casu.ppt

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