v.jayalakshmi , dr.s.prakash · 2 figure 1 block diagram 3. multilevel inverter the stepped...

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MODELING AND ANALYSIS OF H-BRIDGE FIVE LEVEL INVERTER

V.JAYALAKSHMI1, Dr.S.PRAKASH2,

1Assistant professor, 2Professor,Dept. of EEE,

BIST, BIHER, Bharath university,Chennai-73

[email protected]

ABSTRACT

A multilevel Inverter(MLI) accomplishes high power evaluations, as well as

empowers the utilization of renewable vitality sources.MLI offer high power capacity.

Their principle hindrance is their many-sided quality, requiring an incredible number of

force gadgets and aloof parts, and a fairly difficult control hardware. In this work a MLI

with reduced switching technique is implemented for industrial application. H-bridge

bidirectional auxiliary switch is used in this methodology. Another topology is utilized as

a part of the outline of a five-level inverter, just five controlled switches, eight diodes, and

two capacitors are required to execute the five-level inverter utilizing the proposed

topology. The requirement of main power switches requiredis reduced to 37.5% without

diodes or capacitors. Matlab simulation is carried out for the new topology and the results

verify its performances

Key words:H-bridge,Multilevel converter,MOSFET

1.INTRODUCTION

Multi Level Inverter (MLI) topology utilizing a H- bridge output stage with a bidirectional

auiliary switch makes an immense lessening in the amount of power devices and

capacitors required to realize a multilevel output. An inverter is an power electronic device

which convertsDC to AC[1-6]. By the utilization of fitting transformers, exchanging, and

control circuits, the obtained AC may have the desired magnitude and frequency.

inverters have wide range of applications such as (i) small trading power supplies in PCs,

(ii) utility in high-voltage direct current applications[7-11]. (iii)Acts as a sourcefor solar

panels or batteries.

2.BLOCK DIAGRAM

The block diagram is shown below:

International Journal of Pure and Applied MathematicsVolume 119 No. 12 2018, 6727-6738ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

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Figure 1 Block diagram

3. MULTILEVEL INVERTER

The stepped waveforms can be obtained with the help of MLI which comprises voltage

sources,semiconductors devices and capacitors as filters. The recompense of switches

produce the expansion of capacitor voltages, which comes about as high voltage at yield,

while the power semiconductor must withstand just decreased voltages. The different

topologies of MLI demonstrate various qualities in like manner, over bi-level converters,

for example[12-19],

i. The turn off frequency of the power electronics devicesareeliminated

ii. The operations at high voltages can be carried out.

iii. The Transient voltages can be consequently constrained[20-26].

The cost of the MLI can be reduced without affecting the standard design by having

innovative ideas. This paperrecommends another Inverter topology as shown in Fig. 1.

The Utilization bidirectional auxiliary switch with H-bridgetopology radically reduces the

power circuit. This idea is utilized as a part of the configuration of the five-level extension

inverter exhibited here. Thisconfiguration gives lessening in the segment include and

design many-sided quality when contrasted and the five-level converters[27-32].

DC VOLTAGE FIVE LEVEL INVERTER

AC MOTOR

110V,3A

ISOLATION UNIT

CURRENT

AMPLIFIER

MICRO

-CONTROLLER VCC 5V

VCC

12V

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Figure 2 Block diagram of Proposed topology

Figure 3 circuit diagram of five level H-Bridge inverter power stage

3.1Modes of operations

The generation of five level output voltage (Vs, Vs/2, 0, -Vs, -Vs/2) are shown below:


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3.1.1 Maximum positive output, Vs: Figure 4 shows the operation of switches to

generate the output voltage level Vs. Exactly when DISP1 is turn-on, the positive terminal

of load is joined with Vs, and when DISP 4 is turn-on[33-39], the negative terminal of

load is connecting with ground. Remaining switches are turn-off[40-45]; the voltage

joined with the heap terminals is Vs. The flow of current in this stage is appeared in the

Figure 4.

Figure 4 Switching combination required to generate output voltage level Vs .

3.1.2Half-level positive output, Vs/2:

At whatever point DISP5, the assistant switch is turn-on, the positive terminal of switches

is joined with point A, through diodes D5 and D8, and when DISP 4 is turn-on, the

negative terminal of load is joined with ground. All other controlled switches are turn-off;

the voltage connected to the load terminals is Vs/2. The flow of current in this stage is

appeared in Figure 5.

Figure 5 Switching combination required to generate output voltage level Vs/2

3.1.3. Zero output.


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Right when the two principle switches DISP 3 and DISP 4 are turn-on, the load terminals

is short circuited. All other controlled switches are turn-off; the voltage joined with the

load terminals is zero. Fig. 6 shows the current ways that are active at this stage.

Figure 6 Switching combination required to generate output voltage level zero.

3.1.4Half-level negative output,-Vs/ 2:

Exactly when the auxiliary switch, DISP 5 is turn-on, the positive terminal of load is

associated with point A, through diodes D6 and D7, and when the DISP 2 is turn-on, the

negative terminal of load is joined with Vs. All other controlled switches are turn-off; the

voltage associated with the load terminals is –Vs/2. Fig.7 shows the current ways that are

active at this stage.

Figure 7 Switching combination required to generate output voltage (-Vs/2)


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3.1.5 Maximum negative output:-

Exactly when DISP2 is turn-on, the load negative terminal is joined with Vs, and when

DISP3 is turn-on, the load positive terminal is associated with ground. All other controlled

switches are turn-off; the voltage associated with the load terminals is (- Vs). Fig. 8 shows

the current flow in this stage.

Figure 8 Switching combinations required to generate output voltage level (Vs)

3.2Advantages of Multilevel Inverter:-

i. Output voltage with extremely low distortion and lower dv/dt can be generated.

ii. Input current will be having very low distortion.

iii. It reduces the stress on the motor bearings.

iv. It operateson lower switching frequency.

v. Low EMI and Switching stress .

vi. They are suitable for medium and high power applications.


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4.SIMULATIONS H-BRIDGE FIVE LEVEL INVERTER

Figure 9 H-Bridge five level inverter

The above diagram shown is H-Bridge five level inverter circuits. It consists of five

switches. And we have used MOSFET (IRFZ44N) as switches. One digital simulator

(DSTM) is used here, which is of 8 bit. Because the number of bits to be stored is more

than 4 bits. This digital simulator is used to store the hexadecimal codes. And hence it

generates triggering pulses for MOSFETs. MCT2E, which is an opto-isolator, is also

connected between digital simulator and MOSFETs for isolation. Above circuit gives the

five level digital outputs.

V1

12v

0

IC= 110+

M2

IRF840

R6

500k

0V4

12v

0

U3

MCT2E

U1

MCT2E

M1

IRF840

R5

1k

D2

D1N5406

V2

12v

S8DSTM2

Implementation = lev el5

0

A1

M6

IRF840

A0

A4

D5

D1N5406

C1

2200u

V+A2

IC=-110

+

V5

12v

R4

1k

R2

1k

A3

V-

M5

IRF840

a[0..7]

V3

12v

M4

IRF840

C22200u

D4

D1N5406

D3

D1N5406

R3

1k

V6

110v

U4

MCT2E

0

R1

1k

U2

MCT2E

0

U5

MCT2E


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Figure 10 Simulation output for H-Bridge five level inverter

The above diagram shows the digital simulation output for H-Bridge five level inverter. In

the Analog simulation we got the five level output, but the output was not perfect. Analog

output was consisting of distortion, spikes and noises. That is because; in analog

simulation we have used both analog and digital components.But by using digital

simulation we get perfect output without any distortion, spikes and noises.

CONCLUSION

This paper proposed a new H bridge five level inverter for medium-voltage

applications.The various modules of H-Bridge inverter is described. Thismethodology

does not require an isolation transformer whichcan be developed in a cost-effective

manner. The PWM control algorithm is used to generate the switching pulse. The

performances of five level inverter topologies have been analyzed. The simulation of the

H bridge five level inverter was carried using pulse width modulation (PWM).The

simulation results shows that there is reduction in the voltage and current THD.

Time

0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms

V(D4:1,V2:-)

-120V

-80V

-40V

-0V

40V

80V

120V


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v.jayalakshmi , dr.s.prakash · 2 figure 1 block diagram 3. multilevel inverter the stepped...

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