vishwani d. agrawal james j. danaher professor ece department, auburn university

73
Spring 2010, Mar 11 . . . Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design ELEC 7770: Advanced VLSI Design (Agrawal) (Agrawal) 1 ELEC 7770: Advanced VLSI ELEC 7770: Advanced VLSI Design Design Spring 2010 Spring 2010 (Also, ELEC 7250 Class on March (Also, ELEC 7250 Class on March 11, 2010) 11, 2010) Radio Frequency (RF) Testing Radio Frequency (RF) Testing Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E77 70_Spr10

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ELEC 7770: Advanced VLSI Design Spring 2010 (Also, ELEC 7250 Class on March 11, 2010) Radio Frequency (RF) Testing. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] - PowerPoint PPT Presentation

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Page 1: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770: Advanced VLSI DesignELEC 7770: Advanced VLSI DesignSpring 2010Spring 2010

(Also, ELEC 7250 Class on March 11, 2010) (Also, ELEC 7250 Class on March 11, 2010)

Radio Frequency (RF) Testing Radio Frequency (RF) Testing

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10

Page 2: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

ReferencesReferences1.1. S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages

745-789, in 745-789, in System on Chip Test ArchSystem on Chip Test Architectures, edited by L.-T. Wang, itectures, edited by L.-T. Wang, C. E. Stroud and N. A. Touba, Amsterdam: Morgan-Kaufman, 2008.C. E. Stroud and N. A. Touba, Amsterdam: Morgan-Kaufman, 2008.

2.2. M. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI CircuitsDigital, Memory & Mixed-Signal VLSI Circuits, Boston: Springer, , Boston: Springer, 2000.2000.

3.3. J. Kelly and M. Engelhardt, J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, Advanced Production Testing of RF, SoC, and SiP Devicesand SiP Devices, Boston: Artech House, 2007., Boston: Artech House, 2007.

4.4. B. Razavi, B. Razavi, RF MicroelectronicsRF Microelectronics, Upper Saddle River, New Jersey: , Upper Saddle River, New Jersey: Prentice Hall PTR, 1998.Prentice Hall PTR, 1998.

5.5. J. Rogers, C. Plett and F. Dai, J. Rogers, C. Plett and F. Dai, Integrated Circuit Design for High-Integrated Circuit Design for High-Speed Frequency SynthesisSpeed Frequency Synthesis, Boston: Artech House, 2006., Boston: Artech House, 2006.

6.6. K. B. Schaub and J. Kelly, K. B. Schaub and J. Kelly, Production Testing of RF and System-on-Production Testing of RF and System-on-a-chip Devices for Wireless Communicationsa-chip Devices for Wireless Communications, Boston: Artech House, , Boston: Artech House, 2004.2004.

22ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 3: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

An RF Communications SystemAn RF Communications System

33

Dup

lexe

r

LNA

PA

LO

LO

LO

VGA

VGA

PhaseSplitter

PhaseSplitter

Dig

ital S

igna

l Pro

cess

or (

DS

P)

ADC

ADC

DAC

DAC

90°

90°

RF IF BASEBAND

Superheterodyne Transceiver

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 4: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

An Alternative RF Communications SystemAn Alternative RF Communications System

44

Dup

lexe

rLNA

PA

LO

LO

PhaseSplitter

PhaseSplitter

Dig

ital S

igna

l Pro

cess

or (

DS

P)

ADC

ADC

DAC

DAC

90°

90°

RF BASEBAND

Zero-IF (ZIF) Transceiver

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 5: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Components of an RF SystemComponents of an RF System Radio frequencyRadio frequency

DuplexerDuplexer LNA: Low noise amplifierLNA: Low noise amplifier PA: Power amplifierPA: Power amplifier RF mixerRF mixer Local oscillatorLocal oscillator FilterFilter

Intermediate Intermediate frequencyfrequency

VGA: Variable gain VGA: Variable gain amplifieramplifier

ModulatorModulator DemodulatorDemodulator FilterFilter

Mixed-signalMixed-signal ADC: Analog to digital ADC: Analog to digital

converterconverter DAC: Digital to analog DAC: Digital to analog

converterconverter

DigitalDigital Digital signal processor Digital signal processor

(DSP)(DSP)

55ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 6: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

LNA: Low Noise AmplifierLNA: Low Noise Amplifier Amplifies received RF signalAmplifies received RF signal Typical characteristics:Typical characteristics:

Noise figureNoise figure 2dB2dB IP3IP3 – 10dBm– 10dBm GainGain 15dB15dB Input and output impedanceInput and output impedance 5050ΩΩ Reverse isolationReverse isolation 20dB20dB Stability factorStability factor > 1> 1

Technologies:Technologies: BipolarBipolar CMOSCMOS

Reference: Razavi, Chapter 6.Reference: Razavi, Chapter 6.

66ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 7: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

PA: Power AmplifierPA: Power Amplifier Feeds RF signal to antenna for transmissionFeeds RF signal to antenna for transmission Typical characteristics:Typical characteristics:

Output powerOutput power +20 to +30 dBm+20 to +30 dBm EfficiencyEfficiency 30% to 60%30% to 60% IMDIMD – 30dBc– 30dBc Supply voltageSupply voltage 3.8 to 5.8 V3.8 to 5.8 V GainGain 20 to 30 dB20 to 30 dB Output harmonicsOutput harmonics – 50 to – 70 dBc– 50 to – 70 dBc Power controlPower control On-off or 1-dB stepsOn-off or 1-dB steps Stability factorStability factor > 1> 1

Technologies:Technologies: GaAsGaAs SiGeSiGe

Reference: Razavi, Chapter 9.Reference: Razavi, Chapter 9.77ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 8: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Mixer or Frequency (Up/Down) ConverterMixer or Frequency (Up/Down) Converter

Translates frequency by adding or subtracting Translates frequency by adding or subtracting local oscillator (LO) frequencylocal oscillator (LO) frequency

Typical characteristics:Typical characteristics: Noise figureNoise figure 12dB12dB IP3IP3 +5dBm+5dBm GainGain 10dB10dB Input impedanceInput impedance 5050ΩΩ Port to port isolationPort to port isolation 10-20dB10-20dB

Tecnologies:Tecnologies: BipolarBipolar MOSMOS

Reference: Razavi, Chapter 6.Reference: Razavi, Chapter 6.88

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 9: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

LO: Local OscillatorLO: Local Oscillator

Provides signal to mixer for down conversion or Provides signal to mixer for down conversion or upconversion.upconversion.

Implementations:Implementations: Tuned feedback amplifierTuned feedback amplifier Ring oscillatorRing oscillator Phase-locked loop (PLL)Phase-locked loop (PLL) Direct digital synthesizer (DDS)Direct digital synthesizer (DDS)

99ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 10: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

SOC: System-on-a-ChipSOC: System-on-a-Chip All components of a system are implemented on All components of a system are implemented on

the same VLSI chip.the same VLSI chip. Requires same technology (usually CMOS) Requires same technology (usually CMOS)

used for all components.used for all components. Components not implemented on present-day Components not implemented on present-day

SOC:SOC: AntennaAntenna Power amplifier (PA)Power amplifier (PA)

1010ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 11: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

RF TestsRF Tests

Basic testsBasic tests Scattering parameters (S-parameters)Scattering parameters (S-parameters) Frequency and gain measurementsFrequency and gain measurements Power measurementsPower measurements Power efficiency measurementsPower efficiency measurements

Distortion measurementsDistortion measurements Noise measurementsNoise measurements

1111ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 12: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Scattering Parameters (S-Parameters)Scattering Parameters (S-Parameters) An RF function is a two-port device withAn RF function is a two-port device with

Characteristic impedance (Characteristic impedance (ZZ00):):

ZZ00 = 50 = 50ΩΩ for wireless communications devices for wireless communications devices

ZZ00 = 75 = 75ΩΩ for cable TV devices for cable TV devices

Gain and frequency characteristicsGain and frequency characteristics

S-Parameters of an RF deviceS-Parameters of an RF device SS1111 : input return loss or input reflection coefficient : input return loss or input reflection coefficient

SS2222 : output return loss or output reflection coefficient : output return loss or output reflection coefficient

SS2121 : gain or forward transmission coefficient : gain or forward transmission coefficient

SS12 12 : isolation or reverse transmission coefficient : isolation or reverse transmission coefficient

S-Parameters are complex numbers and can be S-Parameters are complex numbers and can be expressed in decibels as 20 × log | Sexpressed in decibels as 20 × log | S ijij | | 1212ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 13: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Active or Passive RF DeviceActive or Passive RF Device

1313

RFDevice

Port 1(input)

Port 2(output)

a1 a2

b1 b2

Input return loss S11 = b1/a1

Output return loss S22 = b2/a2

Gain S21 = b2/a1

Isolation S12 = b1/a2

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 14: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

S-Parameter Measurement by Network AnalyzerS-Parameter Measurement by Network Analyzer

1414

a1

b1

Digitizer

Directional couplers

a2

b2

Digitizer

Directional couplers

DUT

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 15: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Application of S-Parameter: Input Application of S-Parameter: Input MatchMatch

Example: In an S-parameter measurement Example: In an S-parameter measurement setup, rms value of input voltage is 0.1V and the setup, rms value of input voltage is 0.1V and the rms value of the reflected voltage wave is 0.02V. rms value of the reflected voltage wave is 0.02V. Assume that the output of DUT is perfectly Assume that the output of DUT is perfectly matched. Then Smatched. Then S1111 determines the determines the input matchinput match::

SS1111 = 0.02/0.1 = 0.2, or 20 × log (0.2) = –14 dB. = 0.02/0.1 = 0.2, or 20 × log (0.2) = –14 dB.

Suppose the required input match is –10 dB; this Suppose the required input match is –10 dB; this device passes the test.device passes the test.

Similarly, SSimilarly, S2222 determines the output match. determines the output match.

1515ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 16: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Gain (SGain (S2121) and Gain Flatness) and Gain Flatness An amplifier of a Bluetooth transmitter operates over a An amplifier of a Bluetooth transmitter operates over a

frequency band 2.4 – 2.5GHz. It is required to have a gain of frequency band 2.4 – 2.5GHz. It is required to have a gain of 20dB and a gain flatness of 1dB.20dB and a gain flatness of 1dB.

Test: Under properly matched conditions, STest: Under properly matched conditions, S2121 is measured at is measured at

several frequencies in the range of operation:several frequencies in the range of operation:

SS2121 = 15.31 at 2.400GHz = 15.31 at 2.400GHz

SS2121 = 14.57 at 2.499GHz = 14.57 at 2.499GHz

From the measurements:From the measurements: At 2.400GHz, Gain = 20×log 15.31 = 23.70 dBAt 2.400GHz, Gain = 20×log 15.31 = 23.70 dB At 2.499GHz, Gain = 20×log 14.57 = 23.27 dBAt 2.499GHz, Gain = 20×log 14.57 = 23.27 dB

Result: Gain and gain flatness meet specification. Result: Gain and gain flatness meet specification. Measurements at more frequencies in the range may be Measurements at more frequencies in the range may be useful.useful.

1616ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 17: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Power MeasurementsPower Measurements ReceiverReceiver

Minimum detectable RF powerMinimum detectable RF power Maximum allowed input powerMaximum allowed input power Power levels of interfering tonesPower levels of interfering tones

TransmitterTransmitter Maximum RF power outputMaximum RF power output Changes in RF power when automatic gain control is usedChanges in RF power when automatic gain control is used RF power distribution over a frequency bandRF power distribution over a frequency band Power-added efficiency (PAE)Power-added efficiency (PAE)

Power unit: dBm, relative to 1mWPower unit: dBm, relative to 1mW Power in dBmPower in dBm = 10 × log (power in watts/0.001 watts)= 10 × log (power in watts/0.001 watts) Example: 1 W is 10×log 1000 = 30 dBmExample: 1 W is 10×log 1000 = 30 dBm What is 2 W in dBm?What is 2 W in dBm?

1717ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 18: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Harmonic MeasurementsHarmonic Measurements

Multiples of the carrier frequency are called Multiples of the carrier frequency are called harmonics.harmonics.

Harmonics are generated due to nonlinearity in Harmonics are generated due to nonlinearity in semiconductor devices and clipping (saturation) semiconductor devices and clipping (saturation) in amplifiers.in amplifiers.

Harmonics may interfere with other signals and Harmonics may interfere with other signals and must be measured to verify that a manufactured must be measured to verify that a manufactured device meets the specification.device meets the specification.

1818ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 19: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Power-Added Efficiency (PAE)Power-Added Efficiency (PAE) Definition: Power-added efficiency of an RF amplifier is Definition: Power-added efficiency of an RF amplifier is

the ratio of RF power generated by the amplifier to the DC the ratio of RF power generated by the amplifier to the DC power supplied:power supplied:

PAE = PAE = ΔΔPPRFRF / P / PDCDC where where ΔPΔPRFRF == PPRFRF(output) – P(output) – PRFRF(input)(input)

PPdcdc == VVsupply supply × I× Isupplysupply

Important for power amplifier (PA).Important for power amplifier (PA). 1 – PAE is a measure of heat generated in the amplifier, 1 – PAE is a measure of heat generated in the amplifier,

i.e., the battery power that is wasted.i.e., the battery power that is wasted. In mobile phones PA consumes most of the power. A low In mobile phones PA consumes most of the power. A low

PAE reduces the usable time before battery recharge.PAE reduces the usable time before battery recharge.

1919ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 20: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

PAE ExamplePAE Example Following measurements are obtained for an RF Following measurements are obtained for an RF

power amplifier:power amplifier: RF Input powerRF Input power == +2dBm+2dBm RF output powerRF output power == +34dBm+34dBm DC supply voltageDC supply voltage == 3V3V DUT currentDUT current == 2.25A2.25A

PAE is calculated as follows:PAE is calculated as follows: PPRFRF(input)(input) = 0.001 × 10= 0.001 × 102/102/10 = 0.0015W= 0.0015W

PPRFRF(output)(output) = 0.001 × 10= 0.001 × 1034/1034/10 = 2.5118W= 2.5118W

PPdcdc = 3× 2.25= 3× 2.25 = 6.75W= 6.75W

PAEPAE = (2.5118 – 0.00158)/6.75 = 0.373 or 37.2%= (2.5118 – 0.00158)/6.75 = 0.373 or 37.2%

2020ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 21: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Distortion and LinearityDistortion and Linearity An unwanted change in the signal behavior is An unwanted change in the signal behavior is

usually referred to as usually referred to as distortiondistortion.. The cause of distortion is nonlinearity of The cause of distortion is nonlinearity of

semiconductor devices constructed with diodes and semiconductor devices constructed with diodes and transistors.transistors.

Linearity:Linearity: Function f(x) = ax + b, although a straight-line is not Function f(x) = ax + b, although a straight-line is not

referred to as a linear function.referred to as a linear function. Definition: A linear function must satisfy:Definition: A linear function must satisfy:

f(x + y) = f(x) + f(y), andf(x + y) = f(x) + f(y), and f(ax) = a f(x), for all scalar constants af(ax) = a f(x), for all scalar constants a

2121ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 22: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Linear and Nonlinear FunctionsLinear and Nonlinear Functions

2222

x

f(x)

slope = a

b

f(x) = ax + b

x

f(x)

b

f(x) = ax2 + b

x

f(x)

slope = a

f(x) = axELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 23: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Generalized Transfer FunctionGeneralized Transfer Function Transfer function of an electronic circuit is, in Transfer function of an electronic circuit is, in

general, a nonlinear function.general, a nonlinear function. Can be represented as a polynomial:Can be represented as a polynomial:

vvoo = a = a00 + a + a11 v vii + a + a22 v vii22 + a + a33 v vii

33 + · · · · + · · · ·

Constant term aConstant term a00 is the dc component that in RF is the dc component that in RF

circuits is usually removed by a capacitor or high-pass circuits is usually removed by a capacitor or high-pass filter.filter.

For a linear circuit, aFor a linear circuit, a22 = a = a33 = · · · · = 0. = · · · · = 0.

2323

Electronic

circuitvovi

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 24: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Effect of Nonlinearity on FrequencyEffect of Nonlinearity on Frequency Consider a transfer function, vConsider a transfer function, voo = a = a00 + a + a11 v vii + a + a22 v vii

22 + a + a33 v vii33

Let vLet vii = A cos = A cos ωωtt

Using the identities (Using the identities (ωω = 2 = 2ππf):f): coscos22 ωωt = (1 + cos 2t = (1 + cos 2ωωt)/2t)/2 coscos33 ωωt = (3 cos t = (3 cos ωωt + cos 3t + cos 3ωωt)/4t)/4

We get,We get,

vvoo == aa00 + a + a22AA22/2 + (a/2 + (a11A + 3aA + 3a33AA33/4) cos /4) cos ωωtt

+ (a+ (a22AA22/2) cos 2/2) cos 2ωωt + (at + (a33AA33/4) cos /4) cos

33ωωtt

2424ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 25: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem for SolutionProblem for Solution A diode characteristic is, I = IA diode characteristic is, I = Iss ( e ( eααVV – 1) – 1)

Where, V = VWhere, V = V00 + v + vinin, V, V00 is dc voltage and v is dc voltage and v inin is small signal ac is small signal ac

voltage. Ivoltage. Iss is saturation current and is saturation current and αα is a constant that is a constant that

depends on temperature and design parameters of diode.depends on temperature and design parameters of diode. Using the Taylor series expansion, express the diode current I Using the Taylor series expansion, express the diode current I

as a polynomial in vas a polynomial in vinin..

2525

V

I

0

– Is

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 26: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Linear and Nonlinear Circuits and Linear and Nonlinear Circuits and SystemsSystems

Linear devices:Linear devices: All frequencies in the output of a device are related to input by All frequencies in the output of a device are related to input by

a proportionality, or weighting factor, independent of power a proportionality, or weighting factor, independent of power level.level.

No frequency will appear in the output, that was not present in No frequency will appear in the output, that was not present in the input.the input.

Nonlinear devices:Nonlinear devices: A true linear device is an idealization. Most electronic devices A true linear device is an idealization. Most electronic devices

are nonlinear.are nonlinear. Nonlinearity in amplifier is undesirable and causes distortion Nonlinearity in amplifier is undesirable and causes distortion

of signal.of signal. Nonlinearity in mixer or frequency converter is essential.Nonlinearity in mixer or frequency converter is essential.

2626ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 27: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Types of Distortion and Their TestsTypes of Distortion and Their Tests

Types of distortion:Types of distortion: Harmonic distortion: single-tone testHarmonic distortion: single-tone test Gain compression: single-tone testGain compression: single-tone test Intermodulation distortion: two-tone or multitone testIntermodulation distortion: two-tone or multitone test

Testing procedure: Output spectrum Testing procedure: Output spectrum measurementmeasurement

2727ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 28: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Harmonic DistortionHarmonic Distortion Harmonic distortion is the presence of multiples of a Harmonic distortion is the presence of multiples of a

fundamental frequency of interest. fundamental frequency of interest. NN times the times the fundamental frequency is called fundamental frequency is called NNth harmonic.th harmonic.

Disadvantages:Disadvantages: Waste of power in harmonics.Waste of power in harmonics. Interference from harmonics.Interference from harmonics.

Measurement:Measurement: Single-frequency input signal applied.Single-frequency input signal applied. Amplitudes of the fundamental and harmonic Amplitudes of the fundamental and harmonic

frequencies are analyzed to quantify distortion as:frequencies are analyzed to quantify distortion as: Total harmonic distortion (THD)Total harmonic distortion (THD) Signal, noise and distortion (SINAD)Signal, noise and distortion (SINAD)

2828ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 29: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem for SolutionProblem for Solution

Show that for a nonlinear device with a single Show that for a nonlinear device with a single frequency input of amplitude frequency input of amplitude AA, the , the nnth harmonic th harmonic component in the output always contains a term component in the output always contains a term proportional to proportional to AAnn..

2929ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 30: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Total Harmonic Distortion (THD)Total Harmonic Distortion (THD) THD is the total power contained in all harmonics of a signal THD is the total power contained in all harmonics of a signal

expressed as percentage (or ratio) of the fundamental signal expressed as percentage (or ratio) of the fundamental signal power.power.

THD(%) = [(PTHD(%) = [(P22 + P + P33 + · · · ) / P + · · · ) / Pfundamentalfundamental ] × 100% ] × 100%

Or THD(%) = [(VOr THD(%) = [(V2222 + V + V33

22 + · · · ) / V + · · · ) / V22fundamentalfundamental ] × 100% ] × 100%

Where PWhere P22, P, P33, . . . , are the power in watts of second, third, . . . , , . . . , are the power in watts of second, third, . . . ,

harmonics, respectively, and Pharmonics, respectively, and Pfundamentalfundamental is the fundamental signal power, is the fundamental signal power,

And VAnd V22, V, V33, . . . , are voltage amplitudes of second, third, . . . , , . . . , are voltage amplitudes of second, third, . . . ,

harmonics, respectively, and Vharmonics, respectively, and Vfundamentalfundamental is the fundamental signal is the fundamental signal

amplitude.amplitude.

Also, THD(dB) = 10 log THD(%)Also, THD(dB) = 10 log THD(%) For an ideal distortionless signal, THD = 0% or – ∞ dBFor an ideal distortionless signal, THD = 0% or – ∞ dB

3030ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 31: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

THD MeasurementTHD Measurement

THD is specified typically for devices with RF THD is specified typically for devices with RF output.output.

Separate power measurements are made for the Separate power measurements are made for the fundamental and each harmonic.fundamental and each harmonic.

THD is tested at specified power level becauseTHD is tested at specified power level because THD may be small at low power levels.THD may be small at low power levels. Harmonics appear when the output power of an RF Harmonics appear when the output power of an RF

device is raised.device is raised.

3131ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 32: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Gain CompressionGain Compression The harmonics produced due to nonlinearity in an The harmonics produced due to nonlinearity in an

amplifier reduce the fundamental frequency power amplifier reduce the fundamental frequency power output (and gain). This is known as output (and gain). This is known as gain gain compressioncompression..

As input power increases, so does nonlinearity As input power increases, so does nonlinearity causing greater gain compression.causing greater gain compression.

A standard measure of Gain compression is “1-dB A standard measure of Gain compression is “1-dB compression point” power level Pcompression point” power level P1dB1dB, which can be, which can be Input referred Input referred for receiver, orfor receiver, or Output referred Output referred for transmitterfor transmitter

3232ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 33: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Linear Operation: No Gain Linear Operation: No Gain CompressionCompression

3333

time time

LNAor PA

Am

plitu

de

Am

plitu

de

frequency

Pow

er (

dBm

)

f1

frequencyP

ower

(dB

m)

f1

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 34: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Cause of Gain Compression: Cause of Gain Compression: ClippingClipping

3434

time time

LNAor PA

Am

plitu

de

Am

plitu

de

frequency

Pow

er (

dBm

)

f1

frequencyP

ower

(dB

m)

f1 f2 f3

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 35: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Effect of NonlinearityEffect of Nonlinearity Assume a transfer function, vAssume a transfer function, voo = a = a00 + a + a11 v vii + a + a2 2 vvii

22

+ a+ a33 v vii33

Let vLet vii = A cos = A cos ωωtt

Using the identities (Using the identities (ωω = 2 = 2ππf):f): coscos22 ωωt = (1 + cos 2t = (1 + cos 2ωωt)/2t)/2 coscos33 ωωt = (3 cos t = (3 cos ωωt + cos 3t + cos 3ωωt)/4t)/4

We get,We get, vvoo = = aa00 + a + a22AA22/2 + (a/2 + (a11A + 3aA + 3a33AA33/4) cos /4) cos ωωtt

+ (a+ (a22AA22/2) cos 2/2) cos 2ωωt + (at + (a33AA33/4) cos /4) cos

33ωωtt

3535ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 36: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Gain Compression AnalysisGain Compression Analysis

DC term is filtered out.DC term is filtered out. For small-signal input, A is smallFor small-signal input, A is small

AA22 and A and A33 terms are neglected terms are neglected

vvoo = a = a11A cos A cos ωωt, small-signal gain, Gt, small-signal gain, G00 = a = a11

Gain at 1-dB compression point, GGain at 1-dB compression point, G1dB1dB = G = G00 – 1 – 1

Input referred and output referred 1-dB power:Input referred and output referred 1-dB power:

PP1dB(output)1dB(output) – P – P1dB(input)1dB(input) = G = G1dB1dB = G = G00 – 1 – 1

3636 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 37: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

1-dB Compression Point1-dB Compression Point

3737

1 dB

Input power (dBm)

Out

put

pow

er (

dBm

)

1 dBCompression

point

P1dB(input)

P1d

B(o

utpu

t)

Slope

= ga

in

Linear region(small-signal)

Compressionregion

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 38: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Testing for Gain CompressionTesting for Gain Compression Apply a single-tone input signal:Apply a single-tone input signal:

1.1. Measure the gain at a power level where DUT is Measure the gain at a power level where DUT is linear.linear.

2.2. Extrapolate the linear behavior to higher power Extrapolate the linear behavior to higher power levels.levels.

3.3. Increase input power in steps, measure the gain Increase input power in steps, measure the gain and compare to extrapolated values.and compare to extrapolated values.

4.4. Test is complete when the gain difference between Test is complete when the gain difference between steps 2 and 3 is 1dB.steps 2 and 3 is 1dB.

Alternative test: After step 2, conduct a binary Alternative test: After step 2, conduct a binary search for 1-dB compression point.search for 1-dB compression point.

3838ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 39: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Example: Gain Compression TestExample: Gain Compression Test

Small-signal gain, GSmall-signal gain, G00 = = 28dB28dB

Input-referred 1-dB compression point power level,Input-referred 1-dB compression point power level,

PP1dB(input)1dB(input) = = – 19 dBm– 19 dBm

We compute:We compute: 1-dB compression point Gain, G1-dB compression point Gain, G1dB1dB = 28 – 1 = 27 dB = 28 – 1 = 27 dB

Output-referred 1-dB compression point power level, Output-referred 1-dB compression point power level, PP1dB(output) 1dB(output) == PP1dB(input)1dB(input) + G + G1dB1dB

== – 19 + 27– 19 + 27

== 8 dBm8 dBm

3939ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 40: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Intermodulation DistortionIntermodulation Distortion Intermodulation distortion is relevant to devices that handle Intermodulation distortion is relevant to devices that handle

multiple frequencies.multiple frequencies.

Consider an input signal with two frequencies Consider an input signal with two frequencies ωω11 and and ωω22::

vvii = A cos = A cos ωω11t + B cos t + B cos ωω22tt

Nonlinearity in the device function is represented byNonlinearity in the device function is represented by

vvoo = a = a00 + a + a11 v vii + a + a22 v vii22 + a + a33 v vii

33, , neglecting higher order termsneglecting higher order terms

Therefore, device output isTherefore, device output is

vvoo = a = a00 + a + a11 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t) DC and fundamentalDC and fundamental

+ a+ a22 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t)22 22ndnd order terms order terms

+ a+ a33 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t)33 33rdrd order terms order terms

4040ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 41: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problems to SolveProblems to Solve Derive the following:Derive the following:

vvoo = = aa00 + a + a11 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t)

+ a+ a22 [ A [ A22 (1+cos 2 (1+cos 2ωω11t)/2 + AB cos (t)/2 + AB cos (ωω11++ωω22)t )t

+ AB cos (+ AB cos (ωω1 1 – – ωω22)t + B)t + B22 (1+cos 2 (1+cos 2ωω22t)/2 ]t)/2 ]

+ a+ a33 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t)33

Hint: Use the identity:Hint: Use the identity: cos cos αα cos cos ββ = [cos( = [cos(αα + + ββ) + cos() + cos(αα – – ββ)] / 2)] / 2

Simplify aSimplify a33 (A cos (A cos ωω11t + B cos t + B cos ωω22t)t)33

4141ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 42: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Two-Tone Distortion ProductsTwo-Tone Distortion Products Order for distortion product mfOrder for distortion product mf11 ± nf ± nf22 is |m| + |n| is |m| + |n|

4242

Nunber of distortion products Frequencies

Order Harmonic Intermod. Total Harmonic Intrmodulation

2 2 2 4 2f1 , 2f2 f1 + f2, f2 – f1

3 2 4 6 3f1 , 3f2 2f1 ± f2, 2f2 ± f1

4 2 6 8 4f1 , 4f2

2f1 ± 2f2, 2f2 – 2f1,3f1 ± f2, 3f2 ± f1

5 2 8 10 5f1 , 5f2

3f1 ± 2f2, 3f2 ± 2f1,4f1 ± f2, 4f2 ± f1

6 2 10 12 6f1 , 6f2

3f1 ± 3f2, 3f2 – 3f1, 5f1 ± f2, 5f2 ± f1, 4f1 ± 2f2, 4f2 ± 2f1

7 2 12 14 7f1 , 7f2

4f1 ± 3f2, 4f2 – 3f1, 5f1 ± 2f2, 5f2 ± 2f1, 6f1 ± f2, 6f2 ± f1

N 2 2N – 2 2N Nf1 , Nf2 . . . . .

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 43: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem to SolveProblem to SolveWrite Distortion products tones 100MHz and 101MHz

OrderHarmonics

(MHz)Intermodulation products (MHz)

2 200, 202 1, 201

3 300, 303 99, 102, 301, 302

4 400, 404 2, 199, 203, 401, 402, 403

5 500, 505 98, 103, 299, 304, 501, 503, 504

6 600, 6063, 198, 204, 399, 400, 405, 601, 603, 604, 605

7 700, 70797, 104, 298, 305, 499, 506, 701, 707, 703, 704, 705, 706

4343

Intermodulation products close to input tones are shown in bold.

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 44: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Second-Order Intermodulation Second-Order Intermodulation DistortionDistortion

4444

frequency

DUTAm

plitu

de

f1 f2

frequency

Am

plitu

de

f1 f2 2f1 2f2

f 2 –

f1

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 45: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Higher-Order Intermodulation Higher-Order Intermodulation DistortionDistortion

4545

frequency

DUTAm

plitu

de

f1 f2

frequency

Am

plitu

de

f1 f2 2f1 2f2 3f1 3f2

2f1

– f 2

2f2

– f 1

Third-order intermodulationdistortion products (IMD3)

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 46: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem to SolveProblem to Solve For A = B, i.e., for two input tones of equal For A = B, i.e., for two input tones of equal

magnitudes, show that:magnitudes, show that: Output amplitude of each fundamental frequency, fOutput amplitude of each fundamental frequency, f11

or for f22 , is , is

99aa11 A + — a A + — a33 A A33 ≈ ≈ aa11 A A

44 Output amplitude of each third-order intermodulation Output amplitude of each third-order intermodulation

frequency, 2ffrequency, 2f11 – f – f22 or 2f or 2f22 – f – f11 , is , is

33— — aa33 A A33

444646

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 47: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Third-Order Intercept Point (IP3)Third-Order Intercept Point (IP3) IP3 is the power level of the fundamental for which the IP3 is the power level of the fundamental for which the

output of each fundamental frequency equals the output output of each fundamental frequency equals the output of the closest third-order intermodulation frequency.of the closest third-order intermodulation frequency.

IP3 is a figure of merit that quantifies the third-order IP3 is a figure of merit that quantifies the third-order intermodulation distortion.intermodulation distortion.

Assuming aAssuming a11 >> 9a >> 9a33 A A22 /4, IP3 is given by /4, IP3 is given by

aa11 IP3 = 3a IP3 = 3a33 IP3 IP333 / 4 / 4

IP3 = [4aIP3 = [4a11 /(3a /(3a33 )] )]1/21/2

4747

a1 A3a3 A3 / 4

A

Out

put

IP3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 48: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Test for IP3Test for IP3 Select two test frequencies, fSelect two test frequencies, f11 and f and f22, applied in equal , applied in equal

magnitude to the input of DUT.magnitude to the input of DUT.

Increase input power PIncrease input power P0 0 (dBm) until the third-order products (dBm) until the third-order products

are well above the noise floor.are well above the noise floor.

Measure output power PMeasure output power P11 in dBm at any fundamental in dBm at any fundamental

frequency and Pfrequency and P33 in dBm at a third-order intermodulation in dBm at a third-order intermodulation

frquency.frquency.

Output-referenced IP3:Output-referenced IP3: OIP3 OIP3 = = PP11 + (P + (P11 – P – P33) / 2 ) / 2

Input-referenced IP3:Input-referenced IP3: IIP3 IIP3 = = PP00 + (P + (P11 – P – P33) / 2 ) / 2

== OIP3 – GOIP3 – G

Because, Gain for fundamental frequency, G = PBecause, Gain for fundamental frequency, G = P1 1 – P– P00

4848ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 49: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

IP3 GraphIP3 Graph

4949

f1 or f2

20 log a1 Aslope = 1

Input power = 20 log A dBm

Out

put

pow

er (

dBm

)

2f1 – f2 or 2f2 – f1

20 log (3a3 A3 /4)slope = 3

OIP3

IIP3

P1

P3

P0

(P1 – P3)/2

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 50: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Example: IP3 of an RF LNAExample: IP3 of an RF LNA Gain of LNA = 20 dBGain of LNA = 20 dB RF signal frequencies: 2140.10MHz and 2140.30MHzRF signal frequencies: 2140.10MHz and 2140.30MHz Second-order intermodulation distortion: 400MHz; outside Second-order intermodulation distortion: 400MHz; outside

operational band of LNA.operational band of LNA. Third-order intermodulation distortion: 2140.50MHz; within the Third-order intermodulation distortion: 2140.50MHz; within the

operational band of LNA.operational band of LNA. Test:Test:

Input power, PInput power, P00 = – 30 dBm, for each fundamental frequency = – 30 dBm, for each fundamental frequency

Output power, POutput power, P11 = – 30 + 20 = – 10 dBm = – 30 + 20 = – 10 dBm

Measured third-order intermodulation distortion power, PMeasured third-order intermodulation distortion power, P33 = – 84 dBm = – 84 dBm

OIP3 = – 10 + [( – 10 – ( – 84))] / 2 = + 27 dBmOIP3 = – 10 + [( – 10 – ( – 84))] / 2 = + 27 dBm IIP3 = – 10 + [( – 10 – ( – 84))] / 2 – 20 = + 7 dBmIIP3 = – 10 + [( – 10 – ( – 84))] / 2 – 20 = + 7 dBm

5050ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 51: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

What is Noise?What is Noise?

Noise in an RF system is unwanted random fluctuations in a desired Noise in an RF system is unwanted random fluctuations in a desired signal.signal.

Noise is a natural phenomenon and is always present in the Noise is a natural phenomenon and is always present in the environment.environment.

Effects of noise:Effects of noise: Interferes with detection of signal (hides the signal).Interferes with detection of signal (hides the signal). Causes errors in information transmission by changing signal.Causes errors in information transmission by changing signal. Sometimes noise might imitate a signal falsely.Sometimes noise might imitate a signal falsely.

All communications system design and operation must account for All communications system design and operation must account for noise.noise.

5151ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 52: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Describing NoiseDescribing Noise

Consider noise as a random voltage or current Consider noise as a random voltage or current function, x(t), over interval – T/2 < t < T/2.function, x(t), over interval – T/2 < t < T/2.

Fourier transform of x(t) is XFourier transform of x(t) is XTT(f).(f).

Power spectral density (PSD) of noise is power Power spectral density (PSD) of noise is power across 1across 1ΩΩ

SSxx(f) = (f) = lim [ E{ |Xlim [ E{ |XTT(f)|(f)|2 2 } / (2T) ]} / (2T) ]

voltsvolts22/Hz/Hz

T→∞T→∞

This is also expressed in dBm/Hz.This is also expressed in dBm/Hz.

5252ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 53: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Thermal NoiseThermal Noise Thermal (Johnson) noise: Caused by random movement Thermal (Johnson) noise: Caused by random movement

of electrons due to thermal energy that is proportional to of electrons due to thermal energy that is proportional to temperature.temperature.

Called white noise due to uniform PSD over all Called white noise due to uniform PSD over all frequencies.frequencies.

Mean square open circuit noise voltage across R Mean square open circuit noise voltage across R ΩΩ resistor [Nyquist, 1928]:resistor [Nyquist, 1928]:

vv22 == 4hfBR / [exp(hf/kT) – 1]4hfBR / [exp(hf/kT) – 1] WhereWhere

Plank’s constant h = 6.626 × 10Plank’s constant h = 6.626 × 103434 J-sec J-sec Frequency and bandwidth in hertz = f, BFrequency and bandwidth in hertz = f, B Boltzmann’s constant k = 1.38 Boltzmann’s constant k = 1.38 ×× 10 10 – 23 – 23 J/K J/K Absolute temperature in Kelvin = TAbsolute temperature in Kelvin = T

5353

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 54: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem to SolveProblem to Solve Given that for microwave frequencies, hf << kT, derive Given that for microwave frequencies, hf << kT, derive

the following Rayleigh-Jeans approximation:the following Rayleigh-Jeans approximation:

vv22 == 4kTBR4kTBR Show that at room temperature (T = 290K), thermal noise Show that at room temperature (T = 290K), thermal noise

power supplied by resistor R to a matched load is ktB or power supplied by resistor R to a matched load is ktB or – 174 dBm/Hz.– 174 dBm/Hz.

5454

v = (4kTBR)1/2

R

R

Noisyresistor Matched

load

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 55: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Other Noise TypesOther Noise Types Shot noise [Schottky, 1928]: Broadband noise due to random Shot noise [Schottky, 1928]: Broadband noise due to random

behavior of charge carriers in semiconductor devices.behavior of charge carriers in semiconductor devices. Flicker (1/f) noise: Low-frequency noise in semiconductor devices, Flicker (1/f) noise: Low-frequency noise in semiconductor devices,

perhaps due to material defects; power spectrum falls off as 1/f. Can perhaps due to material defects; power spectrum falls off as 1/f. Can be significant at audio frequencies.be significant at audio frequencies.

Quantization noise: Caused by conversion of continuous valued Quantization noise: Caused by conversion of continuous valued analog signal to discrete-valued digital signal; minimized by using analog signal to discrete-valued digital signal; minimized by using more digital bits.more digital bits.

Quantum noise: Broadband noise caused by the quantized nature of Quantum noise: Broadband noise caused by the quantized nature of charge carriers; significant at very low temperatures (~0K) or very charge carriers; significant at very low temperatures (~0K) or very high bandwidth ( > 10high bandwidth ( > 101515 Hz). Hz).

Plasma noise: Caused by random motion of charges in ionized Plasma noise: Caused by random motion of charges in ionized medium, possibly resulting from sparking in electrical contacts; medium, possibly resulting from sparking in electrical contacts; generally, not a concern.generally, not a concern.

5555 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 56: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Measuring NoiseMeasuring Noise Expressed as noise power density in the units of dBm/Hz.Expressed as noise power density in the units of dBm/Hz. Noise sources:Noise sources:

Resistor at constant temperature, noise power = kTB W/Hz.Resistor at constant temperature, noise power = kTB W/Hz. Avalanche diodeAvalanche diode

Noise temperature:Noise temperature: TTnn = (Available noise power in watts)/(kB) kelvins = (Available noise power in watts)/(kB) kelvins

Excess noise ratio (ENR) is the difference in the noise output Excess noise ratio (ENR) is the difference in the noise output between hot (on) and cold (off) states, normalized to between hot (on) and cold (off) states, normalized to reference thermal noise at room temperature (290K):reference thermal noise at room temperature (290K): ENR = [k( TENR = [k( Thh – T – Tc c )B]/(kT)B]/(kT00B) = ( TB) = ( Thh / T / T00) – 1) – 1

Where noise output in cold state is takes same as reference.Where noise output in cold state is takes same as reference. 10 log ENR ~ 15 to 20 dB10 log ENR ~ 15 to 20 dB

5656ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 57: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Signal-to-Noise Ratio (SNR)Signal-to-Noise Ratio (SNR) SNR is the ratio of signal power to noise power.SNR is the ratio of signal power to noise power.

5757

Input signal: low peak power,good SNR

Si/Ni

Output signal: high peak power,poor SNR

So/NoG

Noise floor

Frequency (Hz)

Po

we

r (d

Bm

)

GSi/Ni So/No

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 58: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Noise Factor and Noise FigureNoise Factor and Noise Figure Noise factor (F) is the ratio of input SNR to output SNR:Noise factor (F) is the ratio of input SNR to output SNR:

F = (SF = (Sii /N /Nii) / (S) / (Soo /N /Noo))

= N= Noo / ( GN / ( GNii ), when S ), when Sii = 1W and G = gain of DUT = 1W and G = gain of DUT

= N= Noo /( kT /( kT00 BG), when N BG), when Nii = kT = kT00 B for input noise B for input noise

sourcesource F ≥ 1F ≥ 1

Noise figure (NF) is noise factor expressed in dB:Noise figure (NF) is noise factor expressed in dB: NF = 10 log F dBNF = 10 log F dB 0 ≤ NF ≤ ∞0 ≤ NF ≤ ∞

5858ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 59: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Cascaded System Noise FactorCascaded System Noise Factor Friis equation [Proc. IRE, July 1944, pp. 419 – 422]:Friis equation [Proc. IRE, July 1944, pp. 419 – 422]:

5959

F2 – 1 F3 – 1 Fn – 1Fsys = F1 + ——— + ——— + · · · · + ———————

G1 G1 G2 G1 G2 · · · Gn – 1

Gain = G1

Noise factor = F1

Gain = G2

Noise factor = F2

Gain = G3

Noise factor = F3

Gain = Gn

Noise factor = Fn

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Measuring Noise Figure: Cold Measuring Noise Figure: Cold Noise MethodNoise Method

Example: SOC receiver with large gain so noise output is Example: SOC receiver with large gain so noise output is measurable; noise power should be above noise floor of measurable; noise power should be above noise floor of measuring equipment.measuring equipment.

Gain G is known or previously measured.Gain G is known or previously measured.

Noise factor, F = NNoise factor, F = No o / (kT/ (kT00BG), whereBG), where NNoo is measured output noise power (noise floor) is measured output noise power (noise floor)

B is measurement bandwidthB is measurement bandwidth

At 290K, kTAt 290K, kT00 = – 174 dBm/Hz = – 174 dBm/Hz

Noise figure, NF = 10 log FNoise figure, NF = 10 log F

= N= Noo (dB) – ( – 174 dBm/Hz) – B(dB) – G(dB) (dB) – ( – 174 dBm/Hz) – B(dB) – G(dB)

This measurement is also done using S-parameters.This measurement is also done using S-parameters.6060ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

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Page 61: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Y – FactorY – Factor Y – factor is the ratio of output noise in hot (power on) state to that in cold (power Y – factor is the ratio of output noise in hot (power on) state to that in cold (power

off) state.off) state.

YY == NNh h / N/ Ncc

== NNhh / N / N00

Y is a simple ratio.Y is a simple ratio.

Consider, NConsider, Nh h = kT= kThhBG and NBG and Ncc = kT = kT00BGBG

Then NThen Nhh – N – Ncc = kBG( T = kBG( Thh – T – T00 ) or kBG = ( N ) or kBG = ( Nhh – N – Ncc ) / ( T ) / ( Thh – T – T00 ) )

Noise factor, F = Noise factor, F = NNhh /( kT /( kT00 BG) = ( N BG) = ( Nhh / T / T00 ) [ 1 / (kBG) ] ) [ 1 / (kBG) ]

== ( N ( Nhh / T / T00 ) ( T ) ( Thh – T – T00 ) / (N ) / (Nhh – N – Ncc ) )

== ENR / (Y – 1)ENR / (Y – 1)

6161ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

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Page 62: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Measuring Noise Factor: Y – Factor MethodMeasuring Noise Factor: Y – Factor Method

Noise source provides hot and cold noise power levels and is Noise source provides hot and cold noise power levels and is characterized by ENR (excess noise ratio).characterized by ENR (excess noise ratio).

Tester measures noise power, is characterized by its noise factor FTester measures noise power, is characterized by its noise factor F22

and Y-factor Yand Y-factor Y22..

Device under test (DUT) has gain GDevice under test (DUT) has gain G11 and noise factor F and noise factor F11..

Two-step measurement:Two-step measurement: Calibration: Connect noise source to tester, measure output Calibration: Connect noise source to tester, measure output

power for hot and cold noise inputs, compute Ypower for hot and cold noise inputs, compute Y22 and F and F22..

Measurement: Connect noise source to DUT and tester Measurement: Connect noise source to DUT and tester cascade, measure output power for hot and cold noise inputs, cascade, measure output power for hot and cold noise inputs, compute compute Ycompute compute Y1212, F, F12 12 and Gand G11..

Use Friis equation to obtain FUse Friis equation to obtain F11..

6262ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

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Page 63: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

CalibrationCalibration

YY22 = N = Nh2h2 / N / Nc2c2, where, where

NNh2h2 = measured power for hot source = measured power for hot source

NNc2 c2 = measured power for cold source= measured power for cold source

FF22 = ENR / (Y = ENR / (Y22 – 1) – 1)

6363

Noise sourceENR

Tester(power meter)

F2, Y2

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 64: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Cascaded System MeasurementCascaded System Measurement

YY1212 = N = Nh12h12 / N / Nc12c12, where, where

NNh12h12 = measured power for hot source = measured power for hot source

NNc12 c12 = measured power for cold source= measured power for cold source

FF1212 = ENR / ( Y = ENR / ( Y1212 – 1 ) – 1 )

GG11 = ( N = ( Nh12h12 – N – Nc12c12 ) / ( N ) / ( Nh2h2 – N – Nc2c2 ) )

6464

Noise sourceENR

Tester(power meter)

F2, Y2

DUTF1, Y1, G1

F12, Y12

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 65: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem to SolveProblem to Solve

Show that from noise measurements on a Show that from noise measurements on a cascaded system, the noise factor of DUT is cascaded system, the noise factor of DUT is given bygiven by

FF22 – 1 – 1

FF11 = F = F12 12 – – ——————

GG11

6565ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 66: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Phase NoisePhase Noise Phase noise is due to small random variations in the phase of an Phase noise is due to small random variations in the phase of an

RF signal. In time domain, phase noise is referred to as RF signal. In time domain, phase noise is referred to as jitterjitter.. Understanding phase:Understanding phase:

6666

φ

amplitudenoise

t t

V sin ωt [V + δ(t)] sin [ωt + φ(t)]

phasenoise

δ

Frequency (rad/s)ω

Frequency (rad/s)ω

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 67: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Effects of Phase NoiseEffects of Phase Noise Similar to phase modulation by a random signal.Similar to phase modulation by a random signal. Two types:Two types:

Long term phase variation is called Long term phase variation is called frequency driftfrequency drift.. ShShort term phase variation is ort term phase variation is phase noisephase noise..

Definition: Phase noise is the Fourier spectrum (power spectral density) Definition: Phase noise is the Fourier spectrum (power spectral density) of a sinusoidal carrier signal with respect to the carrier power.of a sinusoidal carrier signal with respect to the carrier power.

L(f) = L(f) = PPnn /P /Pc c (as ratio) (as ratio)

== PPnn in dBm/Hz – P in dBm/Hz – Pcc in dBm (as dBc) in dBm (as dBc)

PPnn is RMS noise power in 1-Hz bandwidth at frequency f is RMS noise power in 1-Hz bandwidth at frequency f

PPcc is RMS power of the carrier is RMS power of the carrier

6767ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 68: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Phase Noise AnalysisPhase Noise Analysis

6868

[V + δ(t)] sin [ωt + φ(t)] = [V + δ(t)] [sin ωt cos φ(t) + cos ωt sin φ(t)]

≈ [V + δ(t)] sin ωt + [V + δ(t)] φ(t) cos ωt

In-phase carrier frequency with amplitude noiseWhite noise δ(t) corresponds to noise floor

Quadrature-phase carrier frequency with amplitude and phase noiseShort-term phase noise corresponds to phase noise spectrum Phase spectrum, L(f) = Sφ(f)/2Where Sφ(f) is power spectrum of φ(t)

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 69: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Phase Noise MeasurementPhase Noise Measurement Phase noise is measured by low noise receiver Phase noise is measured by low noise receiver

(amplifier) and spectrum analyzer:(amplifier) and spectrum analyzer: Receiver must have a lower noise floor than the signal noise Receiver must have a lower noise floor than the signal noise

floor.floor. Local oscillator in the receiver must have lower phase noise Local oscillator in the receiver must have lower phase noise

than that of the signal. than that of the signal.

6969

Frequency (Hz)

Pow

er (

dBm

)

Receiver noise floor

Receiver phase noise

Signal spectrum

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 70: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Phase Noise MeasurementPhase Noise Measurement

7070

DUTPure tone

Input(carrier)

carrier

offsetHz

Spectrum analyzer power measurementPower (dBm) over resolution bandwith (RBW)

ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 71: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Phase Noise Measurement ExamplePhase Noise Measurement Example

Spectrum analyzer data:Spectrum analyzer data: RBW = 100HzRBW = 100Hz Frequency offset = 2kHzFrequency offset = 2kHz

PPcarriercarrier = – 5.30 dBm = – 5.30 dBm

PPoffsetoffset = – 73.16 dBm = – 73.16 dBm

Phase noise, L(f) =Phase noise, L(f) = P Poffsetoffset – P – Pcarriercarrier – 10 log RBW – 10 log RBW

== – 73.16 – ( – 5.30) – 10 log 100– 73.16 – ( – 5.30) – 10 log 100

= = – 87.86 dBc/Hz– 87.86 dBc/Hz Phase noise is specified as “ – 87.86 dBc/Hz at 2kHz from Phase noise is specified as “ – 87.86 dBc/Hz at 2kHz from

the carrier.”the carrier.”

7171ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 72: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

Problem to SolveProblem to Solve

Consider the following spectrum analyzer data:Consider the following spectrum analyzer data: RBW = 10HzRBW = 10Hz Frequency offset = 2kHzFrequency offset = 2kHz

PPcarriercarrier = – 3.31 dBm = – 3.31 dBm

PPoffsetoffset = – 81.17 dBm = – 81.17 dBm

Determine phase noise in dBc/Hz at 2kHz from Determine phase noise in dBc/Hz at 2kHz from the carrier.the carrier.

7272ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .

Page 73: Vishwani  D.  Agrawal James J. Danaher Professor ECE Department, Auburn University

References, AgainReferences, Again1.1. S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages

745-789, in 745-789, in System on Chip Test ArchSystem on Chip Test Architectures, edited by L.-T. Wang, itectures, edited by L.-T. Wang, C. E. Stroud and N. A. Touba, Amsterdam: Morgan-Kaufman, 2008.C. E. Stroud and N. A. Touba, Amsterdam: Morgan-Kaufman, 2008.

2.2. M. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI CircuitsDigital, Memory & Mixed-Signal VLSI Circuits, Boston: Springer, 2000., Boston: Springer, 2000.

3.3. J. Kelly and M. Engelhardt, J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, Advanced Production Testing of RF, SoC, and SiP Devicesand SiP Devices, Boston: Artech House, 2007., Boston: Artech House, 2007.

4.4. B. Razavi, B. Razavi, RF MicroelectronicsRF Microelectronics, Upper Saddle River, New Jersey: , Upper Saddle River, New Jersey: Prentice Hall PTR, 1998.Prentice Hall PTR, 1998.

5.5. J. Rogers, C. Plett and F. Dai, J. Rogers, C. Plett and F. Dai, Integrated Circuit Design for High-Integrated Circuit Design for High-Speed Frequency SynthesisSpeed Frequency Synthesis, Boston: Artech House, 2006., Boston: Artech House, 2006.

6.6. K. B. Schaub and J. Kelly, K. B. Schaub and J. Kelly, Production Testing of RF and System-on-a-Production Testing of RF and System-on-a-Chip Devices for Wireless CommunicationsChip Devices for Wireless Communications, Boston: Artech House, , Boston: Artech House, 2004.2004.

7373ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2010, Mar 11 . . .Spring 2010, Mar 11 . . .