elec 2200-002 digital logic circuits fall 2008 binary arithmetic (chapter 1) vishwani d. agrawal...

ELEC 2200-002Digital Logic Circuits

Fall 2008Binary Arithmetic (Chapter 1)

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal

[email protected]

Fall 2008, Aug 20 . . .Fall 2008, Aug 20 . . . ELEC2200-002 Lecture 2ELEC2200-002 Lecture 2 11

Exercises from Lecture 1Identify radio frequency (RF), mixed (analog and digital) signal, and digital components in a communications system.

Which parts in computing and communications systems contain digital arithmetic logic circuits?

Where is the binary machine code stored in a digital computer?

What is the difference between sequential and combinational circuits? Which category does the control of a computer belong to?


AnswersComponents of a communications system:

RF: Antenna, duplexer, filter, mixer, local oscillator.

Mixed-signal: ADC, DAC.

Digital: DSP.

Arithmetic logic is contained in DSP and datapath.

Machine code is stored in a memory.

Sequential and combinational circuits:

A sequential circuit contains memory. Its output is determined by input and the content of the memory.

A combinational circuit contains no memory. Its output depends entirely upon the input.

Control of a computer is a sequential circuit.Fall 2008, Aug 20 . . .Fall 2008, Aug 20 . . . ELEC2200-002 Lecture 2ELEC2200-002 Lecture 2 33


Why Binary Arithmetic?

Hardware can only deal with binary digits, 0 and 1.

Must represent all numbers, integers or floating point, positive or negative, by binary digits, called bits.

Can devise electronic circuits to perform arithmetic operations: add, subtract, multiply and divide, on binary numbers.


Positive IntegersDecimal system: made of 10 digits, {0,1,2, . . . , 9}

41 = 4×101 + 1×100

255 = 2×102 + 5×101 + 5×100

Binary system: made of two digits, {0,1}

00101001 = 0×27 + 0×26 + 1×25 + 0×24 +1×23 + 0×22 + 0×21 + 1×20

= 32 + 8 +1 = 41

11111111 = 255, largest number with 8 binary digits, 28-1


Base or Radix

For decimal system, 10 is called the base or radix.

Decimal 41 is also written as 4110 or 41ten

Base (radix) for binary system is 2.

Thus, 41ten = 1010012 or 101001two

Also,111ten = 1101111two

and 111two = 7ten


Signed Integers – What Not to Do

Use fixed length binary representation

Use left-most bit (called most significant bit or MSB) for sign:

0 for positive

1 for negative

Example: +18ten = 00010010two

–18ten = 10010010two


Why Not to Use Sign BitSign and magnitude bits should be differently treated in arithmetic operations.

Addition and subtraction require different logic circuits.

Overflow is difficult to detect.

“Zero” has two representations:+ 0ten = 00000000two

– 0ten = 10000000two

Signed-integers are not used in modern computers.


Integers With Sign – Other WaysUse fixed-length representation, but no sign bit– 1’s complement: To form a negative number,

complement each bit in the given number.– 2’s complement: To form a negative number,

start with the given number, subtract one, and then complement each bit, orfirst complement each bit, and then add 1.

2’s complement is the preferred representation.


1’s-ComplementTo change the sign of a binary integer simply complement (invert) each bit.

Example: 3 = 0011, – 3 = 1100

n-bit representation: Negation is equivalent to subtraction from 2n – 1

-4 0 4 8 12 16 200000 0100 1000 1100 10000 10100

Infiniteuniverseof integers

Modulo-16(4-bit)universe

16/0

8

412 0100

1000

1100

0000

151111 0

8

412 0100

1000

1100

0000

-0

111115

-77 7

0111

-3

∞-∞


2’s-Complement

Why not 1’s-complement? Don’t like two zeros.

Add 1 to 1’s-complement representation.

Some properties:Only one representation for 0

Exactly as many positive numbers as negative numbers

Slight asymmetry – there is one negative number with no positive counterpart

General Method for Binary Integers with Sign

Select number (n) of bits in representation.

Partition 2n integers into two sets:00…0 through 01…1 are n/2 positive integers.

10…0 through 11…1 are n/2 negative integers.

Negation rule transforms negative to positive, and vice-versa:Signed integers: invert MSB

1’s complement: Subtract from 2n – 1 = 1…1 (same as “invert all bits”)

2’s complement: Subtract from 2n = 10…0 (same as 1’s complement + 1)


Three SystemsThree Systems


0000

10000111

1111

1010 = – 2

Signed intergers

0000

1000

1111

1010 = – 5

1’s complement integers

0010

1010 1010

0101

2

– 25

– 5

0000

1000

1111

10000

1010 = – 6

2’s complement integers

1010 01106– 6

0– 0

0

– 7 – 87 7

0

– 07

– 7


Three RepresentationsSign-magnitude

000 = +0001 = +1010 = +2011 = +3100 = - 0101 = - 1110 = - 2111 = - 3

2’s complement

000 = +0001 = +1010 = +2011 = +3100 = - 4101 = - 3110 = - 2111 = - 1

(Preferred)

1’s complement

000 = +0001 = +1010 = +2011 = +3100 = - 3101 = - 2110 = - 1111 = - 0


2’s Complement Numbers0

+1

+2

+3

-1

-2

-3

- 4

000

001

010

011

100

101

110

111

+1-1

Po

sitive nu

mb

ers

Neg

ative nu

mb

ers

Overflow Negation


2’s Complement n-bit NumbersRange: –2n –1 through 2n –1 – 1 Unique zero: 00000000 . . . . . 0Negation rule: see slide 9.Expansion of bit length: stretch the left-most bit all the way, e.g., 11111101 is still – 3.Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.Subtraction rule: for A – B, add – B to A.


2’s-Compliment to Decimal Conversion

an-1an-2 . . . a1a0 = -2n-1an-1 + Σ 2i aii=0

n-2

-128 64 32 16 8 4 2 1

8-bit conversion box

-128 64 32 16 8 4 2 1 1 1 1 1 1 1 0 1

Example

-128+64+32+16+8+4+1 = -128 + 125 = -3


For More on 2’s-Complement

Chapter 2 in D. E. Knuth, The Art of Computer Programming: Seminumerical Algorithms, Volume II, Second Edition, Addison-Wesley, 1981.

A. al’Khwarizmi, Hisab al-jabr w’al-muqabala, 830.

Read: A two part interview with D. E. Knuth, Communications of the ACM (CACM), vol. 51, no. 7, pp. 35-39 (july), and no. 8, pp. 31-35 (August), 2008.

Donald E. Knuth (1938 - ) Abu Abd-Allah ibn Musa al’Khwarizmi (~780 – 850)


AdditionAdding bits:

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = (1) 0

Adding integers:

carry

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 1 (1)1 (1)0 (0)1 two = 13ten

1 1 0


SubtractionDirect subtraction

Two’s complement subtraction

0 0 0 . . . . . . 0 1 1 1 two = 7ten

- 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 0 0 0 1two = 1ten

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 1 1 1 . . . . . . 1 0 1 0 two = - 6ten

= 0 0 0 . . . . . . 0 (1) 0 (1) 0 (0)1 two = 1ten

1 1 1 . . . . . . 1 1 0


Overflow: An ErrorExamples: Addition of 3-bit integers (range - 4 to +3)

-2-3 = -5 110 = -2 + 101 = -3

= 1011 = 3 (error)

3+2 = 5 011 = 3 010 = 2 = 101 = -3 (error)

Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.

01

2

3

-1

-2

-3- 4

000

001

010

011

100

101

110

111

– +

Overflowcrossing


Design Hardware Bit by Bit

Adding two bits:a b half_sum

carry_out

h_s(a, b) c_o(a, b)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half-adder circuit

a

b

half_sum

carry_out

XOR

AND


One-bit Full-Adder

ci+1

Adding three bits

a b ci half sum (a, b) full sum

h_s c_o h_s c_o (a, b) (a, b) (h_s(a, b), ci) (h_s(a, b), ci)

0 0 0 0 0 0 0 00 0 1 0 0 1 0 00 1 0 1 0 1 0 00 1 1 1 0 0 1 11 0 0 1 0 1 0 01 0 1 1 0 0 1 11 1 0 0 1 0 0 11 1 1 0 1 1 0 1


One-bit Full-Adder Circuit

ai

bi

XOR

AND

XOR

ANDOR

ci

sumi

Ci+1

FAih_s(ai, bi)

c_o(ai, bi)

h_s

(h_s(ai, bi), ci)

c_o

(h_s(ai, bi), ci)


32-bit Ripple-Carry Adder32-bit Ripple-Carry Adder

FA0

FA1

FA2

FA31

c0=0 a0 b0

a1 b1

a2 b2

a31 b31

sum0

sum1

sum2

sum31


How Fast is Ripple-Carry Adder?

Longest delay path (critical path) runs from cin to sum31.

Suppose delay of full-adder is 100ps.

Critical path delay = 3,200ps

Clock rate cannot be higher than 1/(3,200×10 –12) Hz = 312MHz.

Must use more efficient ways to handle carry.


Speeding Up the AdderSpeeding Up the Adder16-bit ripple carry adder

a0-a15

b0-b15

cin

sum0-sum15

16-bit ripple carry adder

a16-a31

b16-b31

0

16-bit ripple carry adder

a16-a31

b16-b31

1

Mu

ltip

lex

er

sum16-sum31

0

1

This is a carry-select adder


Fast AddersIn general, any output of a 32-bit adder can be evaluated as a logic expression in terms of all 65 inputs.Number of levels of logic can be reduced to log2N for N-bit adder. Ripple-carry has N levels.

More gates are needed, about log2N times that of ripple-carry design.Fastest design is known as carry lookahead adder.


N-bit Adder Design OptionsType of adder Time complexity

(delay)

Space complexity

(size)

Ripple-carry O(N) O(N)

Carry-lookahead O(log2N) O(N log2N)

Carry-skip O(√N) O(N)

Carry-select O(√N) O(N)

Reference: J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Second Edition, San Francisco, California, 1990, page A-46.


Binary Multiplication (Unsigned)

1 0 0 0 two = 8ten multiplicand

1 0 0 1 two = 9ten multiplier

____________

1 0 0 0 0 0 0 0 partial products 0 0 0 0 1 0 0 0____________

1 0 0 1 0 0 0two = 72ten

Basic algorithm: For n = 1, 32,only If nth bit of multiplier is 1,then add multiplicand × 2 n –1

to product


LSB of multiplier

?

Multiplication FlowchartInitialize product register to 0 Partial product number, n = 1

Left shift multiplicand register 1 bit

Right shift multiplier register 1 bit

i = ? n = n + 1Done

Start

Add multiplicand to product and place result

in product register

1 0

n < 32n = 32


Serial Multiplication

64-bit product register

64

64

64

64-bit ALU Test LSB32 times

shift right

32-bit multiplier

shift left

write3 operations per bit:

shift rightshift leftadd

Need 64-bit ALU

Multiplicand (expanded 64-bits)

LSB = 0LSB= 1

add

shift


Serial Multiplication (Improved)Multiplicand

64-bit product register

32

32

32

32-bit ALUTest LSB32 times

LSB

shift right

00000 . . . 00000 32-bit multiplier Initialized product register

write

2 operations per bit:shift rightadd

32-bit ALU

1

1add


Example: 0010two× 0011two

Iteration Step Multiplicand Product

0 Initial values 0010 0000 0011

1 LSB=1 => Prod=Prod+Mcand 0010 0010 0011

Right shift product 0010 0001 0001



3 LSB=0 => no operation 0010 0001 1000


4 LSB=0 => no operation 0010 0000 1100


0010two× 0011two = 0110two, i.e., 2ten×3ten = 6ten


Multiplying with SignsConvert numbers to magnitudes.

Multiply the two magnitudes through 32 iterations.

Negate the result if the signs of the multiplicand and multiplier differed.

Alternatively, the previous algorithm will work with some modifications. See B. Parhami, Computer Architecture, New York: Oxford University Press, 2005, pp. 199-200.


Example 1: 1010two× 0011two


0 Initial values 11010 00000 0011





3 LSB=0 => no operation 11010 11011 1000


4 LSB=0 => no operation 11010 11101 1100


1010two× 0011two = 101110two, i.e., -6ten×3ten = -18ten


Example 2: 1010two× 1011two


0 Initial values 11010 00000 1011





3 LSB=0 => no operation 11010 11011 1010


4 LSB=1 => Prod=Prod – Mcand* 00110 00011 1101


1010two× 1011two = 011110two, i.e., -6ten×(-5ten) = 30ten

*Last iteration with a negative multiplier in 2’s complement.*Last iteration with a negative multiplier in 2’s complement.


Adding Partial Products

y3 y2 y1 y0 multiplicand x3 x2 x1 x0 multiplier ________________________

x0y3 x0y2 x0y1 x0y0 four carry← x1y3 x1y2 x1y1 x1y0 partial

carry← x2y3 x2y2 x2y1 x2y0 productscarry← x3y3 x3y2 x3y1 x3y0 to be__________________________________________________ summed p7 p6 p5 p4 p3 p2 p1 p0

Requires three 4-bit additions. Slow.


Array Multiplier: Carry Forward

y3 y2 y1 y0 multiplicand x3 x2 x1 x0 multiplier ________________________

x0y3 x0y2 x0y1 x0y0 four x1y3 x1y2 x1y1 x1y0 partial x2y3 x2y2 x2y1 x2y0 products

x3y3 x3y2 x3y1 x3y0 to be__________________________________________________ summed p7 p6 p5 p4 p3 p2 p1 p0

Note: Carry is added to the next partial product (carry-save addition).Adding the carry from the final stage needs an extra (ripple-carry stage. These additions are faster but we need four stages.


Basic Building Blocks

Two-input ANDFull-adder

Full adder

yi x0

p0i = x0yi

0th partial product sum bit

to (k+1)th sum

sum bit from (k-1)th

sum

yi xk

carry bits from (k-1)th

sum

carry bits to (k+1)th

sum

Slide 24

ith bit ofkth partialproduct


Array Multiplier y3 y2 y1 y0

x0

x1

x2

x3

FA

xiyj

ppk

ppk+1co

0

0

0

ci

0

0 0 0 0

p7 p6 p5 p4 p3 p2 p1 p0FA FA FA FA

Critical path0


Types of Array Multipliers

Baugh-Wooley Algorithm: Signed product by two’s complement addition or subtraction according to the MSB’s.Booth multiplier algorithmTree multipliersReference: N. H. E. Weste and D. Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Boston: Addison-Wesley, 2005.


Binary Division (Unsigned)

1 3 Quotient1 1 / 1 4 7 Divisor / Dividend 1 1 3 7 Partial remainder 3 3 4 Remainder

0 0 0 0 1 1 0 11 0 1 1 / 1 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0


4-bit Binary Division (Unsigned)

Dividend: 6 = 0110Divisor: 4 = 0100

- 4 = 1100

6─ = 1, remainder 24

0 0 0 10 0 0 0 1 1 01 1 0 01 1 0 0 negative → quotient bit 00 1 0 0 → restore remainder 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 negative → quotient bit 0 0 1 0 0 → restore remainder 0 0 0 1 1 0 1 1 0 0 1 1 1 1 negative → quotient bit 0 0 1 0 0 → restore remainder 0 0 1 1 0 1 1 0 0 0 0 1 0 positive → quotient bit 1

Itera

tion

4

Itera

tion

3

I

tera

tion

2

Ite

rati

on

1


32-bit Binary Division Flowchart $R=0, $M=Divisor, $Q=Dividend, count=n

Shift 1-bit left $R, $Q

$R ← $R - $M

$R < 0?$Q0=1$Q0=0

$R←$R+$M

count = count - 1

count = 0?Done

$Q=Quotient$R= Remainder

Start

Yes

Yes

No

No

$R and $M have one extra sign bit beyond 32 bits.

Restore $R(remainder)

$R (33 b) | $Q (32 b)


4-bit Example: 6/4 = 1, Remainder 2Actions n $R, $Q $M = Divisor

Initialize 3 0 0 0 0 0 | 0 1 1 0 0 0 1 0 0

Shift left $R, $Q 3 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0

Add – $M (11100) to $R 3 1 1 1 0 0 | 1 1 0 0 0 0 1 0 0

Restore, add $M (00100) to $R 2 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0

Shift left $R, $Q 2 0 0 0 0 1 | 1 0 0 0 0 0 1 0 0

Add – $M (11100) to $R 2 1 1 1 0 1 | 1 0 0 0 0 0 1 0 0

Restore, add $M (00100) to $R 1 0 0 0 0 1 | 1 0 0 0 0 0 1 0 0

Shift left $R, $Q 1 0 0 0 1 1 | 0 0 0 0 0 0 1 0 0

Add – $M (11100) to $R 1 1 1 1 1 1 | 0 0 0 0 0 0 1 0 0

Restore, add $M (00100) to $R 0 0 0 0 1 1 | 0 0 0 0 0 0 1 0 0

Shift left $R, $Q 0 0 0 1 1 0 | 0 0 0 0 0 0 1 0 0

Add – $M (11100) to $R 0 0 0 0 1 0 | 0 0 0 0 0 0 1 0 0

Set LSB of $Q = 1 0 0 0 0 1 0 | 0 0 0 1 0 0 1 0 0Remainder | Quotient

cou

nt

4

3

2

1

0


Initialize$R←0

Division33-bit $M (Divisor)

33-bit $R (Remainder)

33

33

33

33-bit ALU

32 timesStep 1: 1- bit left shift $R and $Q

32-bit $Q (Dividend)

Step 2: Subtract $R← $R - $M

Step 3: If sign-bit ($R)=0, set Q0=1If sign-bit ($R)=1, set Q0=0 and restore $R

V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, Fourth Edition,New York: McGraw-Hill, 1996.


Example: 8/3 = 2, Remainder = 2

Initialize $R = 0 0 0 0 0 $Q = 1 0 0 0 $M = 0 0 0 1 1

Step 1, L-shift $R,Q = 0 0 0 0 1 $Q = 0 0 0 0Step 2, Add - $M = 1 1 1 0 1

$R = 1 1 1 1 0Step 3, Set Q0 $Q = 0 0 0 0 Restore + $M = 0 0 0 1 1

$R = 0 0 0 0 1

Step 1, L-shift $R,Q = 0 0 0 1 0 $Q = 0 0 0 0 $M = 0 0 0 1 1Step 2, Add - $M = 1 1 1 0 1

$R = 1 1 1 1 1Step 3, Set Q0 $Q = 0 0 0 0 Restore + $M = 0 0 0 1 1

$R = 0 0 0 1 0

Ite

rati

on

2It

era

tio

n 1


Example: 8/3 = 2 (Remainder = 2) (Continued)

$R = 0 0 0 1 0 $Q = 0 0 0 0 $M = 0 0 0 1 1

Step 1, L-shift $R ,Q = 0 0 1 0 0 $Q = 0 0 0 0 $M = 0 0 0 1 1Step 2, Add - $M = 1 1 1 0 1

$R = 0 0 0 0 1Step 3, Set Q0 $Q = 0 0 0 1

Step 1, L-shift $R,Q = 0 0 0 1 0 $Q = 0 0 1 0 $M = 0 0 0 1 1Step 2, Add - $M = 1 1 1 0 1

$R = 1 1 1 1 1Step 3, Set Q0 $Q = 0 0 1 0 Final quotient Restore + $M = 0 0 0 1 1

$R = 0 0 0 1 0Ite

rati

on

4It

era

tio

n 3

Note “Restore $R” in Steps 1, 2 and 4. This method is known as the RESTORING DIVISION. An improved method, NON-RESTORINGDIVISION, is possible (see Hamacher, et al.)

Remainder


Signed Division

Remember the signs and divide magnitudes.

Negate the quotient if the signs of divisor and dividend disagree.

There is no other direct division method for signed division.


Symbol RepresentationEarly versions (60s and 70s)

Six-bit binary code (CDC)EBCDIC – extended binary coded decimal interchange code (IBM)

Presently used – ASCII – American standard code for information interchange – 7 bit code specified by American National Standards Institute (ANSI), see Table 1.11 on page 63; an eighth MSB is often used as parity bit to construct a byte-code.Unicode – 16 bit code and an extended 32 bit version


ASCIIEach byte pattern represents a character (symbol)– Convenient to write in hexadecimal, e.g., with even

parity,

00000000 0ten 00hex null

01000001 65ten 41hex A

11100001 225ten E1hex a– Table 1.11 on page 63 gives the 7-bit ASCII code.– C program – string – terminating with a null byte (odd

parity):01000101 01000011 01000101 10000000

69ten or 45hex 67ten or 43hex 69ten or 45hex 128ten or 80hex

E C E (null)

Error Detection CodeErrors: Bits can flip due too noise in circuits and in communication.

Extra bits used for error detection.

Example: a parity bit in ASCII code


Even parity code for A 01000001(even number of 1s)

Odd parity code for A 11000001(odd number of 1s)

7-bit ASCII code

Parity bits

Single-bit error in 7-bit code of “A”, e.g., 1000101, will changesymbol to “E” or 1000000 to “@”. But error will be detected inthe 8-bit code because the error changes the specified parity.

Richard W. HammingError-correcting codes (ECC).

Also known forHamming distance (HD) = Number of bits two binary vectors differ in

Example:

HD(1101, 1010) = 3

Hamming Medal, 1988


1915-1998

The Idea of Hamming CodeThe Idea of Hamming Code


Code space contains 2N possible N-bit code words

1010”A”

1110”E”

1011”B”

1000”8”

0010”2”

1-bit error in “A”

HD = 1HD = 1

HD = 1HD = 1

Error not correctable. Reason: No redundancy.Hamming’s idea: Increase HD between valid code words.

Hamming’s Distance ≥ 3 CodeHamming’s Distance ≥ 3 Code


1010010

”A”1-bit error in “A”shortest distancedecoding eliminateserror

HD = 2

HD = 1

0010101

”2”

1000111

”8”1011001

”B”

1110100

”E”

HD = 3

HD = 3

HD = 3

HD = 4

0010010

”?”

HD = 3

HD = 4

HD = 4

0011110

”3”

Minimum Distance-3 Hamming CodeSymbol

Original code

Odd-parity code

ECC, HD ≥ 3

0 0000 10000 0000000

1 0001 00001 0001011

2 0010 00010 0010101

3 0011 10011 0011110

4 0100 00100 0100110

5 0101 10101 0101101

6 0110 10110 0110011

7 0111 00111 0111000

8 1000 01000 1000111

9 1001 11001 1001100

A 1010 11010 1010010

B 1011 01011 1011001

C 1100 11100 1100001

D 1101 01101 1101010

E 1110 01110 1110100

F 1111 11111 1111111


Original code: Symbol “0” with a single-bit error will be Interpreted as“1”, “2”, “4” or “8”.

Reason: Hamming distance betweencodes is 1. A code with any bit error willmap onto another valid code.

Remedy: Design codes with HD ≥ 2.Example: Parity code. Single bit errordetected but not correctable.

Remedy: Design codes with HD ≥ 3.For single bit error correction, decodeas the valid code at HD = 1.

For more error bit detection orcorrection, design code with HD ≥ 4.


Integers and Real NumbersIntegers: the universe is infinite but discrete– No fractions– No numbers between consecutive integers, e.g., 5 and 6– A countable (finite) number of items in a finite range– Referred to as fixed-point numbers

Real numbers – the universe is infinite and continuous– Fractions represented by decimal notation

Rational numbers, e.g., 5/2 = 2.5Irrational numbers, e.g., 22/7 = 3.14159265 . . .

– Infinite numbers exist even in the smallest range– Referred to as floating-point numbers


Wide Range of Numbers

A large number:

976,000,000,000,000 = 9.76 × 1014

A small number:

0.0000000000000976 = 9.76 × 10 –14


Scientific NotationDecimal numbers

0.513×105, 5.13×104 and 51.3×103 are written in scientific notation.

5.13×104 is the normalized scientific notation.

Binary numbersBase 2

Binary point – multiplication by 2 moves the point to the right.

Normalized scientific notation, e.g., 1.0two×2 –1


Floating Point NumbersGeneral format

±1.bbbbbtwo×2eeee

or (-1)S × (1+F) × 2E

WhereS = sign, 0 for positive, 1 for negative

F = fraction (or mantissa) as a binary integer, 1+F is called significand

E = exponent as a binary integer, positive or negative (two’s complement)


Binary to Decimal Conversion

Binary (-1)S (1.b1b2b3b4) × 2E

Decimal (-1)S × (1 + b1×2-1 + b2×2-2 + b3×2-3 + b4×2-4) × 2E

Example: -1.1100 × 2-2 (binary) = - (1 + 2-1 + 2-2) ×2-2

= - (1 + 0.5 + 0.25)/4

= - 1.75/4

= - 0.4375 (decimal)


William Morton (Velvel) Kahan

1989 Turing Award Citation:

For his fundamental contributions to numerical analysis. One of the foremost experts on floating-point computations. Kahan has dedicated himself to "making the world safe for numerical computations."

Architect of the IEEE floating point standard

b. 1933, CanadaProfessor of Computer Science, UC-Berkeley


NegativeOverflow

PositiveOverflow

Expressible numbers

Numbers in 32-bit FormatsTwo’s complement integers

Floating point numbers

Ref: W. Stallings, Computer Organization and Architecture, Sixth Edition, Upper Saddle River, NJ: Prentice-Hall.

-231 231-10

Expressible negativenumbers

Expressible positivenumbers

0-2-127 2-127

Positive underflowNegative underflow

(2 – 2-23)×2128- (2 – 2-23)×2128

Positive zeroNegative zero + ∞+ ∞– ∞– ∞


IEEE 754 Floating Point StandardBiased exponent: true exponent range[-126,127] is changed to [1, 254]:

Biased exponent is an 8-bit positive binary integer.

True exponent obtained by subtracting 127ten or 01111111two

First bit of significand is always 1:± 1.bbbb . . . b × 2E

1 before the binary point is implicitly assumed.Significand field represents 23 bit fraction after the binary point.Significand range is [1, 2), to be exact [1, 2 – 2-23]


Examples

1.1010001 × 210100 = 0 10010011 10100010000000000000000 = 1.6328125 × 220

-1.1010001 × 210100 = 1 10010011 10100010000000000000000 = -1.6328125 × 220

1.1010001 × 2-10100 = 0 01101011 10100010000000000000000 = 1.6328125 × 2-20

-1.1010001 × 2-10100 = 1 01101011 10100010000000000000000 = -1.6328125 × 2-20

Biased exponent (0-255), bias 127 (01111111) to be subtracted

1.00.50.1250.00781251.6328125

Sign bit

8-bit biased exponent107 – 127

= – 20

23-bit Fraction (F) of significand


Example: Conversion to Decimal

Sign bit is 1, number is negativeBiased exponent is 27+20 = 129The number is

1 10000001 01000000000000000000000

Sign bit S bits 23-30 bits 0-22 normalized E F

(-1)S × (1 + F) × 2(exponent – bias) = (-1)1 × (1 + F) × 2(129 – 127)

= - 1 × 1.25 × 22

= - 1.25 × 4= - 5.0

Fall 2008, Aug 20 . . .Fall 2008, Aug 20 . . . ELEC2200-002 Lecture 2ELEC2200-002 Lecture 26868

NegativeOverflow

PositiveOverflow

IEEE 754 Floating Point Format

Floating point numbers

Expressible negativenumbers

Expressible positivenumbers

0-2-126 2-126

Positive underflowNegative underflow

(2 – 2-23)×2127- (2 – 2-23)×2127

+ ∞+ ∞– ∞– ∞


Positive Zero in IEEE 754

+ 1.0 × 2-127

Smallest positive number in single-precision IEEE 754 standard.Interpreted as positive zero.True exponent less than -126 is positive underflow; can be regarded as zero.

0 00000000 00000000000000000000000Biased

exponentFraction


Negative Zero in IEEE 754

- 1.0 × 2-127 Smallest negative number in single-precision IEEE 754 standard.Interpreted as negative zero.True exponent less than -126 is negative underflow; may be regarded as 0.

1 00000000 00000000000000000000000Biased

exponentFraction


Positive Infinity in IEEE 754

+ 1.0 × 2128 Largest positive number in single-precision IEEE 754 standard.Interpreted as + ∞If true exponent = 128 and fraction ≠ 0, then the number is greater than ∞. It is called “not a number” or NaN and may be interpreted as ∞.

0 11111111 00000000000000000000000Biased

exponentFraction


Negative Infinity in IEEE 754

-1.0 × 2128 Smallest negative number in single-precision IEEE 754 standard.Interpreted as - ∞If true exponent = 128 and fraction ≠ 0, then the number is less than - ∞. It is called “not a number” or NaN and may be interpreted as - ∞.

1 11111111 00000000000000000000000Biased

exponentFraction


Addition and Subtraction0. Zero check

- Change the sign of subtrahend, i.e., convert to summation- If either operand is 0, the other is the result

1. Significand alignment: right shift significand of smaller exponent until two exponents match.

2. Addition: add significands and report exception if overflow occurs. If significand = 0, return result as 0.

3. Normalization- Shift significand bits to normalize.- report overflow or underflow if exponent goes out of range.

4. Rounding


Example (4 Significant Fraction Bits)

Subtraction: 0.5ten – 0.4375ten

Step 0: Floating point numbers to be added

1.000two× 2 –1 and –1.110two× 2 –2

Step 1: Significand of lesser exponent is shifted right until exponents match

–1.110two× 2 –2 → – 0.111two× 2 –1

Step 2: Add significands, 1.000two + ( – 0.111two)

Result is 0.001two × 2 –1 01000+11001 00001

2’s complement addition, one bit added for sign


Example (Continued)

Step 3: Normalize, 1.000two× 2 – 4

No overflow/underflow since

127 ≥ exponent ≥ –126

Step 4: Rounding, no change since the sum fits in 4 bits.

1.000two × 2 – 4 = (1+0)/16 = 0.0625ten


FP Multiplication: Basic Idea

1. Separate sign

2. Add exponents

3. Multiply significands

4. Normalize, round, check overflow/underflow

5. Replace sign


FP Multiplication: Step 0

Multiply, X × Y

X = 0? Y = 0?

Z = 0

Return

Steps 1 - 5

yes

no

yes

no


FP Multiplication IllustrationMultiply 0.5ten and – 0.4375ten

(answer = – 0.21875ten) or

Multiply 1.000two×2 –1 and –1.110two×2 –2

Step 1: Add exponents–1 + (–2) = – 3

Step 2: Multiply significands 1.000

×1.110 0000 1000 100010001110000 Product is 1.110000


FP Mult. Illustration (Cont.)Step 3:– Normalization: If necessary, shift significand right and

increment exponent.

Normalized product is 1.110000 × 2 –3

– Check overflow/underflow: 127 ≥ exponent ≥ –126

Step 4: Rounding: 1.110 × 2 –3

Step 5: Sign: Operands have opposite signs,

Product is –1.110 × 2 –3

(Decimal value = – (1+0.5+0.25)/8 = – 0.21875ten)


FP Division: Basic Idea

Separate sign.

Check for zeros and infinity.

Subtract exponents.

Divide significands.

Normalize and detect overflow/underflow.

Perform rounding.

Replace sign.

elec 2200-002 digital logic circuits fall 2008 binary arithmetic (chapter 1) vishwani d. agrawal...

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