spring 08, apr 17 elec 7770: advanced vlsi design (agrawal) 1 elec 7770 advanced vlsi design spring...

Spring 08, Apr 17Spring 08, Apr 17 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2008Spring 2008System TestSystem Test

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html


A System and Its TestingA System and Its Testing A system is an organization of components

(hardware/software parts and subsystems) with capability to perform useful functions.

Functional test verifies integrity of system: Checks for presence and sanity of subsystems Checks for system specifications Executes selected (critical) functions

Diagnostic test isolates faulty part: For field maintenance isolates lowest replaceable unit (LRU),

e.g., a board, disc drive, or I/O subsystem For shop repair isolates shop replaceable unit (SRU), e.g., a

faulty chip on a board Diagnostic resolution is the number of suspected faulty units

identified by test; fewer suspects mean higher resolution


System Test ApplicationsSystem Test Applications

A

Application Functional test Diagnostic test Resolution

Manufacturing Yes LRU, SRU

Maintenance Yes

Field repair LRU

Shop repair SRU

LRU: Lowest replaceable unitSRU: Shop replaceable unit


Functional TestFunctional Test All or selected (critical) operations executed with

non-exhaustive data. Tests are a subset of design verification tests (test-

benches). Software test metrics used: statement, branch and

path coverages; provide low (~70%) structural hardware fault coverage.

Examples: Microprocessor test – all instructions with random

data (David, 1998). Instruction-set fault model – wrong instruction is

executed (Thatte and Abraham, IEEETC-1980).


Gate-Level DiagnosisGate-Level Diagnosis

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:

T1 = 010T2 = 011T3 = 100T4 = 110

Logic circuitKarnaugh map

(shaded squares are true outputs)


Gate Replacement FaultGate Replacement Fault

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:T1 = 010 (pass)T2 = 011 (fail)T3 = 100 (pass)T4 = 110 (fail)

Faulty circuit(OR replaced by AND)

Karnaugh map(faulty output:

Only red sqaure is 1 output)


Bridging FaultBridging Fault

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:T1 = 010 (pass)T2 = 011 (pass)T3 = 100 (fail)T4 = 110 (pass)

Faulty circuit(OR bridge: a, c)

Karnaugh map(all red squares are faulty 1 outputs)

a+c

a+c


Fault Test syndrome

t1 t2 t3 t4

No fault

a0, b0, d0

a1

b1

c0

c1, d1, e1

e0

Fault DictionaryFault Dictionary

0

0

1

0

0

1

0

0

0

0

0

1

0

1

0

0

0

1

0

1

0

0

1

0

0

0

0

1

a0 : Line a stuck-

at-0

ti = 0, if Ti passes

= 1, if Ti fails


Diagnosis with DictionaryDiagnosis with Dictionary

Fault Test syndrome Diagnosis

t1 t2 t3 t4

OR AND 0 1 0 1 e0

OR-bridge (a,c) 0 0 1 0 b1

OR NOR 1 1 1 1 c1, d1, e1, e0

Dictionary look-up with minimum Hamming distance


Diagnostic TreeDiagnostic Tree

T4

T1

T2

T3

No faultfound

T3

T2

b1

a1

c1, d1, e1

a0, b0, d0

e0

c0

Pass: t4=0

Fail: t4=1

a0, b0, d0, e0

a1, c1, d1, e1

OR AND

OR bridge(a,c)

OR NOR


System Test: A DFT ProblemSystem Test: A DFT Problem

Changing scenario in VLSI: Mixed-signal (analog and RF) circuits System-on-a-chip Multi-chip modules Intellectual property (IP) cores


Conventional Test:Conventional Test:In-Circuit Test (ICT)In-Circuit Test (ICT)

A bed-of-nails fixture provides direct access to each chip on A bed-of-nails fixture provides direct access to each chip on the board.the board.

Advantages: Thorough test for devices; good interconnect Advantages: Thorough test for devices; good interconnect test.test.

Limitations:Limitations: Works best when analog and digital functions are implemented Works best when analog and digital functions are implemented

on separate chips.on separate chips. Devices must be designed for backdriving protection.Devices must be designed for backdriving protection. Not applicable to system-on-a-chip (SOC).Not applicable to system-on-a-chip (SOC).

Disadvantages:Disadvantages: High cost and inflexibility of test fixture.High cost and inflexibility of test fixture. System test must check for timing.System test must check for timing.


PCB vs. SOCPCB vs. SOC

Tested partsTested parts In-circuit test (ICT)In-circuit test (ICT) Easy test accessEasy test access BulkyBulky SlowSlow High assembly costHigh assembly cost

High reliabilityHigh reliability Fast interconnectsFast interconnects Low costLow cost Untested coresUntested cores No internal test accessNo internal test access Mixed-signal devicesMixed-signal devices

PCB SOC


Core-Based DesignCore-Based Design

Cores are predesigned and verified but Cores are predesigned and verified but untested blocks:untested blocks: Soft core (synthesizable RTL)Soft core (synthesizable RTL) Firm core (gate-level netlist)Firm core (gate-level netlist) Hard core (non-modifiable layout, often called Hard core (non-modifiable layout, often called

legacy corelegacy core))

Core is the intellectual property of vendor Core is the intellectual property of vendor (internal details not available to user.)(internal details not available to user.)

Core-vendor supplied tests must be applied Core-vendor supplied tests must be applied to embedded cores.to embedded cores.


Partitioning for TestPartitioning for Test

Partition according to test methodology:Partition according to test methodology: Logic blocksLogic blocks Memory blocksMemory blocks Analog blocksAnalog blocks

Provide test access:Provide test access: Boundary scanBoundary scan Analog test busAnalog test bus

Provide test-wrappers (also called collars) Provide test-wrappers (also called collars) for cores.for cores.


Test-Wrapper for a CoreTest-Wrapper for a Core Test-wrapper (or collar) is the logic added around a core to

provide test access to the embedded core. Test-wrapper provides:

For each core input terminal A normal mode – Core terminal driven by host chip An external test mode – Wrapper element observes core input

terminal for interconnect test An internal test mode – Wrapper element controls state of core

input terminal for testing the logic inside core For each core output terminal

A normal mode – Host chip driven by core terminal An external test mode – Host chip is driven by wrapper element

for interconnect test An internal test mode – Wrapper element observes core outputs

for core test


A Test-WrapperA Test-Wrapper

Wrappertest

controller

Scan chain

Sc

an c

ha

in

Sc

an c

ha

in

to/from TAP

from/toExternalTest pins

Wrapperelements

Core

Fu

nc

tio

nal

co

re in

pu

ts

Fu

nc

tio

nal

co

re o

utp

uts


Overhead of Test AccessOverhead of Test Access

Test access is non-intrusive.Test access is non-intrusive. Hardware is added to each I/O signal of block Hardware is added to each I/O signal of block

to be tested.to be tested. Test access interconnects are mostly local.Test access interconnects are mostly local. Hardware overhead is proportional to:Hardware overhead is proportional to:

(Block area) – 1/2


Overhead EstimateOverhead Estimate

Rent’s rule: For a logic block the number of gates Gand the number of terminals t are related by

t = K G

where 1 ≤ K ≤ 5, and ~ 0.5.

Assume that block area A is proportional to G, i.e.,

t is proportional to A 0.5. Since test logic is addedto each terminal t,

Test logic added to terminals

Overhead = ──────────────────── ~ A –0.5

A


DFT Architecture for SOCDFT Architecture for SOC

User defined test access mechanism (TAM)

Module

1Tes

t

wra

pp

er

Testsource

Testsink

Module

NTes

t

wra

pp

er

Test access port (TAP)

Functionalinputs

FunctionaloutputsFunc.

inputs

Func.outputs

SOC inputs SOC outputsTD

I

TC

K

TM

S

TR

ST

TD

O

Instruction register control

Serial instruction data


DFT ComponentsDFT Components Test source: Provides test vectors via on-chip LFSR,

counter, ROM, or off-chip ATE. Test sink: Provides output verification using on-chip

signature analyzer, or off-chip ATE. Test access mechanism (TAM): User-defined test data

communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components.

Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.


SummarySummary Functional test: verify system hardware, software,

function and performance; pass/fail test with limited diagnosis; high ( ~100%) software coverage metrics; low ( ~70%) structural fault coverage.

Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree.

SOC design for testability: Partition SOC into blocks of logic, memory and analog

circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures.

spring 08, apr 17 elec 7770: advanced vlsi design (agrawal) 1 elec 7770 advanced vlsi design spring...

Documents

c slide

advanced vlsi design

b c stuck

advanced vlsi design

advanced vlsi design

fault tests

b c t3 t1 t2 t4

c karnaugh