virtuoso -xl layout editor -...

Version 5.0

Lab Manual December 16, 2002

Virtuoso®-XL Layout Editor

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Table of Contents Virtuoso-XL Layout Editor

Table of Contents

Virtuoso-XL Layout Editor

Module 1 Introduction to Virtuoso XL

Lab 1-1 Using the Cadence Online Documentation System......................................................... 1-1

Lab 1-2 Overview of the Design Flow.......................................................................................... 1-4Starting the Software.................................................................................................. 1-4Opening a Schematic ................................................................................................. 1-4Invoking the XL Tool ................................................................................................ 1-4Viewing the Window Banner..................................................................................... 1-5Generating the Design................................................................................................ 1-6Place the Components in the Boundary ..................................................................... 1-7Moving a Device........................................................................................................ 1-8Examine the Design Connectivity ............................................................................. 1-8Abutting Devices ....................................................................................................... 1-8Permuting Pins ......................................................................................................... 1-10Updating the Connectivity Source ........................................................................... 1-12Checking Against the Source................................................................................... 1-12Verifying Missing Devices ...................................................................................... 1-13Updating Components and Nets .............................................................................. 1-14Placing the Inverters from the Schematic ................................................................ 1-14Manually Creating Interconnect .............................................................................. 1-15Exporting to the Router............................................................................................ 1-17Loading the FFreva_new.do File ............................................................................. 1-18Importing from the Router ....................................................................................... 1-19

Module 2 Virtuoso-XL Setup

Lab 2-1 Starting Layout XL .......................................................................................................... 2-1Starting the Software.................................................................................................. 2-1Opening a Schematic ................................................................................................. 2-1Starting Layout XL .................................................................................................... 2-1Verifying the Technology File................................................................................... 2-2Starting Layout XL Again ......................................................................................... 2-4Saving the Technology File ....................................................................................... 2-4

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Virtuoso-XL Layout Editor Table of Contents

Lab 2-2 Adding Pins...................................................................................................................... 2-6Placing Devices.......................................................................................................... 2-6Reloading the SKILL File.......................................................................................... 2-6Viewing the SKILL File ............................................................................................ 2-7Loading the SKILL File............................................................................................. 2-8

Lab 2-3 Creating Interconnect..................................................................................................... 2-10Placing Devices........................................................................................................ 2-10Moving the Pin......................................................................................................... 2-12Creating the Connection .......................................................................................... 2-13Adding the ViaLayers Rule ..................................................................................... 2-14Viewing the Changes ............................................................................................... 2-17

Lab 2-4 Auto Abutment............................................................................................................... 2-20Verifying Auto Abutment ........................................................................................ 2-20Adding Abutment Rules .......................................................................................... 2-21Loading the Abutment Rules ................................................................................... 2-22Abutting Devices ..................................................................................................... 2-22Changing Device Size.............................................................................................. 2-23

Lab 2-5 Permuting Pins ............................................................................................................... 2-25Abutting the Pmos Devices...................................................................................... 2-25Verifying the permuteRule ...................................................................................... 2-25Verifying the XL Options Form .............................................................................. 2-26

Lab 2-6 Adding Mfactor.............................................................................................................. 2-28Setting Up ................................................................................................................ 2-28Probing the Design................................................................................................... 2-28Adding Mfactor as a CDF........................................................................................ 2-29Changing the Multiplication Factor ......................................................................... 2-31Verifying the Multiplication Factor ......................................................................... 2-31Editing the Layout XL Options................................................................................ 2-31Replacing the Devices.............................................................................................. 2-32

Lab 2-7 Customizing the Desktop............................................................................................... 2-33Set Up Your Environment ....................................................................................... 2-33Saving Your Environment ....................................................................................... 2-34Reloading the .classcdsenv File ............................................................................... 2-34

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Module 3 Layout Generation

Lab 3-1 Generating a Layout from a Schematic ........................................................................... 3-1Opening a Cellview.................................................................................................... 3-1Invoking Layout XL .................................................................................................. 3-1Investigating the Layout Generation Form................................................................ 3-1Changing Pin Layers.................................................................................................. 3-3Removing Pins ........................................................................................................... 3-3Creating a Feedthru Pin ............................................................................................. 3-3Creating Labels .......................................................................................................... 3-4Changing the Size of the Boundary ........................................................................... 3-5Loading a Template File ............................................................................................ 3-5Verifying the Layout.................................................................................................. 3-6Regenerating Your Design......................................................................................... 3-6Summary .................................................................................................................... 3-7

Lab 3-2 Cloning............................................................................................................................. 3-8Starting the Software.................................................................................................. 3-8Opening a Cellview.................................................................................................... 3-8Invoking Layout XL .................................................................................................. 3-8Generating the Cloned Objects .................................................................................. 3-9Cloning the Inverters................................................................................................ 3-13Summary .................................................................................................................. 3-17

Module 4 Editing Placement

Lab 4-1 Editing Placement ............................................................................................................ 4-1Starting the Software.................................................................................................. 4-1Opening the Schematic .............................................................................................. 4-1Generating the Design................................................................................................ 4-2Placing the Instances.................................................................................................. 4-3Chaining Devices ....................................................................................................... 4-4Completing the Design .............................................................................................. 4-5Examine the Design Connectivity ............................................................................. 4-6Abutting Devices ....................................................................................................... 4-6Splitting Devices........................................................................................................ 4-7Transistor Folding...................................................................................................... 4-8Permuting Pins ......................................................................................................... 4-10Creating Additional Pins.......................................................................................... 4-12Moving Components into Optimal Placement......................................................... 4-14Tips on Placement.................................................................................................... 4-15Completing Placement of Components ................................................................... 4-16

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Module 5 Creating Interconnect in Virtuoso-XL

Lab 5-1 Basic Interconnect Tasks ................................................................................................. 5-1Before You Start ........................................................................................................ 5-1Opening a Cellview.................................................................................................... 5-1Invoking Virtuoso-XL ............................................................................................... 5-2Enabling Auto Permute.............................................................................................. 5-2Checking the Connectivity......................................................................................... 5-3Creating Interconnect Using Shapes.......................................................................... 5-3Creating Interconnect with the Path Command......................................................... 5-6Moving Pins and Keeping Connectivity .................................................................... 5-8Starting a Path Over Multiple Shapes........................................................................ 5-9Creating a Short in Your Design................................................................................ 5-9Summary .................................................................................................................. 5-10

Lab 5-2 Creating Interconnect..................................................................................................... 5-11Opening a Cellview.................................................................................................. 5-11Invoking the XL Setup............................................................................................. 5-11Wiring the Design .................................................................................................... 5-11Summary .................................................................................................................. 5-12

Module 6 Wire Editor

Lab 6-1 Using Wire Editor ............................................................................................................ 6-1Starting the Software.................................................................................................. 6-1Opening a Schematic ................................................................................................. 6-1Invoking Virtuoso-XL ............................................................................................... 6-1Enable the Wire Editor............................................................................................... 6-2Set the Routing Rules ................................................................................................ 6-2Show Incomplete Nets ............................................................................................... 6-2Begin Using the Wire Editor...................................................................................... 6-2Create the Power and Ground Rails........................................................................... 6-2Use autoContact to Attach Power Rails to Pdevices ................................................. 6-3

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Lab 6-2 Wire Editor Commands ................................................................................................... 6-7Opening a Schematic ................................................................................................. 6-7Invoking Virtuoso-XL ............................................................................................... 6-7Enable the Wire Editor............................................................................................... 6-7Create Path ................................................................................................................. 6-8Edit Stretch............................................................................................................... 6-10Edit—Other—Split .................................................................................................. 6-10Edit—Pull ................................................................................................................ 6-10Edit—Copy Route.................................................................................................... 6-11Verify—Check Route .............................................................................................. 6-11Verify—Report ........................................................................................................ 6-12

Lab 6-3 Wire Editor Options....................................................................................................... 6-14Starting the Software................................................................................................ 6-14Opening the Layout.................................................................................................. 6-14Invoking Virtuoso-XL ............................................................................................. 6-14Interactive Checking ................................................................................................ 6-15Via Assistance.......................................................................................................... 6-16Allow Orthogonal Jogs ............................................................................................ 6-17Route To Cursor....................................................................................................... 6-18Bus Routing ............................................................................................................. 6-18Summary .................................................................................................................. 6-20

Module 7 Using the Cadence Chip Assembly Router

Lab 7-1 Translating from Design Framework II to Cadence Chip Assembly Router................... 7-1Starting the Software.................................................................................................. 7-1Opening a Design....................................................................................................... 7-1Viewing the Design.................................................................................................... 7-2Creating a New Rules File ......................................................................................... 7-3Defining the Layers for Translation........................................................................... 7-3Saving the Layer Definitions ..................................................................................... 7-6Defining the Vias to Utilize ....................................................................................... 7-6Defining Equivalent Layers ....................................................................................... 7-7Defining Boundary Layers......................................................................................... 7-8Defining Keepouts ..................................................................................................... 7-9Defining Conductors................................................................................................ 7-11Translating the Design ............................................................................................. 7-13

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Lab 7-2 Becoming Familiar with the CCAR Environment......................................................... 7-16Viewing the Different Sections of the Window....................................................... 7-17Zooming and Panning .............................................................................................. 7-18Using the Color Palette ............................................................................................ 7-20Using the Layers Window ....................................................................................... 7-21

Lab 7-3 Routing Your Design ..................................................................................................... 7-24Aligning Devices ..................................................................................................... 7-24Pushing Components ............................................................................................... 7-25Moving a Single Component ................................................................................... 7-26Clustering the Aligned Devices ............................................................................... 7-27Creating Pins............................................................................................................ 7-29Editing Wiring Polygons ......................................................................................... 7-30Adding Connectivity to the Pins .............................................................................. 7-32Redefining the Boundary ......................................................................................... 7-33Setting Timing Rules for a Class ............................................................................. 7-34Removing Interlayer Rules ...................................................................................... 7-36Running the Router .................................................................................................. 7-37Using Split View to Examine the Connections........................................................ 7-38Examining the Tolerance Rule Routing................................................................... 7-38Wire Redundancy..................................................................................................... 7-40Protecting Nets......................................................................................................... 7-41Manually Creating Keepouts ................................................................................... 7-42Routing with Keepouts ............................................................................................ 7-44Deleting Keepouts.................................................................................................... 7-44Adding Angles to the Routing ................................................................................. 7-45Perform Same Net Checking ................................................................................... 7-45Using Critic and Miter Setbacks .............................................................................. 7-46Closing the CCAR Window .................................................................................... 7-47Translating Back to Design Framework II............................................................... 7-47

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Module 8 Analyzing and Updating Data

Lab 8-1 Engineering Change Order .............................................................................................. 8-1Opening a Cellview.................................................................................................... 8-1Invoking the Virtuoso-XL Setup ............................................................................... 8-1Changing the Schematic ............................................................................................ 8-1Starting Virtuoso-XL Again ...................................................................................... 8-2Verifying the Design.................................................................................................. 8-2Updating Components and Nets ................................................................................ 8-2Updating Parameters.................................................................................................. 8-3Deleting the Extra Devices ........................................................................................ 8-4Deleting Wiring ......................................................................................................... 8-4Placing the New Devices ........................................................................................... 8-5Translating the Design ............................................................................................... 8-6Routing the Design .................................................................................................... 8-6Translating to DFII .................................................................................................... 8-6Verifying the Design.................................................................................................. 8-7Steps for Updating the Design ................................................................................... 8-8Summary .................................................................................................................... 8-8

Module 9 Working with Hierarchical Designs and Variables

Lab 9-1 Lay Out a Hierarchical CMOS Design ............................................................................ 9-1Opening a Cellview.................................................................................................... 9-1Invoking the Virtuoso-XL Setup ............................................................................... 9-2Building the Layout ................................................................................................... 9-3Summary .................................................................................................................... 9-3

Module 10 Virtuoso Custom Placer

Lab 10-1 Defining Component Types........................................................................................... 10-1Starting the Software................................................................................................ 10-1Starting Virtuoso Layout Editor............................................................................... 10-1Opening a Schematic ............................................................................................... 10-2Invoking the XL Tool .............................................................................................. 10-2Generating the Design.............................................................................................. 10-3Defining Component Types..................................................................................... 10-3Generating the New Design ..................................................................................... 10-6

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Module 11 Pin Placement

Lab 11-1 Pin Placement................................................................................................................. 11-1Opening a Design..................................................................................................... 11-1Using the Pin Placer................................................................................................. 11-3Summary .................................................................................................................. 11-5

Module 12 Placement Planning and AutoPlacer

Lab 12-1 Placement Planning and AutoPlacer.............................................................................. 12-1Defining the Rows ................................................................................................... 12-1MOS Device Level Placement................................................................................. 12-3MOS Device Level Placement – Component Assisted Mode ................................. 12-6Setting Placement Styles for Power Supplies .......................................................... 12-6Placing the Components Using Auto Placer............................................................ 12-9Standard Cell Placement ........................................................................................ 12-10Opening a Schematic ............................................................................................. 12-11Invoking the XL Tool ............................................................................................ 12-11Defining the Rows ................................................................................................. 12-13Setting the Auto Placer Form................................................................................. 12-14

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Terminology Conventions

Mouse Use and TerminologyUse the mouse to move the cursor on the screen, to make selections from a menu, and to draw.

The basic uses of mouse buttons are shown in this graphic.

Term Action Icon Example

click Quickly press and release the specified mouse button. On

menus and forms, you use the left mouse button most of

the time.

double click Rapidly press the specified mouse button twice.

Shift-click

Control-click

Shift-Control-click

Hold down the appropriate key or keys and click a

specified mouse button.

draw through Define a box by pressing the mouse button at one corner

of the box, moving to the diagonally opposite corner of the

box with the mouse button held down, and releasing the

button.

pop up Press the middle mouse button.

pull down Move the mouse cursor to the menu name on the menu

banner, press and hold the left mouse button, move the

cursor down to highlight the menu selection, release the

mouse button to execute the selection.

Enter Type a command in an xterm window and press Return to

execute the command.

Select Position the cursor over a command and press the left

mouse button. Choose or pick are synonyms for select.

Click left

Doubleclick

2

Shift

Shift- click right

Drawthrough›

Clickmiddle

To repeat last commandTo undo points in a graphic

Click or select buttonTo choose commandsTo select options on forms

Pop-up menu buttonTo pop up menusTo pop up options windows by double clicking

To draw objects

To select menu command on pop-up menus

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Conventions Virtuoso-XL Layout Editor

xii Cadence Design Systems, Inc. 12/13/02

Labs for Module 1

Introduction to Virtuoso-XL

Lab 1-1 Using the Cadence Online Documentation System

Lab 1-1 Using the Cadence Online DocumentationSystem

Objective: Learn to use the new HTML-based Cadence onlinedocumentation.

The Cadence® online documentation system (CDSDoc) your web browser toread the Cadence product manuals for Virtuoso® XL and all other tools.

1. In a UNIX window, enter:

cdsdoc &

The Cadence Documentation window opens. Continue with the nextstep.

2. In the main Cadence Documentation window, ensure the Docs byProduct option is chosen.

12/13/02 Virtuoso-XL Layout Editor 1-1

Using the Cadence Online Documentation System Lab 1-1

3. Scroll down through the product list and double-click on the productnamed Virtuoso XL Layout Editor (or single-click on the + signpreceding the book name).

The field expands to show the documentation relevant to theVirtuoso-XL Layout Editor (VXL).

1-2 Virtuoso-XL Layout Editor 12/13/02

Lab 1-1 Using the Cadence Online Documentation System

4. Double-click on the book Virtuoso XL Layout User Guide.

The document page is loaded into your Internet browser. This maytake a moment. At the top of the window is a built-in tool bar thatlets you move forward and backward through the chapters. Thedocument also has hyperlinked cross-references.

5. Review the list of topics within the user guide that you justexpanded.

6. Double-click on the book Virtuoso XL Layout User Guide.

7. At the bottom of the CDSDOC: Library window, click on theSearch button.

A browser window will appear and load the product documentationinformation search window. If Netscape was not already invoked,this may take a moment as it will invoke Netscape automaticallywith the correct documentation page loaded.

Use the All of the Following buttons at the bottom of each of thesefields or select a specific family, product or book to narrow yoursearch. You can also reduce your search further by using theBoolean operators such as AND, OR, and NOT.

Note: You can also start the Cadence documentation from the Helpbutton in any Cadence window of the application.

8. In the Search for field (do not choose the option Go), enter:

.cdsinit

9. Choose Custom IC Layout from the Families group, chooseVirtuoso XL Layout Editor from the Products group, leave theBooks field selected as All of the Following, and click Go.

The results of your search show a number of document titles tochoose from. You can click on the cross-referenced text to findspecific information about the .cdsinit file.

10. Iconify the Search Results window.

End of Lab


Overview of the Design Flow Lab 1-2

Lab 1-2 Overview of the Design Flow

Objective: Step through the basic design flow on a CMOScircuit.

In this lab, you will follow the steps to create a layout using the Virtuoso-XLlayout editor tool. The emphasis is on observing how the different commandswork within the tool. The details on setup and tool behavior will be coveredfully in the rest of the course. It is important to follow the steps exactly in thislab.

Starting the Software


cd VXL_50/VXLFLOW

Note: To open a UNIX window, click the right mouse button in theUNIX background of your screen and selectTools—Terminal.

2. To start the Cadence Design Framework II software, enter:

layoutPlus &

Opening a Schematic

In the CIW, select File—Open, then type the following values in the OpenDesign form:

Invoking the XL Tool

You must change the tools to Layout XL in order for the menus to updatewith the XL commands.

Library Name designflow

Cell Name FFreva

View Name schematic



1. In the schematic, select Tools—Design Synthesis—Layout XL.

The Virtuoso XL Startup Option form appears. This form lets youopen an existing cellview or create a new cellview.

2. Select Create New and click OK.

The Create New File form appears.

By default the cell name is the same as the schematic name, and theview name is layout.

3. Click OK in the Create New File form to accept opening the librarydesignflow and the cell FFreva layout.

The layout window is opened and the windows are rearranged sothat you can see the schematic, layout, CIW and LSW all at once.This is the default setting. You will learn how to change the defaultsetting later in the class.

Notice that the layout window is empty since you created a newcellview.

Viewing the Window Banner

You may not be able to view the pull down menus from the window banner,because the windows have been moved up towards the top of the screen.

1. In any Cadence window, move your cursor to the edge of either theschematic or layout design window and click with the middle mousebutton.

2. By holding down the middle mouse button on any edge of a UNIXor Cadence window, you can move that window down if you can’tsee the top edge of that Cadence window.

Note: You can also stretch the edge of a window by using your rightmouse. A right click and drag on the window banner will alsomove the window.

3. Move the other design window down using the same steps.



Generating the Design

The next step is to place design elements, such as instances and pins, from theschematic into the layout window.

1. In the layout window select Design—Gen from Source.

The Layout Generation Options form appears.

From this form you can define which pins to generate, instances, orboundary. You can define each pins width, height, and layer. Youcan also specify which pins will be created during generation.

Once you have edited the form, you can save the information to atemplate file that can be loaded to reset your options.

2. At the bottom of the Layout Generation Options form, select theoption for Load Template File for Layout Generation.

3. In the text field below the Load Cyclic button type:

FFrevaLayGen.template

Do not press OK at the top of the Layout Generation Options form.

4. Select Load at the bottom right of the Layout Generation Optionsform.

The Layout Generation Options form is updated.

If you scroll the list of pins, notice that the layer for each pin and thewidth and height of four pins have been changed. Also, the nets gnd!and vdd! will each create two pins.

5. Turn on Transistor Chaining at the top of the Layout GenerationOptions form.

6. Click OK on the Layout Generation Options form.



7. Review the contents of the layout window. You may have to fit thewindow, to view all layout data. Select Window—Fit All, or pressthe bindkey f.

A rectangle on the prBoundary layer is drawn to show the estimatedsize of the design. This information was taken from the LayoutGeneration Options form.

Below the boundary are placed instances for each device specifiedin the schematic. This is a simple CMOS technology. The pmos andnmos devices are built with SKILL Pcells that have width and lengthparameters as well as parameters to control whether the sources anddrains have metal contacts or just diffusion pins. Because theChaining option was turned on in the Layout Generation form thedevices are sharing diffusions.

There are also pin shapes for each pin defined in the schematic.These were created on the metal1 dg, metal2 dg, and metal3 dglayers.

The components (devices and pins) are originally placed inrelatively the same position as they are found in the schematic.

Place the Components in the Boundary

1. In the layout window, select Edit—Place As In Schematic.

The components are mostly placed within the boundary. Becauseyou will be moving the devices around to create an optimalplacement, it does not matter that the devices do not fit into theboundary right now. But, you need to have all devices and pinsplaced inside the prBoundary before exporting your design to theCadence Chip Assembly Router tool.

You can change the size of the prBoundary from the LayoutGeneration form. If the prBoundary is still too small, use the EditStretch command to change the size of the rectangle.

Caution

All devices that were previously chained together are no longer chained. Thisis because the Place from Schematic command breaks the chaining.



Moving a Device

Use the Virtuoso Layout Editor commands to move any device to anotherlocation.

1. Use the Edit—Move command to move one of the devices in thelayout window.

Notice that the corresponding symbol in the schematic is highlightedand the flight lines appear.

2. Move the selected device to another location.

Notice that the flightlines stay with the device as it is being moved.

3. Press Esc to cancel the Edit Move command.

Examine the Design Connectivity

1. In the layout window, select Connectivity—Show IncompleteNets.

Notice that all of the incomplete nets are highlighted and theflightlines displayed.

Flight lines show the connections between the I/O pins and the pinson the devices. In the Show Incomplete Nets form you see a messageindicating how many incomplete nets there are. The number ofincomplete nets is displayed at the bottom of the Show IncompleteNets form.

2. Move the Show Incomplete Nets form over on top of the schematicso that you can see the results in your layout window more clearly.

Abutting Devices

Auto abutment allows you to overlap, partially or completely, two pcells tocreate a connection without introducing rule or connectivity errors.

1. In the Show Incomplete Nets form select NAND2_4|net11 from theincomplete nets section (may need to scroll that list of nets) and clickApply.



at theins

2. To better view the highlighted net select Zoom at the bottom of theShow Incomplete Nets form.

The Zoom button can be found at the bottom right side of the form.

The nmos devices each show the source as highlighted andconnected by a flight line. This indicates that both of the nets are thesame and the diffusion of the two devices can be shared.

To zoom out, choose Window—Zoom—Out by 2 from thewindow menu. You can also choose Window—Zoom—In to viewdevices closer.

3. Select Edit—Move and move the devices so that the source drainsoverlap as shown below.

Notice that the devices align, and the contacts from one of thedevices are removed. In the example above, the two gates are inseries on the schematic. The VXL rules ensure the devices are inseries in the layout as well.

4. Click Cancel on the Move form.

Select the device on the left. Move the device so thhighlighted source/draoverlap each other.



Permuting Pins

You can swap the source drain pins to achieve a better placement forconnections. Permuting pins on the same device is the same as swappingpins.

1. In the Show Incomplete Nets form select gnd! from the list ofincomplete nets and click Apply.

The gnd! nets are highlighted, click on the Zoom button at thebottom of the form to see the entire net.

2. Use the Window—Zoom—In command from the window menu tozoom your viewing area around any device that has flightlinesshown like the illustration.

3. Select Connectivity—Permute Pins.

A Permutation Information window appears. If this window doesnot appear automatically, press the F3 key.

4. Slide the Permutation Information Window either below the layoutwindow or on top of the schematic window. Do not close or hide thiswindow as it gives you information about the nets that you chooseto permute.



5. Click on the source and then click on the drain of any yellowhighlighted device as shown below.

Notice that the flightlines swapped, and the nodes that you clickedon are specified in the Permutation Information window.

The Permutation Information window shows you information aboutwhich pins have been permuted.

Note: If two mos devices are in series and already abutted, you cannot swap the source from one mos device to the drain of themos device it is in series with. Permute Pins works on anysingle device.

Click onthe highlightedsource.

Followed byclicking onthe drain.

The flightlinesare permuted,or swapped.



6. Click Cancel in the Permutation Information window.

7. To hide the incomplete nets select Connectivity—Hide IncompleteNets.

The flight lines are removed.

Updating the Connectivity Source

You will now take a different schematic and bind it to the existing layout.Notice that when you open the updated schematic that there are two extrabuffers in the design.

1. Select Connectivity—Update—Source.

2. Ensure the Cell property references the name FFreva_new in theDefine Connectivity Reference form as shown below and click OK.

Checking Against the Source

Now that you have sourced the schematic, you need to check the differencesbetween the schematic and layout.



1. In the layout window select Connectivity—Check—AgainstSource.

The Virtuoso XL Info window appears.

2. Scroll back in the Virtuoso XL Info window until you see:

“Layout instance ‘|BUF_0|N1’ is missing; expected to matchschematic instance’/BUF_0/N1’.

There are more devices in this new schematic than the layout.

3. In the Virtuoso XL Info window select File—Close Window.

Verifying Missing Devices

Use the XL Probe command to verify which devices are missing.

1. In the layout window select Connectivity—XL Probe.

2. Press the F3 key to bring up the Virtuoso XL Probe Options form.

3. Move your cursor into the schematic and click on the device BUF_0.

Within the schematic window you can use the window menucommand Window—Zoom—Zoom In if you want to see theinstance labels.

Notice in the Virtuoso XL Probe Options form there is nocorresponding layout for the schematic.

Click on BUF_0



4. To remove the layout probes press the Control-l bindkey in thelayout window.

5. Click Cancel.

Updating Components and Nets

Update the layout with the new schematic information.

1. Select Connectivity—Update—Components and Nets.

The Layer Generation Options form appears.

2. In the Generate section turn off Instances and click OK.

The pin and boundary information is updated. Notice that the twobuffers are not placed in the layout window. This is because youturned off the Instance option in the Layout Generation form. If youhad left the Instance option turned on, then the correspondingbuffers would be placed below the prBoundary.

Placing the Inverters from the Schematic

Use the Pick from Schematic command to place the instance from theinverter into the layout window.

1. Select Create—Pick from Schematic.

2. In the Pick from Schematic form select Unplaced.

3. In the Create From Schematic Component/Pin list click on the firstdevice in the list and click OK.

4. Move your cursor into the layout window. The first component ofthe BUF_0 buffer is ready for placement.

Do you see the corresponding devices?

Even though you selected one device in the list, all of the devicesfrom BUF_0 are ready to be placed, starting with the firstcomponent. After placing the first device, the other three devices aregenerated and ready for placement. All of these BUF_0 devicesmake up the one buffer.



5. Place the devices anywhere inside of the layout window.

6. Move your cursor into the schematic window and select the bottombuffer.

7. Move your cursor into the layout window and place the devicesanywhere in the design window.

8. Select Cancel to end the Pick from Schematic command.

9. In the layout window select Window—Close and do not save yourchanges.

You will be using a different layout for the rest of the lab where thedevices have been optimally placed.

Manually Creating Interconnect

In this lab you do not have time to create an optimal placement. Instead youwill open a layout window in which the devices have been optimally placedfor you. You will use the Create Path command to manually createinterconnect.

Select this buffer



1. Select File—Open, change the following to match the illustration,then click OK:

2. To add the Layout XL menu to the window banner, from theschematic window select Tools—Design Synthesis—Layout XL.Choose the Open Existing startup option and click OK.

Notice that the windows are rearranged and the schematic and layoutwindow are now synched together.

3. Select Connectivity—Check—Against Source.

Many messages appear in the Virtuoso XL Info window. Some ofthese messages can be turned off by adding the lxIgnoredParamsproperty.

If you want to update the parameters in the layout window you coulduse the Connectivity—Update—Layout Parameters.

4. In the Virtuoso XL Info window select File—Close Window.

If flight lines are turned on, turn them off by using theConnectivity—Hide Incomplete Nets command. The flight linesmake it difficult to view the connections of the path.



5. Select Create—Path in the layout window to manually createinterconnect.

If you click on Hide on the Create Path form, the form is hidden, andyou are still in the Create Path function. Press the bindkey F3 tobring that options form back.

6. Click on any one of the cyan pins in the middle of the design.

Notice the current drawing layer in the LSW updates to metal 3 dg,the net is highlighted in the schematic, and in the layout all pins thatare connected to this net are highlighted. You may have to zoom intothe area that you are editing in the layout withWindow—Zoom—In in order to view the highlighted pins.

7. Create a path by stitching from the M3 pin using the layers ofM3->M2->M1->poly to the gate pin. To complete one of theconnections do the following:

a. On the Create Path form choose the Change to Layer option.

b. Select a layer next to the metal layer you are currently on.

Only routing layers directly next to the layer you are on areavailable. A via is automatically added. You can select anotherlayer to step down to if you choose - which adds a via for thatlayer.

c. Press the Return key to finish the connection.

You do not need to complete all connections.

8. To save your cellview, select Design—Save.

Exporting to the Router

Instead of creating the interconnect manually, you will translate the layout tothe router and then route the design. Once the design has been routed, youwill translate back to design framework.

1. In the layout window select Route—Export to Router.

The Export to Router form appears.

2. Scroll all the way down to the bottom of the form.



3. Select Load Defaults.

4. Select ~/VXL_50/VXLFLOW/export.file and click OK.

The Export to Router form is filled out. The translation rules,cellview information, and options have already been defined in thisfile.

5. Click OK to start the export.

Notice in the CIW a message appears that the translation hascompleted successfully. The router is also invoked since that optionwas chosen at the bottom of the export form.

Loading the FFreva_new.do File

The FFreva_new.do file is a replay file that will invoke the commands toroute your design.

1. In the router window select File—Execute Do File.

2. In the Execute Do File form enter:

~/VXL_50/VXLFLOW/ccar/data/FFreva_new.do

3. Click OK.

Routing begins. The routing takes a bit of time to complete. Theobject is to demonstrate the routing capability, not to route acomplete design. You will go through more details on the CadenceChip Assembly Router in a later module to see the benefits of thistool.

4. If you do not want to wait for the entire design to be routed click thePause button. You do not have to route the entire design for this lab.

5. Select File—Quit in the CCAR window.

6. In the Save And Quit form click Save and Quit.

This saves the routed design to a~/VXL_50/VXLFLOW/ccar/data/FFreva_new.ses file. You will usethis file to import into Design Framework.



7. Click Yes to replace the existing session file.

8. When you see a warning that same_net_checking is off, click Yes tocontinue.

Importing from the Router

You will import the FFreva_new.ses file back into a layout window.

1. With the MPS utility, the layout cellview window within VXLshould already be updated with your routed design from CCAR.

If this is true, go to step 6.

Note: The MPS utility is a mechanism that automatically updatesthe information between design framework windows.

2. If your VXL layout window does not reflect your routed design, thenwithin the layout window select Route—Import from Router.

The Import from Router form appears.


4. Select the ~/VXL_50/VXLFLOW/import.file.

Change the Import Router File to~/VXL_50/VXLFLOW/ccar/data/FFreva_new.ses if it is not alreadyset.

The CIW tells you that the import has completed successfully.

The layout design window updates with the routing.

5. Close and save the design windows when you are done.

6. Select File—Exit on the Command Interpreter Window (CIW) toexit out of the software. This is the main Cadence window fromwhich you opened the cells from.



Summary

■ You learned the basics of the XL layout editor tool.

End of Lab


Labs for Module 2

Virtuoso-XL Setup

Lab 2-1 Starting Layout XL


Objective: Open a schematic and invoke layout XL.



cd VXL_50/PHYSDES


2. To start the Cadence® Design Framework II software, enter in thesame UNIX window:

layoutPlus &

Opening a Schematic


The vabffa schematic cellview opens for editing.

Starting Layout XL

1. Select Tools—Design Synthesis—Layout XL.

The Startup Option window appears.

2. Select Create New in the Startup Option window and click OK.

Library Name layoutDesign

Cell Name vabffa

View Name schematic


Starting Layout XL Lab 2-1

3. In the Create New File form, click OK to confirm the followingvalues:

An error occurs and the Virtuoso®-XL dialog box appears. ThelxExtractRules have not been defined in the technology file. In thenext steps we will add this information to the technology file beforeyou start Virtuoso-XL.

4. Click Close in all error windows.

Verifying the Technology File

View the contents of the technology file to verify that the lxExtractRules arenot present in the technology file.

1. In the CIW select Tools—Technology File Manager.

2. Click on the Edit Rules button.

The Technology File Edit Rules form appears.

3. In the Technology File Edit Rules form ensure that the TechnologyLibrary cyclic button is set to layoutDesign.

4. In the Classes field, select LX.

The Rules section updates to show you the rules that are in the LXclass. This does not mean that these rules are present.

5. Select File—Edit in the Technology File Edit Rules form.

The Technology File - LX Rules form appears.

6. Within the Technology File - LX Rules form, select Extract Layersfor the LX Rule.


Cell Name vabffa

View Name layout



7. Add the individual layers without their layer purpose in thefollowing order:

pwell, buried, isolation, ndiff, pdiff, poly, poly2, cont, metal1,via1, metal2, via2, metal3, via3, metal4.

Note: Click on the Browse button to invoke the browser. Click onone layer in the browser and then click on Edit in the LXRules form to add the layers. You can also just type in theindividual layer (without quotes) in the Layer line followedby a click on the Edit button.

The form will look like this when you are done. You can scroll thelist to see all of the Extract Layers that you added.

Verify that you have all the required layers by scrolling in this formthrough the layer metal4.


Starting Layout XL Lab 2-1

8. Click OK in the Technology File - LX Rules form.

9. Select File—Close in the Technology File Set Up form.

10. Select File—Close in the Technology File Tool Box form.

Starting Layout XL Again

1. In the schematic window select Tools—Design Synthesis—Layout XL.

Does the same dialog box appear?

No, because you have added the lxExtractRules to the technologyfile.

2. In the Startup Option form the Create New option is selected, clickon the OK button.

3. Click OK in the Create New File form accepting the followingoptions:

The vabffa layout cellview opens for editing.

Saving the Technology File

You must save the changes that you made to the technology file.

1. Enter the following command on the CIW command line:

saveTechLX()


Cell Name vabffa

View Name layout



2. Do not close the design windows. You will use this same schematicand layout for the rest of the module.

End of Lab


Adding Pins Lab 2-2

Lab 2-2 Adding Pins

Objective: Adding pins to the nmos and pmos devices.

Because the pins have not been added to the SKILL Pcells your design willhave no connectivity. If you do not have any pins in your devices then thereis no connectivity. You will learn how to add connectivity through a SKILLfile which creates the nmos and pmos devices.

Placing Devices

Place the one nand device in the layout window and view the connectivity.

1. In the schematic click on one of the nand symbols.

The nand is now selected.

2. In the layout window select Create—Pick from Schematic.

The Pick from Schematic form appears.

The Pick from Schematic command allows you to place instancesand pins one at a time or as a selected set. This way you controlwhere the instances are placed in the layout window. You will learnmore about the Pick from Schematic command in the next module.

3. Move your cursor into the layout window and place the mos devices.

Are you able to place the nmos and pmos devices with no errors?

Notice that in the CIW there are warning messages that the pcellevaluation for the nmos and pmos devices failed. Also warnings thatthe source and drain pins are not found. Later you will look in theSKILL file that creates the nmos and pmos devices to see why thepins are not being created.

4. Select Cancel in the Pick from Schematic form.

Reloading the SKILL File

To remove the warnings, reload the rodnopins.il SKILL file.


Lab 2-2 Adding Pins

1. In the CIW enter:

load “rodnopins.il”

2. To rebuild the nmos and pmos devices load the following functionby entering in the CIW:

rodDemoCreateMosPcellsNoPins()

3. In the layout window select Window—Redraw.

The pcells appear because the pcell SKILL code representing thepmos and nmos cells has been loaded.


If you had deselected the nand, you must select it again.

5. Place the devices from that nand in the layout window.

Notice in the CIW you receive warning messages that the S and Dterminals are missing. This is because the pins have not been addedto the nmos and pmos devices.

6. Select Connectivity—Show Incomplete Nets in the layoutwindow.

Is there any connectivity?

There is zero incomplete nets because the pins have not been createdin the pcells. You will view the file to see how the pins are createdusing ROD.

7. Select Cancel in the Show Incomplete Nets form.


Viewing the SKILL File

The rodnopins.il file creates the nmos and pmos devices. View this file tounderstand why the pins were not created.

1. In an xterm window enter:

vi skill/rodnopins.il


Adding Pins Lab 2-2

2. Search for rodCreateRect by entering:

/rodCreateRect

This takes you to where the left diffusion pin is created. Thediffusion pin is created by using ROD. Notice that termName,termIOType, and pin are commented out. These arguments createthe connectivity for the rectangle.

3. Press the n key to search for the next rodCreateRect statement.

Is all of the pin information commented out?

All pin information has been commented out in this file. The source,drain, and gate pins have not been created for the nmos and pmosdevices.

4. To close the file enter:

:q!

Loading the SKILL File

You will now load a SKILL file that has the pin information.

1. Delete the mos devices in the layout window.


load “rodpins.il”


rodDemoCreateMosPcells()

The rodDemoCreateMosPcells function updates the nmos and pmosdevices.

4. Select Create—Pick from Schematic in the layout window.

?termName specifies the name of the terminal

and net with which you want to

associate the shape.

?termIOType identities the direction of the pin.

?pin determines that the rectangle is a pin.


Lab 2-2 Adding Pins

5. Select one of the other nand symbols in the schematic that has notbeen placed previously in the layout window.

6. Place the corresponding devices from that nand by moving yourcursor into the layout window.


8. Select Connectivity—Show Incomplete Nets to verify theconnectivity. Move the Show Incomplete Nets form on top of theschematic so that you can see the layout window completely.

9. Choose the window menu command Window—Fit All in the layoutwindow to view all of the placed data.

10. In the Show Incomplete Nets form, press the Select All button andclick Apply.

Do you see the flightlines?

Yes, because the pins are added to the nmos and pmos pcells. Noticethat the flight line has a resistor shape to it. This specifies that the pinis weakly connected. Weakly connected pins can only be connectedfrom either the top or bottom of the gate. You will learn more aboutthis in the Creating Interconnect in Virtuoso XL module.


12. Select Connectivity—Hide Incomplete Nets in the layout window.

13. Do not close the design window.

End of Lab


Creating Interconnect Lab 2-3

Lab 2-3 Creating Interconnect

Objective: Create manual interconnect between devices.

Now that you have connectivity, you will want to connect the devices. As youconnect the devices notice that the highlighting of the net is not removed fromthe net when the connection is completed. This is because you do not havethe viaLayers set in the technology file.

Placing Devices

In the next steps, you will remove the devices that are placed, and place the Jpin and the nand that connects to that pin.

1. Delete all devices from the layout window. In the layout window,choose the Edit—Select—Select All command. To delete thedevices, choose the Edit—Delete command.



2. In the schematic select the J pin and device NAND2_1. Selectmultiple items with a left click on each item while holding the Shiftkey.

You can use the window menu Window—Zoom—Zoom Incommand if you want to magnify the devices in the schematic.

These devices are in the lower-left corner of the schematic.

3. Select Create—Pick from Schematic in the layout window.

4. Move your cursor into the layout window and place the devices.

5. Left-click in an open area to deselect all instances in the schematic.

6. Select Connectivity—Show Incomplete Nets in the layoutwindow.

Select the J pin and the NAND2_1 instance



7. In the Show Incomplete Nets form click the Select All button andclick Apply.

Do all of the devices have connections?

All devices except for the J pin have connectivity. The J pin is drawnon the cellBoundary layer which is not defined in thelxExtractLayers.


Moving the Pin

1. Move the J pin to the top of the design with the pulldown menucommand Edit—Move to the location as shown below:

Select theJ pin.



2. Select the J pin.

Do you see the corresponding pin highlighted in the schematic?

The Cross Selection option is turned off in the Layout XL Optionsform. Any device that you select in the layout window or schematicwindow will not be highlighted in the corresponding window.

3. Select Options—Layout XL in the layout window.

4. Turn on the Cross Selection option and click Apply.

5. Click on the J pin again.

Is the J pin highlighted in the schematic?

No, because the Cellview Options have been set so that CrossSelection is turned off. Cellview options apply only to one cellview,while the Global Options apply to the entire design environment.

6. Select Cellview Options at the top of the Layout XL Options form.

7. Turn on Cross Selection and click OK.

8. Click on the J pin again to verify that the pin is highlighted in theschematic and the layout.

9. Deselect the J pin in the layout window.

Now that you have learned about the Cross Selection option, you donot need the pin selected.

Creating the Connection

You will connect the J pin to the input of the nmos device. Use the CreateRectangle command to make the connection.

1. Select Create—Rectangle in the layout window.

2. In the LSW change the current drawing layer to metal1 dg.



3. In the layout window, draw three rectangles to make a connectionthat starts at the J pin and ends at the poly gate using metal1, cont,and poly as shown in the picture below:

Are the flightlines removed?

The flightlines are not removed because the viaLayers have not beendefined in the Layers class of the technology file.

4. Select the Escape key to stop the create rectangle command.

Adding the ViaLayers Rule

You will now add the viaLayers to the technology file using the Set Upcommand.

1. In the CIW select Tools—Technology File Manager.

2. Click on the Edit Rules button.

The Technology File Edit Rules form appears.

3. In the Technology File Edit Rules form ensure that the TechnologyLibrary cyclic button is set to layoutDesign.

Draw rectanglesas shown usingmetal1, cont, andpoly.

Incomplete netflightline indicatesneeded Via Layersrules.



4. In the Classes field, select Layer.

The Rules section updates to show you the rules that are in the Layerclass. This does not mean that these rules are present.

5. Select File—Edit in the Technology File Edit Rules form.

The Technology File - Layer Rules form appears.

6. Ensure the Layer Rule field is set to Via Layers.



7. Review the example of how to fill out the form.

Notice that you do not have to add the quotes or parentheses in thebottom three fields when adding the layers.

8. Add one layer rule at a time filling in the bottom three fields(Layer1, Via, and Layer2) followed by clicking Edit.

Note: You can either type in the layer names or use the Browsebutton to select the layer names.



9. Add each of the Via Layer rules as shown in the list below:

If you have more questions about how to add the ViaLayersinformation click on Help. If netscape is not currently open, youmay have to click on the Help button again after netscape hasopened.

10. When you have completed adding the ViaLayers click OK in theTechnology File - Layer Rules form.

11. Select File—Close in the Technology File Edit Rules form.

12. Select File—Close in the Technology File Tool Box window.

13. Enter the following command in the CIW command line:

saveTechVias()

Viewing the Changes

Reconnect the J pin to the input using paths and symbolic contacts.

1. Delete the existing connection that you just created from the J pin tothe nmos device.

2. Select Create—Path and click on the J pin.

Notice that the current drawing layer in the LSW automaticallychanges to metal1dg.

Layer 1 Via Layer 2

poly cont metal1

poly2 cont metal1

metal1 via1 metal2

metal2 via2 metal3

metal3 via3 metal4



3. Press the bindkey F3 to get the Create Path options. In the ChangeTo Layer field, change the layer option to poly dg.



4. Notice that the path which you are digitizing will place a via at yournext digitized coordinate. See the illustration below:

5. To end the path at the nmos device, either press the Return key ordouble-click the last coordinate of the path.

Are the flightlines removed from the J pin to the gate extension?

Yes, because the Via Layers have been added to the technology file.You should only see the flight line from the gate extension to thegate of the next device.


End of Lab


Auto Abutment Lab 2-4

Lab 2-4 Auto Abutment

Objective: Adding auto abutment rules

Auto abutment allows you to overlap or abut the source drains of devicesallowing you to share the diffusion. This saves you much space in yourdesign. Auto abutment rules are added to the SKILL Pcell. These rules definespacing between poly, contact, and diffusion. If you do not have the autoabutment rules defined in the SKILL Pcells then you will not be able to abutany cells. Also, chaining will not work if you don’t set the abutment rules.

Verifying Auto Abutment

Verify that auto abutment works with this design.

1. Select Connectivity—Show Incomplete Nets.

2. Look for any diffusions on devices that can be shared as shownbelow:

3. Move the devices so that the diffusions overlap.

Are the diffusions abutted properly?

The diffusions are not abutted properly because the abutment ruleshave not been defined for the nmos layout cellview.

Abut two deviceswhich have flightlines sharing drains



Adding Abutment Rules

1. In an xterm window enter:

vi skill/rodfixabut.il

2. Search for the abutment rules by typing:

/abutCondInclusion

You are now at the section that defines abutment.

The abutCondInclusion property conditionally includes or excludesthe contacts and connecting metal tab. The pcell parameter mustremove all features that are required for metal hookup and leave onlythe diffusion material to be stretched.

3. Search for vxlInstSpacingDir.

You can assign automatic spacing properties to pins of instances sothat if these pins are on different nets or the pins cannot abut for anyreason, the software automatically separates the instances by thedistance that you have specified.

4. Search for abutGateNet.

The abutGateNet parameter identifies the gate pins so the abutmentsoftware knows where the edge of the gate is.

5. Search for abutAccessDir.

The abutAccessDir property identifies the abutment accessdirection. Valid access directions are left, right, bottom, and top.



6. Search for abutStretchMat.

The abutStretchMat stretches the material toward or away from thegate when the instance is altered for abutment.

■ The first element in the list (leftSt) is the name of the stretchablematerial parameter.

■ The second element in the list (abutMinExt) is the rule forminimum diffusion overhang from the edge of the poly gate.

■ The third element in the list (abutRule1Ext) is thepoly-layer-to-poly-layer rule. This rule is used when the netconnecting the two instances do not share the net with any otherpin.

■ The fourth element in the list (abutRule2Ext) is thepoly-layer-to-diffusion rule. The rule is used when the gate widthis different for the two instances being abutted.

■ The fifth element in the list (abutContactExt) is the diffusionextension value used when one of the contacts needs to be addedduring the abutment process.

7. Close the file when you are done viewing the abutment rules.

Loading the Abutment Rules


load(“rodfixabut.il”)


rodDemoCreateMosPcells()

This rebuilds the nmos and pmos layout cellviews.

Abutting Devices

1. Move the devices away from each other.



2. Abut the two devices again.

Does auto abutment work?

Auto abutment does not work because the Auto Abutment option inthe Layout XL Options form is not turned on.

3. Select Options—Layout XL in the layout window.

4. In the Edit field at the top of the Layout XL form, turn on the GlobalOptions button.

5. Turn on Auto Abutment in the Layout XL form and click the Applybutton.

6. In the Edit field at the top of the Layout XL form, turn on theCellview Options button.

7. Turn on Auto Abutment in the Layout XL form and click the Applybutton.

8. Abut the two devices.

Are the devices abutted?

Yes, the devices are automatically abutted.

Changing Device Size

1. Select one of the devices that is abutted.

2. Select Edit—Properties in the layout window.

3. Select the Parameter button in the Edit Properties form.

How does the change relate to the abutment properties that were setin the rodabut.il file?

The abutment properties that have been added to the pcells specifythat the minimum poly to diff spacing is .1 micron. Either the LeftContact or the Right Contact parameter has been turned off since thetwo devices were in series within the schematic. The abutRule2Extis where the poly to diff spacing rule is defined.





End of Lab


Lab 2-5 Permuting Pins


Objective: Understand where the permuteRule is stored andhow to turn on permutability.

To abut any of the other devices in the layout, you must first have thepermuteRules added to the design. You can swap pins and abut source/drainsat the same time. You do not have to swap pins first, then auto abut devices.

Abutting the Pmos Devices

You will verify that the permuteRule has been added to the design by abuttingthe cyan pmos devices. The pmos devices have a common source drain thatneeds to be swapped before abutment. You will verify that the permuteRulehas been added to the design by abutting the two devices.

1. Select one of the cyan pmos devices.


3. Move the pmos device on top of the other pmos devices to abut thedevices.

Turn on Hide Incomplete Nets if you cannot easily view thedevices.

Are you able to abut the pmos devices?

No, you are not able to automatically swap the pins of the devicesand abut the devices because either the permuteRule has not beendefined for the pmos device or auto permute option has not beenturned on in the Virtuoso XL Options form. Instead of abutting thedevices, the devices are being spaced as per the vxlInstSpacing rulethat is defined in the skill file which creates the pmos device.

Verifying the permuteRule

You will verify that the permuteRule has been added to the pmos layoutcellview. If the permuteRule has not been added to the cellview, then youcannot automatically swap the pins or abut the two pmos devices. If thepermuteRule has been added to the cellview, then you will check to see if theautopermute option has been turned on in the VXL Options form.


Permuting Pins Lab 2-5


The pmos layout cellview opens for editing.

1. Select Design—Properties (or the Shift-q bindkey) to view theproperties of the cellview.

2. In the Edit Cellview Properties form select Property.

Is there a permuteRule?

The permuteRule is set to permute the S and D pins. This is not thereason you cannot permute the pins on the device. Next look at theXL Options form to verify that Auto Permutation is turned on.

3. Select Cancel.

4. Close the pmos layout cellview.

Verifying the XL Options Form

1. Select Options—Layout XL.

2. In the Global Options and Cellview Options area’s of the form, turnon Auto Permute Pins and click Apply.

3. At the top of the Layout XL Options form click on Cellview Options.Turn on Auto Permute Pins and click OK.

4. Move the cyan pmos device back over the pmos device on the rightso that the diffusions overlap.

Do the pins permute?

The Auto Permute Pins option automatically swaps the pins of adevice and abuts the source/drain diffusions.


Cell Name pmos

View Name layout




End of Lab


Adding Mfactor Lab 2-6

Lab 2-6 Adding Mfactor

Objective: Learn how to set up your design for one-to-manymapping.

Virtuoso-XL supports the use of a multiplication factor (m-factor) as aparameter to define a one-to-many parallel relationship between a device ina schematic and multiple instances of the device in the layout.

Setting Up

Remove the existing devices and place them again.

1. Select all devices in the layout and delete them.

2. Select the Nand2_1 device in the schematic.

This device is placed in the lower-left corner of the schematic.


4. Place the instances which represent Nand2_1 in the layout window.


Probing the Design

Probe the Nand2_1 device to view how many corresponding nmos and pmosdevices have been placed in the layout.

1. Select Connectivity—XL Probe.

The Virtuoso XL Probe Options form appears.

2. Select the NAND2_1 device in the schematic.

This device is placed in the lower-left corner of the schematic.

How many devices are highlighted in the layout?

Four devices are highlighted. Two are pmos devices and two arenmos devices.



3. Select Cancel.

4. Press Control-l in the layout window to remove the layout probes.

Note: You can also click in empty space in the layout window toremove the layout probes.

Adding Mfactor as a CDF

You will add the mfactor property to the nmos and pmos devices as aComponent Description Property (CDF).

1. In the CIW select Tools—CDF—Edit.

2. In the Edit Component CDF form, change the following:

Press the Tab key to update the form. Do not use the Return key asthat will apply the changes and close the form.

Caution

Make sure you make your changes to the Base CDF. Any changes you maketo the User or Effective CDF are not saved.

3. In the Component Parameters section of the form, select Add.

CDF Type (at the top right of the form) Base


Cell Name nmos



4. In the Add CDF Parameter form change the following:

5. Click OK in the Add CDF Parameter form.

6. Click Apply in the Edit Component CDF form.

7. In the Edit Component CDF form change the Cell Name to pmos.

8. Press Tab to update the form.

9. In the Component Parameters section of the form, select Add.

10. Add the same multiplication factor information as you did for thenmos device.

11. Click OK in the Add CDF Parameter form.

12. Click Apply in the Edit Component CDF form.



Changing the Multiplication Factor

You will change the multiplication factor for the pmos device to place twiceas many pmos devices.

1. In the Edit Component CDF form change the m value to 2.

2. Click OK in the Edit Component CDF form.

Verifying the Multiplication Factor

You will now verify that the multiplication factor has been changed to twofor the pmos devices.

1. Select and delete all of the existing devices in the layout.


3. Select Create—Pick from Schematic and place the NAND2_1device in the layout.


5. Click on the NAND2_1 device in the schematic.

How many pmos devices are placed in the layout?

There are only two pmos devices placed. The other two pmosdevices were not placed because the Generate Multiple Instanceoption was turned off in the Layout XL Options form.

6. Select Cancel in the XL Probe form.

Editing the Layout XL Options

1. Select Options—Layout XL.

2. Turn on the Generate Multiple Instance option and click OK.



Replacing the Devices

Place the devices once more to verify the mfactor for the pmos devices.

1. Select and delete the existing devices in the layout.


3. Select Create—Pick from Schematic and place the NAND2_1device in the layout.


5. Click on the NAND2_1 device in the schematic.

How many pmos devices are placed in the layout?

There are four pmos devices and two nmos devices. This is becauseyou changed the multiplication factor for the pmos device to two.

6. Select Cancel in the XL Probe form.

7. Do not close the windows.

End of Lab


Lab 2-7 Customizing the Desktop

Lab 2-7 Customizing the Desktop

Objective: Change environmental options by saving to the.cdsenv file.

You might want to change Virtuoso-XL options and environment options.You can set the options forms and then save the information to a .cdsenv file.The .cdsenv file is read when you start the executable layoutPlus. You canalso load the .cdsenv file while inside of layoutPlus.

Set Up Your Environment

1. Move and resize the LSW, CIW, schematic and layout windowsuntil they are arranged as you prefer.

2. In the CIW, select Options—User Preferences and choose whetheror not to have Scroll Bars enabled. You can also choose whether tomove the Fixed Menu, or disable it.

3. Click OK in the User Preferences form.

4. Select Options—Layout XL from the VXL layout window.

5. Select Help from the upper right corner of that options window.

Cadence online documentation opens in your internet browser. Thismay take a minute or two depending on the speed of your computer.

6. Read and scroll to the end of that document.

This document is the beginning of the different environmentalsettings that you can set in the .cdsenv file. Also covered are theoptions within the Layout XL environment.

7. Select File—Exit from your internet browser pulldown when youare done reading.


Customizing the Desktop Lab 2-7

Saving Your Environment

In the CIW, select Options—Save Defaults and fill in the Save Defaultsform as follows:

By using this file name, your environment will be loadedautomatically whenever you restart the software. The .classcdsenvfile is loaded from the .cdsinit file.

1. Click OK in the Save Defaults form, and overwrite if it exists.

Reloading the .classcdsenv File

1. In the layout window select Options—Display.

The Display Options form appears.

2. Select File.

Make sure that the file is set to ./.classcdsenv The .classcdsenv filewas updated with your new changes from the Save Defaultscommand.

3. Select Load From and click OK.

Verify that the forms are updated with all of your changes.

4. Close the layout and schematic windows without saving any edits.

End of Lab

Tool to Save All loaded tools

Save To File ./.classcdsenv


Labs for Module 3

Layout Generation

Lab 3-1 Generating a Layout from a Schematic


Objective: Understand how to use the Layout Generation Optionform.

In this lab you will use the Layout Generation form to place instances, pins,and the prBoundary into the layout window. The Layout Generation formallows you to specify different pin attributes for each pin. You can also turnon or off the creation of instances and prBoundary. Once you understand theLayout Generation form, you can easily generate your layout placements.

Opening a Cellview

In the CIW, select File—Open, then enter the following values in the form ifthis cell is not still already open:

The vabffa schematic cellview opens for editing.

Invoking Layout XL


2. In the Virtuoso XL Options form verify that the Open Existingoption is selected, and click OK.

3. Click OK in the Open File form.

Investigating the Layout Generation Form

Before you generate a layout, review the options on the form.

1. Select Design—Gen From Source.



Cell Name vabffa

View Name schematic


Generating a Layout from a Schematic Lab 3-1

2. Review the form as shown below:



Now that you are familiar with the Layout Generation form you will generatea layout using the different options.

Changing Pin Layers

1. In the Defaults section of the Layout Generation form change theLayer/Master to poly dg.

All of the layers in the Layer/Master cyclic field are defined in thelxExtractLayers in the technology file.

2. Select Apply Pin Defaults.

What layer are all of the pins on?

The pins are all on the poly dg layer. The pin layer will not updateunless you click on the Apply Pin Defaults option.

Removing Pins

Turn off the creation of pins during layout generation. To create these pinsmanually in your design you would use the Create Pin command.

1. Click on CLK and notice the Update area now shows the CLKproperties.

2. Turn off the Create button for the pin CLK.

3. Click on Update.

4. Click Apply.

5. Repeat the steps above for the pin CLR.

Creating a Feedthru Pin

Feedthru pins are needed when you know that you will have to put in an extraconnection later in the layout process, but don’t need the pin right at this time.



1. Select Add a Pin.

The Add A New Pin form comes up.

2. In the text field of the Add A New Pin form type:

feedthru

3. Click OK in the Add A New Pin form.

Do you see the new field that is added to the Layout GenerationOptions form?

All new pin information is added to the bottom of the overall pin listin the Layout Generation Options form. You may have to scroll tosee the full list. In the text field you can specify a unique name forthe feedthru pin and all of the other pin attributes.

You will keep the rest of the information the same for the feedthrupin.

Creating Labels

You create labels for pins so that you will always know the pin name. If youdo not add pin labels, the only way to find the pin name is by selecting thepin and invoking the Edit Properties command. You will turn labels on viathe Generate from Source (Layout Generation) form.

1. Within the Layout Generation form in the Pin Label Shape sectionclick on Label.

2. Select Pin Label Options.

The Set Pin Label Text Style form appears.

3. Set the Layer Name field to poly.

4. Set the Layer Purpose field to drawing.

5. Change the Height field to 0.5.



6. Click OK in the Set Pin Label Text Style form.

Changing the Size of the Boundary

You can generate the boundary for a specific size, or set a utilization size.

1. In the Boundary section change from Utilization to BoundaryWidth.

2. Change from Aspect Ratio (W/H) to Boundary Height.

3. Change the Boundary Width to 75.

4. Change the Boundary Height to 50.

Loading a Template File

You can reload a template file for the Layout Generations form if you needto regenerate your design.

1. At the bottom of the form, select Load Template File.

2. In the Load Template File text field enter:

generate.lxt

3. Click the Load field to the right of the text field.

Review the Layout Generation Options form with the changes justloaded.

4. Review the syntax of the template file in a UNIX window byentering:

more ~/VXL_50/PHYSDES/generate.lxt

Does the generate.lxt file reflect the options on the LayoutGeneration form?

Yes, pin and boundary information are saved to the generate.lxt file.Notice that the CLK and CLR pins are not listed in this file. That isbecause these options were turned off for the generation of thesepins.



5. Click OK to generate the layout.

6. To save a template of the existing layout generation options, chooseDesign—Save To Template from the layout window.

7. In the Template File Name field enter:

test.lxt

Verifying the Layout

1. Compare and verify the options that you set on the LayoutGeneration form to the components placed in the layout window.

Do you have two gnd! and vdd! pins?

Yes, because you specified two pins. These pins are placed justbelow the prBoundary.

Have the CLK and CLR pins been created?

No, because you turned off the generation of the pins.

What layer are the pins on?

The pins are on poly1 dg. To verify the layer use theEdit— Properties command.

How large is the boundary?

The boundary is 75 by 50. Use the Window—Create Rulercommand to verify the size.

Do you have a feedthru pin?

Yes, because you added a pin named feedthru.

Regenerating Your Design

If you have components placed in the layout window and invoke the GenFrom Source command, all devices and wiring will be deleted.

1. Select Design—Gen From Source.

2. Click Yes in the Virtuoso XL dialog box.

All devices and wiring is deleted from the design.



3. Select Transistor Chaining.

4. Click OK in the Layout Generation Options form.

5. Click Yes in the Virtuoso-XL dialog box.

All devices and wiring is deleted from the design.

6. Select Window —Close in both the schematic and layout windows,choosing Save to save your design.

7. Do not exit the layoutPlus session.

Summary

■ You learned about the options on the Layout Generation form.

■ You learned how to generate a design using different options fromthe Layout Generation form.

End of Lab


Cloning Lab 3-2

Lab 3-2 Cloning

Objective: Become familiar with the Clone command.

Cloning is the ability to replicate a section of the layout and still maintainconnectivity by preserving the hierarchical structure of the design. You canclone devices, pins, and (if selected from the layout window) interconnectstructures such as wires and paths made of shapes. You will learn how to takepart of a layout and use the cloning feature to build other parts of the design.



cd ~/VXL_50/PHYSDES/REF



layoutPlus &

Opening a Cellview

In the CIW, select File—Open, then enter the following values in the form ifthis cell is not still already open:

The encode schematic cellview opens for editing.

Invoking Layout XL


2. In the Startup Options form select Create New.

Library Name 50TRO

Cell Name encode

View Name schematic


Lab 3-2 Cloning

3. Click OK in the Startup Options form.

4. In the Create New File form, modify the View Name field:

Note: If the window appears stating the file already exists, click Yesto overwrite the existing file.

Generating the Cloned Objects

1. In the schematic window, hold your Shift key and select the and3_2xinstances of I0 and I1:

Library Name 50TRO

Cell Name encode

View Name layout_vxl


Cloning Lab 3-2

2. In the layout window, select Create—Pick From Schematic.

3. In the Pick from Schematic form, set the following options:

4. Move your cursor into the layout window and place the layoutinstances in the layout window.

Press the Esc key to cancel the command.

5. Select Cancel at the top of the Pick from Schematic form.


Lab 3-2 Cloning

6. Arrange the placement of the devices with the pmos devices over thenmos devices how you wish.

7. Select Edit—Select—Select All ( or the Control-a bindkey) toselect all of the layout objects including any optional wiring youmay have completed.

8. Select Create—Clone in the layout window.

Notice the prompt in the bottom of the layout window: SelectConnectivity Source, hit <Return> after selection.

9. Since our objects are already selected, press your Return key.

Press your F3 key if the Cloning form does not automatically comeup.


Cloning Lab 3-2

10. Within the bottom half of the Cloning form, select Find MatchingTargets.

This step could take a few minutes. Wait while the tool scrutinizesyour hierarchy and the command returns the result that shows in theUnplaced and Placed fields of the form.

11. Click on one of the matching targets in the Unplaced field.

The corresponding schematic instances will be selected.

12. Click the Clone button from the Cloning form.

13. Move your cursor to the layout window and place the cloned objects.

14. Click on Cancel in the Cloning form.

15. Use the Virtuoso®-XL functionalities, such as Probe and CrossSelections, to check connectivity on the cloned objects.

16. Select Design—Save in the layout window.

17. Do not close these layout or schematic windows.


Lab 3-2 Cloning

Cloning the Inverters

This exercise will show you how to clone the layout that was previouslycreated as a part of the 4_inv cell into the encode block.

Important

Make sure not to close the layout or schematic windows from the lastexercise.

1. In the CIW, select File—Open, then enter the following values inthe form if this cell is not still already open:

The encode schematic cellview opens for editing.


3. In the Startup Option form select Open Existing.

4. Click OK in the Startup Option form.

5. In the Open File form, ensure the settings within the fields:


Library Name 50TRO

Cell Name 4_inv

View Name schematic

Library Name 50TRO

Cell Name 4_inv

View Name layout


Cloning Lab 3-2

7. Within the 4_inv layout window, select the two groups of devices(pmos and nmos pairs) on the right.

8. From the 4_inv layout window, select Create—Clone.

9. Press the Return key since the objects are already selected forcloning.

Wait while the tool scrutinizes your hierarchy and the commandreturns the result that shows in the Unplaced and Placed fields of theform.


Lab 3-2 Cloning

10. Within the Cloning form, set the Target Schematic field to thefollowing:

The Target Layout field is automatically updated to reflect theVirtuoso-XL pair.

11. Click on Find Matching Targets in the lower half of the Cloningform.


Cloning Lab 3-2

12. Examine the search results by clicking on each target and comparingto the schematic view.

13. Choose any target and click on Clone in the form.

14. Select Design—Save in the layout window.


Lab 3-2 Cloning

15. Take some time to explore the options in the Clone command andexamine the layout results.

16. Select Window—Close in the layout window.

17. Choose No in the Save Changes window.

18. Select File—Exit on the Command Interpreter Window (CIW) toexit out of the software. This is the main Cadence window fromwhich you opened the cells.

Summary

■ You learned how to clone devices in a design library.

End of Lab


Cloning Lab 3-2


Labs for Module 4

Editing Placement

Lab 4-1 Editing Placement


Objective: Use the different XL commands to create an optimalplacement.

In this lab you will have layout generation place the pins and prBoundary inthe layout window. You will place the instances in the layout by using thePick from Schematic command. You will learn how to use the XLcommands that will help you in creating your placement.



cd ~/VXL_50/PHYSDES



layoutPlus &

Opening the Schematic


The vabffb schematic appears for editing.


2. In the Virtuoso XL Startup Options form select Open Existing andclick OK.


Cell Name vabffb

View Name schematic


Editing Placement Lab 4-1

3. Click OK in the Open File form to confirm opening the vabffblayout cellview.


The next step is to place the pins from the schematic into the layout windowand generate the prBoundary. In this design example you will not place theinstances through the Layout Generation form, but from the Pick fromSchematic form.


This command regenerates the devices in this layout view.

2. In the Virtuoso-XL information window that pops up, select Yes toconfirm this action.

This window warns you that when you select OK from the Gen FromSource command (Layout Generation Options form), you will deleteall constraints, wiring, and instances at that time.


3. Make sure the Instances option is selected near the top of the LayoutGeneration Options form.

4. To load an existing template file, select the Load Template File forLayout Generation option at the bottom of the Layout GenerationOptions form.

5. In the text field enter:

vabffb.lxt

6. Click the Load option to the right of the in the Load Template textfield.

7. Within the Layout Generation form in the Pin Label Shape field,click on Label.



8. Select the Pin Label Options button.

The Set Pin Label Text Style form appears.

9. In the Set Pin Label Text Style form change the Height field to 0.5.

10. In the Layer Name field, select the option Same As Pin. This willset the pin label to be the same layer as the pin.

11. In the Layer Purpose field, select the option Same As Pin.

12. Click OK on the Set Pin Label Text Style form.

13. Turn off Instances near the top of the Layout Generation form.

The Instances button was turned on previously so that the boundaryand pins would be updated. The instances will not get regenerated;they will use the existing placements.

14. Review the list of pins being created.

15. Click OK on the Layout Generation form.

16. Review the contents of the layout window. You may have to fit thewindow. Select Window—Fit All or press bindkey f to view all ofthe data.

Is this what you expect to see?

The data in the design window matches the options set in the LayoutGeneration form. Labels were created for each pin and no instanceswere placed in the layout because you turned that option off.

Placing the Instances

You will use the Pick from Schematic form to place the instances in thelayout.

1. Select Create—Pick from Schematic.

2. Select one of the nand symbols in the schematic and move the cursorinto the layout window.



3. Click anywhere inside the prBoundary to place the devices.

Notice that the nmos and pmos devices are placed together.

4. Select another nand symbol.

You can press the F3 bindkey to reveal the Pick from Schematicform, if you selected the Hide button on the form.

5. Select Place Individually on the Pick from Schematic form.

The Pick from Schematic form updates. This option will allow youto place each of the instances from the corresponding symbolindividually.

6. Select another nand symbol.

7. Move your cursor into the layout window and click to place thedevice.

How many devices were placed?

One device was placed. The Pick from Schematic commandprompts you to place the next device until each of the devices forthat nand are placed.

8. Select Defaults at the top of the Pick from Schematic form to set theform back to the original settings.

9. Select the Cancel button on the Pick from Schematic form.

Chaining Devices

You can abut source/drains as you place devices.


2. In the Pick from Schematic form turn on Transistor Chaining.



3. Select another nand from the schematic that you have not placed andmove your cursor into the layout to place the devices.

Note: If a device does not place into the layout window with theflightlines to your cursor, that device is already placed inyour layout window.

Are the source/drains of the devices shared?

The source/drains of the nmos and pmos devices are shared. If thedevices were not abutted then check that the Auto Abutment optionis turned on in the Layout XL Options form. You must also have theabutment rules set for the SKILL pcells, and a component type mustbe defined for the nmos and pmos layout.

Completing the Design

Complete the placement of devices in the layout following the next steps.You will wire the devices in the next chapter.

1. In the Pick from Schematic form turn off Draglines.

2. Select another symbol in the schematic.

3. Move your cursor into the layout window and click to place thedevices.

Can you see the flightlines between the devices?

The flightlines are not visible because the Draglines option has beenturned off.

4. Turn back on Draglines and place the rest of the instances tocomplete the layout.

If you select a symbol and are not able to place it in the layout, thenyou have already placed the corresponding devices.

5. Select Connectivity— XL Probe and probe each of the symbols inthe schematic.

Another way to verify that all devices have been placed is to invokethe Connectivity—Check—Against Source command.

6. Select Cancel when you have placed all of the instances.



Examine the Design Connectivity

1. In the layout window, select Connectivity—Show IncompleteNets.

Flight lines show the connections between the I/O pins and the pinson the devices. In the Show Incomplete Nets form you see a messageindicating how many incomplete nets there are.

2. From the listing of complete nets select the gnd! net.

3. Select Apply.

4. Click on the Cycle cyclic field (or As Is cyclic field) to change thecolor of the flightlines for the gnd! net.

5. Change the color to y4 and click Set Color.

Does the color of the flightline update?

The color of the flightline changes to cyan. If you do not like thecolor of the y0-y9 layers, then you can change the color through theDisplay Resource Editor. The editor can be found in the LSWwindow under the Edit pulldown.

Abutting Devices

You can overlap, partially or completely, two pcells to create a connectionwithout introducing rule or connectivity errors.

1. In the Show Incomplete Nets form select gnd! and click Apply.

2. To better view the highlighted net select Zoom.

The nmos devices each show the source has being highlighted andconnected by a flightline. This indicates that both of the nets are thesame and the diffusion of the two devices can be shared.



3. Find two single-gated mos transistors on the far right of the cellview.Select Edit—Move and move the devices so that the source drainsoverlap as shown below in the illustration on the right.

Notice that the devices align, and the contacts from both of thedevices are removed. Contacts are not placed on the shared diffusionbecause the shared net does not connect to any other net.

Splitting Devices

There are two different ways to split devices into fingers. The first way is toadd a parameter to the SKILL pcells that splits the devices into equal sizefingers. The second way to split devices into fingers is to use the EditTransistor Folding command. Transistor Folding allows you to specify thewidth of each finger. You will explore both ways of transistor splitting in thissection of the lab.



1. Select the device on the right that you previously abutted.

2. Select Edit—Properties.

3. Select Parameter.

4. Change Number of Fingers to 2 and click OK.

Are the devices still abutted?

The abutRule2Ext rule set in the pcell determines the poly todiffusion spacing. You can verify the spacing by looking at the~/VXL_50/PHYSDES/skill/rodabut.il file. Search for abutRule2Ext.

Transistor Folding

You will use the Transistor Folding command to split devices into differentlength gates. Previously you split gates into equal sizes.

1. Select Window—Fit to view the complete design.



2. With the flightlines and connectivity shown, choose anysingle-gated mosfet transistor that shows common connectivityfrom the source or drain to another nearby source or drain fromanother mosfet transistor.

Note: Make sure that you have two separate transistors, not devicesthat already have two gates with a series connection. Use theEdit—Move command if you need to separate two devices inseries.

This example shows zooming in on two devices in the upper rightcorner of the overall set of transistors.

3. To better view the area of the two transistors as shown above, selectWindow—Zoom—In.

4. Select Edit—Transistor Folding.



5. Select one of the two mosfet devices (the larger gate-width device)by left-clicking on the device.

The name of the device appears in the Set Transistor Folding formwithin the Transistor Name field.

6. Change the Number of Fingers value to 3 and click on Set FingerWidths.

7. Set the width of each gate to 1, 1.5, and .5.

If the device width is too small to allow these three increments,choose another device that has a larger gate width.

8. Select Apply.

9. Move your cursor into the design window and click to place thedevices.

If you have devices that are abutted together you must unabut thembefore you can split them into multiple gates using the TransistorFolding command.

Permuting Pins

You can swap the source drain pins to achieve a better placement forconnections.

1. In the Show Incomplete Nets form select gnd! and click Apply.

The gnd! nets are highlighted.

2. Select Connectivity—Permute Pins.

Press the F3 key to bring up the Permute Information window if thiswindow does not appear automatically.



3. Click on the source and drain of any highlighted device as shownbelow.

Notice that the flightlines update.

In the Permutation Information window you receive informationabout which pins have been permutted.

Caution

If you are not able to permute the pins, change the CDS_Netlisting_Modevariable to Analog or change it to Compatibility in the .cshrc file. Alwaysresource the .cshrc file in your UNIX window after any changes followed byreopening Cadence. The .cshrc file resides in your home directory.

4. Click Cancel in the Permutation Information window.

5. To hide the incomplete nets select Connectivity—Hide IncompleteNets.

The flight lines are removed.

Where do you define the permute rule?

The permute rule can be defined as a CDF, or on the symbol, or onthe layout instance. The Auto Permute Pins option must be turnedon in the Layout XL options form even if the permute rule is defined.



Creating Additional Pins

We will replace the gnd! and vdd! pins as we would like to have power andground rails. You will create the gnd! and vdd! pins using the Create Pincommand.

1. Select the vdd! and the gnd! pins and delete them.

2. In the LSW, change the current layer to metal1 dg.

3. In the layout window, select Create—Pin.

4. If the title of the form denotes Create Shape Pin proceed to the nextstep. If the title of the form does not denote Create Shape Pin, thenclick on the Shape Pin mode towards the top of this form.

5. In the Create Shape Pin form change the following:



6. Draw the rectangles for the vdd! and gnd! pins. As you draw eachpin, you will place the label for that pin in a location on the bus pin.Make your design look similar to the following:



Moving Components into Optimal Placement

Next you will move the devices so that you have a more optimal placementas shown below:



1. Use the following commands to edit the components for optimalplacement.

■ Edit—Move

■ Edit—Other—Align .

■ Edit—Other—Swap Components

■ Connectivity—Permute Pins

■ Auto abutment

When you are done, the layout might look something like this:

Tips on Placement

1. Place all pmos devices on the top and all nmos devices on thebottom. Use the Edit Properties command to find out if the devicesare nmos or pmos devices.



2. Abut devices that can share source/drain diffusion.

3. Permute source/drains that can be abutted.

Completing Placement of Components

Once the devices are placed you can lock the devices to their placement.

1. Select the cyan pmos devices with a select-window by draggingyour left-mouse around the devices.

You should have 22 devices selected.

2. Select Edit— Other —Lock Selected.

3. Select Edit —Move and try to move the select pmos devices.

Can you move the devices?

The devices cannot be moved because they are constrained to theirexact location. If you changed the Constraint Assisted Control toignore on the Edit Move form, then you would be able to move thedevices and the constraint would no longer be valid.

4. When you have finished placing all components, save your designby selecting Design—Save in the layout window.

5. Close both the schematic and layout windows by selectingWindow—Close.

6. In the CIW, select File—Exit.

End of Lab


Labs for Module 5

Creating Interconnect in Virtuoso-XL

Lab 5-1 Basic Interconnect Tasks


Objective: Create interconnect and highlight incomplete nets.

In this lab, you will be working on a very simple design consisting of pins andresistors.

Before You Start

1. Close any VXL sessions that were open from previous labs. Go tothe following directory in your UNIX window prior to opening thenext VXL session:

cd ~/VXL_50/PHYSDES

2. Open a new Cadence® session by entering:

layoutPlus &

Opening a Cellview

In the CIW, select File—Open, then type or choose the following values inthe form:


The resBank layout cellview opens for editing.

This design is a set of resistors with input and output pins defined.The layout generation and placement is done for you.

2. In the layout window, select Options—Display.

Library Name overview

Cell Name resBank

View Name layout


Basic Interconnect Tasks Lab 5-1

3. In the Display Options form, set the following:

4. Click OK in the Display Options form.

Invoking Virtuoso-XL

1. In the layout view, select Tools—Layout XL.

The schematic window opens and the windows are arranged in theVirtuoso®-XL setup.

2. In the layout window, select Options—Layout XL.

Enabling Auto Permute

1. In the Layout XL Options form, turn on Auto Permute Pins andclick OK on the form.

2. Select one of the resistors with a left-click.

3. Select Edit—Properties (or press q).

The Edit Instance Properties form appears.

4. Within the Edit Instance Properties form, click on the Propertyfield.

5. Ensure that the following value accompanies the permuteRuleproperty:

p(PLUS MINUS)

6. Check each of the other resistors to make sure permuteRule is aproperty for each resistor.

7. Select Cancel in the Edit Instance Properties form.

Display Levels

From 0

To 32



Checking the Connectivity

1. In the layout view, select Connectivity—Show Incomplete Nets.

2. Click Select All and then Apply.

How many incomplete nets are there?

Look at the bottom of the Show Incomplete Nets form. There are sixincomplete nets. Notice that the flightlines from the pins on the leftside of the cell actually go to the pins on the right side of theresistors. The pins on the right side of the cell go to the pins on theleft side of the resistors.

3. Leave the Show Incomplete Nets form open, moving it to the side ofthe layout window.

Creating Interconnect Using Shapes

With the use of auto permute we will demonstrate how the two terminals onthe resistor can swap connectivity automatically. Properties within theresistor cell are already defined on the cell instances to allow these twoterminals’ connectivity to be swapped. Since we enabled the Auto PermutePins feature from the XL Options form, we have everything needed to swapthe pins automatically.

1. Look at the In1 pin in the top-left of the layout.

From the color of the incomplete net flight line and the outlinearound the pins they connect to, you can see that this pin isconnected to the right pin of the top resistor and not the pin on theleft side of the resistor.

2. In the LSW, change the current drawing layer to metal1 dg.

3. Move your cursor into the layout view and selectCreate—Rectangle or choose bindkey r.



4. Create a rectangle that overlaps both the In1 pin and the left pin ofthe top resistor.

What happens to the flightline?

The flightline is removed, because you completed the connection. Inthe Show Incomplete Nets form, you see that there are now only fiveincomplete nets. Net In1 is not listed as Incomplete.

5. Look at the In2 pin in the middle-left of the layout.

From the incomplete net flight line, you can see that this pin issupposed to be connected to the right pin of the middle resistor, butwe will connect it to the left pin of the middle resistor.

6. Move your cursor into the layout view and select Create—Polygonalso defined with the bindkey P.

7. Create a polygon that overlaps both the In2 pin and the left pin of themiddle resistor.

Notice that the incomplete net flight line that was previously shownbetween the In2 pin and the resistor pin from the right side is gone.



8. Look at the Out1 pin in the top-right of the layout. From theincomplete net flight line, you can see that this pin is supposed to beconnected to the right pin of the top resistor.

The Out1 pin is on the metal2 dg layer and the pin on the resistor ison the metal1 dg layer. Using only polygons and rectangles, createshapes on the metal1 dg, via dg, and metal2 dg layers to connectthese two pins. Do not worry about design rules for this exercise.The via dg layer connects metal1 to metal2.

Note: To end a path or polygon, you can either double-click on thelast point, or press on the Return key. The command that isexecuted is:

mouseApplyOrFinishPoint()

The shapes may look like the following:

How do the flightlines change as you create the connection?

Notice that as you add each shape, the incomplete net flight linechanges to show the connection between the closest two shapes.When all of the shapes are created, the incomplete net flight line thatwas previously shown between the Out1 pin and the resistor pin isgone. These layers are viewed as electrically equivalent based on theviaLayer function definition in the technology file.

9. Look at the Out2 pin in the middle-right of the layout. From theincomplete net flight line, you can see that this pin is supposed to beconnected to the right pin of the middle resistor. The Out2 pin is onthe metal2 dg layer while the pin on the resistor is on the metal1 dglayer.



10. Using rectangles on the metal1 and metal2 layers and the M2_M1contact, make the connection between the pins. Use theCreate—Contact command or the bindkey o to place the contact.The layout may look like:

Notice that the incomplete net flight line that was previously shownbetween the Out1 pin and the resistor pin is gone.

Creating Interconnect with the Path Command

1. Select Connectivity—Hide Incomplete Nets so the incomplete netflight lines do not obstruct your view of the probes.

2. Look at the In3 pin in the bottom-left of the layout.

From the color of the incomplete net flight line, you can see that thispin is connected to the right pin of the bottom resistor and not the pinon the left side of the resistor.

3. In the LSW, change the current drawing to text dg.

4. Select Create—Path or the bindkey p.

5. Click on the In3 pin.

What is the current drawing layer set to in the LSW?

The current drawing layer in the LSW is set to metal1 dg. Also,notice that the net is highlighted in both the schematic and the layoutviews. In the schematic, the wires and pins associated with the netare highlighted. In the layout, there are no shapes on this net yet, soonly pins are highlighted.




7. The flightline shows where you need to connect the path to theresistor. But with this resistor, you really want to connect to the otherside of the resistor. Connect to the left pin on the resistor.

Note: To end a path or polygon, can either double-click on thelast point, or press Return key. The command that isexecuted is:

mouseApplyOrFinishPoint()

Notice that the pins of the resistor are now swapped.

8. Look at the Out3 pin in the bottom right of the layout.

From the incomplete net flight line, you can see that this pin issupposed to be connected to the right pin of the bottom resistor. TheOut3 pin is on the metal2 dg layer while the pin on the resistor is onthe metal1 dg layer.

9. Select Create Path or the bindkey p.

10. Click on the Out3 pin.

Notice that the current drawing layer in the LSW is set to metal2 dg.Also, notice that the net is highlighted in both the schematic and thelayout views. In the schematic, the wires and pins associated withthe net are highlighted. In the layout, there are no shapes on this netyet, so only pins are highlighted.

11. Use path stitching to complete the wiring on this net. To accomplishthis you will need to change from the metal2 dg layer to the metal1dg layer. Press the bindkey F3 if you do not see the Create PathOptions form. Select the Change To Layer option in the CreatePath form to drop a contact or via between the two layers.



12. After changing layers, left click a coordinate where you want toplace the via. Press Return while your cursor is over the right pin ofthe bottom resistor to complete the connection to the resistor. Thelayout will look like the following:

The path ends and the net highlights are turned off.

Are there any incomplete nets listed in the Show Incomplete Netsform?

There are no incomplete nets in the Show Incomplete Nets form.You have completed all connections.


Moving Pins and Keeping Connectivity

You can move the pin with the path when you use the Maintain Connectionsoption.

1. Select Options—Layout Editor from the layout window pulldown.

2. Turn on Maintain Connections.

3. Click OK in the Layout Editor Options form.

4. Select the In3 pin.

5. Move the In3 pin to a different location.

If you move the In3 pin on top of one of the other shapes withmetal1, you will see a marker flag.

6. Deselect the pin when you are done.



Starting a Path Over Multiple Shapes

1. Select Create—Path or the bindkey p.

2. Click on the contact between the Out2 pin and the resistor.

A form appears offering you a choice of which layer and net tocreate the path.

3. Double click over your choice or single click and then click OK inthe form.

The net is highlighted in the schematic and layout views. You couldcontinue at this point to wire the net.

4. Press Esc to leave the Path command.

Creating a Short in Your Design

1. Use the Path command to create a short in your design.

You should now see markers indicating a short.

2. To find out what the error is, select Verify—Markers—Find.

3. Turn on Zoom to Markers in the Find Marker form and click onNext.

You zoom into the error, and a Marker Text window appears withthe error message.

4. Click on Cancel when you have viewed all of your errors.

5. Close the resBank layout and schematic. You do not need to save.



Summary

In this lab you have:

■ Learned how to create interconnect with shapes.

■ Created interconnect with the Create Path command andreviewed the use of path stitching.

■ Used the Status, Incomplete Nets and Markers commands toevaluate the connectivity and errors.

End of Lab




Objective: Use the interconnect techniques you learned tocreate the interconnect for the vabffb layout cellview.

Opening a Cellview



If you did not complete the module lab Editing Placement, you canuse vabffb placed instead.

Invoking the XL Setup


The schematic window opens and the windows are arranged with theXL setup.

Wiring the Design

1. Use the interconnect techniques to wire your design.

During wiring, you may find that some changes in placement areneeded. Do whatever is needed to the placement to create goodconnectivity without shorts or overlap errors. Do not try to followany specific design rules.

2. Use the Check Against Source, Show Incomplete Nets and VerifyMarkers commands to evaluate the connectivity.

3. Save your design frequently by selecting Design—Save.


Cell Name vabffb

View Name layout



4. Close both the schematic and layout cellviews.

5. In the CIW window, select File—Exit closing all VXL sessions andsaving all cellviews.

Summary


■ Learned how to create interconnect in your design.

End of Lab


Labs for Module 6

Wire Editor

Lab 6-1 Using Wire Editor


Objective: Use the commands in the Wire Editor

In this lab, you will create a layout using the Wire Editor utility within theVirtuoso® XL layout editor tool. The emphasis is on observing how thedifferent commands work within the tool. The details on setup and toolbehavior will be covered fully in the rest of the course. It is important tofollow the steps exactly in this lab.



cd ~/VXL_50/WE_COMMANDS


2. To start the Cadence® Design Framework II software, enter:

layoutPlus &

Opening a Schematic




The schematic window opens and the windows are arranged in theVirtuoso-XL setup.


Library Name WireCom

Cell Name encode

View Name layout.plc


Using Wire Editor Lab 6-1

Enable the Wire Editor

1. In the cellview window select Options—Layout XL.

2. Click on Enable Wire Editing near the left middle of the form.

3. Click OK.

Set the Routing Rules

1. Select Options—Route in the cellview window to display the RouteOptions form.

2. Click to enable the Rules field towards the bottom of this form.

3. Enter the following into the rules field:

vcr/rules/routerDigital.rules

4. Click OK on the Route Options form.

Show Incomplete Nets


2. Click on Select All.

3. Click OK.

Begin Using the Wire Editor

1. Select Window—Fit All to have the design view at full size in thedesign window.

Create the Power and Ground Rails

1. Select Create—Path to start the path command.



2. Near the coordinate X:0 Y:7, click with your left mouse button on themetal2 vdd! pin to enter the path.

3. Move the cursor away from the pin to see you have started a path.

4. Click middle mouse to bring up the popup menu and highlightWidth.

5. When the form expands, click Match Pin Wide.

6. You now see a highlight on the lower right vdd! pin showing thecenterline position.

7. Left click on the vdd! pin near X82 Y7.

8. The path has been completed.

9. Repeat this for the other power and ground pins at the y-coordinatesof Y:21 and Y:35.

Use autoContact to Attach Power Rails to Pdevices


2. Select vdd!

3. Click Apply.

4. Now the only net highlighted is vdd!.

5. Use the Cycle button in the Incomplete Nets form to changehighlilght colors.

a. Select y8.

b. Click on Set Color

The vdd! highlight color becomes white.

The areas where you need to place the contacts are now moreeasily seen. Feel free to choose another color that suits you.



6. Zoom to the top left row to show the first four devices (X:6 Y:39through X:35 Y:40).

7. Select Create Contact.

8. Click on Auto Contact.

9. Click where the metal1 vdd! rail intersects the highlighted contactarrays of the devices such as X:7 Y:35.



10. Notice the 2x1 contact appears and the highlight is removed fromthat area.

Note: The highlights have changed. The flightlines are connectednear corners of the contacts on the net. Notice the color of theflightlines connecting are offset from the metal1 in thecontact and only the source contacts are highlighted. Thisallows you to see which set of contacts are in the net vdd!.The contacts indicated by the arrows are not part of the net.This is more obvious when looking at the other end of thetransistor contacts.

Flightlines appear only at one end of the contact array. These twocontact arrays are not part of vdd! net.



11. Place another contact at X:10 Y:35.

The highlight changes as the incomplete net is connected. Notice now, thecontacts you placed have connected the nodes to vdd!. Since that part of thenet is no longer incomplete, the highlight is removed.

12. Save your design by selecting Design—Save in the layout window.


Note: Do not exit the VXL tool, as we can proceed using the samelibraries for the next lab.

End of Lab


Lab 6-2 Wire Editor Commands


Objective: Use the commands in the Wire Editor utility.

In this lab, you will try the various commands within the Wire Editor.

Opening a Schematic






Enable the Wire Editor

1. In the cellview window select Options—Layout XL.

2. Click on Enable Wire Editing near the left middle of the form.

3. Click OK.

4. Set the routing rules.

5. In the layout window select, Options —Route.

Library Name WireCom

Cell Name encode

View Name layout.we


Wire Editor Commands Lab 6-2

6. Enter the following:

/vcr/rules/routerDigital.rules

7. Click the Rules button.

8. Click OK.


10. Click on Select All.

11. Click OK.

Create Path

1. Zoom in to the upper left hand side of the design, approximately 5.0,25 to 17, 35.You should see four regular poly pins and three widepoly pins.

2. From the Layout window, select Create—Path.

3. The Create Path popup comes up with a width of .35.

4. Move the form off to the side of the VXL window.

5. Click on the leftmost poly pin.

6. Route this path by coming down a short distance, then click once toenter a point of the path.

7. Move to the left until the flight line is lined up with the pin and enterthe next point in the path.

8. Click on the middle mouse button and select Finish Route.

9. Route this wire to the fourth pin in the lower row by putting ahorizontal segment in the middle of the rows of pins. Click on thepin to finish the route.



10. Click on the next pin.

11. In the Create Path popup, click on Match Pin Width and togglebetween Narrow and Wide to see the width of the wire change.

12. Click in the layout window and press Backspace to stop this route.

13. Click on one of the wide pins and toggle between Narrow andWide.

14. Press Backspace again.

Note: You may need to press Backspace a couple of times.

15. In the Create Path form, change the value of the Width back to .25and turn off Match Pin Width.

16. Click on the horizontal wire that you just routed.

17. In the Create Path form, click on the Match Path Width.

18. Notice the width of the wire changes to .10.

19. Click on the middle mouse button and select Finish Route.

20. Click on the first wide pin and start a route.

21. Come down a short distance and enter a point.

22. Click the middle mouse button and select AddVia.

23. Select the M1_PLY1 via on metal1.

24. Move to the right, then add another via to get back to poly.

25. Finish the route.

26. Cancel the Create Path popup.



Edit Stretch

1. Fit the design, then zoom to the area in the upper right atapproximately 55,30 to 75,42.You should see two verticalmetal1wires tied with a horizontal metal2 wire.

2. Select Edit—Stretch.The Edit Stretch popup comes up.

3. With the left mouse button, select the metal2 wire to stretch.

4. Click where you want to place the wire.

Edit—Other—Split

1. Select Edit—Other—Split

2. Select the horizontal metal1 wire.

3. Click on a point above the wire, then on a point below the wire.

4. Move horizontally to the length you want to split, then click.

5. Move above the wire and double click.

6. Click the right mouse button until you are on the segment that youwant to move.

7. Click where you want to place the wire.

Edit—Pull

1. Fit the design then zoom to the area in the upper right.

2. At approximately X 50,15 to 65,35, you should see three verticalpoly wires.

3. Select Edit—Pull.



4. Click to the left of the leftmost wire a little above where it bends tothe right, approximately at 55.7, 30.0.Extend the line downward andclick just below the bend at the lower part of the wire.

5. Click to the right of the set of three wires somewhere midpoint.Notice that the three wires now get “pulled” together.

Edit—Copy Route

1. Zoom in to the whole design, then zoom to the area in the lower leftat approximately 12,8 to 19,14.You should see an upside-down Ushape on the poly layer.

2. Select Edit—Copy Route.

3. Click on the wire.Then click on the pin to the right of the wire. Youwill see the same pattern copied to a like connection.

4. Select Edit—Critic Wire.

5. Zoom in to the whole design, then zoom to the area in the middle atapproximately 19,15 to 35,23.You should see an a jagged wire onthe metal1 layer.

6. Select Edit—Critic Wire.

7. Click on the wire.You will see the unnecessary bends removed .

Verify—Check Route

1. Use bindkey f to fit the window.

2. Select Verify—Check Routes.

3. Click on Same Net.

4. Select Apply.



5. Notice some flashing markers.

6. To see what the errors are select Verify—Markers—Find and clickon Next.

7. To get rid of the flashing markers, select Verify—Markers—Delete all.

Verify—Report

1. To get a Route Status Report, select Verify—Report.

2. While in the General tab, click Apply.

3. The Route Status Report comes up and you can see all the routingsummary information.

4. If you wanted to save the file, click on File—Save As and provide aname.

5. Select File —Close Window.

6. In the Report popup, select the Component Tab and click Apply.

7. The Instance Report comes up with information about the particularcomponent.

8. Select File—Close Window.

9. In the Report popup, select the Net Tab and click Apply.

10. Select a net name and click Apply.

11. The Net Report comes up and you can see the information that isattached to that particular net.

12. Select File—Close Window.



13. Move your cursor to the layout window and press Esc to make thiswindow the active window.

Note: You need to ensure that the layout window is the activewindow (by pressing the Esc key) before each report viewed.Otherwise you will see the CIW message about invalid layoutwindow.

14. In the Report popup, select the Rules Tab and click Apply.

15. You can view all the rules or specify only some of the rules.

16. The Rules Report comes up.You can see all the rules that are appliedto the layout.


18. Select File—Exit on the Command Interpreter Window (CIW) toexit the software.


Wire Editor Options Lab 6-3

Lab 6-3 Wire Editor Options

Objective: Use the commands in the Wire Editor utility.

In this lab, you will follow the instructions to try the various commandswithin the Wire Editor.



cd ~/VXL_50/WE


2. To start the Cadence Design Framework II software, enter:

layoutPlus &

Opening the Layout





Library Name amsPLL

Cell Name DFFRHQS1

View Name wire



2. Enter the Wire Editing mode.

Hint: Enable Wire Editing mode from the Options form.

Note: For this database you do not have to specify a rules file sincerules are part of the technology file.

Interactive Checking

1. Select Create—Path.

2. Start a route from the bottom poly pin of lower left nmos device(approximate location X=3.35, Y=3.67).

3. Proceed routing down until you hit the boundary.

Note: The path cannot go outside the boundary. Also, you cannotmake any invalid connections.

4. While in path mode, click on the middle mouse button and bring upSet up popup menu.

Notice that Interactive Checking button is turned on.This prohibitsthe path to go outside the boundary. Similarly, this will also checkDRC violations.on the fly to make sure that no violations are createdwith other routing objects. The outline is the clearance distancewhich the Wire Editor will try to maintain.

5. Turn Interactive Checking off in the Route Options form and clickApply.

Note: Proceed below by following the similar steps again withInteractive Checking mode off.

6. Start a route from the bottom poly pin of the left most nmos device(approximate location X=3.35, Y=3.67).

7. Proceed routing down until you hit the boundary.

Note: The path can go outside the boundary. There is also no otherchecking if the path shorts objects on other nets.



8. Turn Interactive Checking on in the Route Options form, clickApply, remain in the Path command.

Via Assistance

1. Select Options—Route.

The Route Options Form appears.

2. Change the Via Assistance field to Display from Snap.

3. Turn the Push Routing option off.

4. Start the route from the path connecting the transistor poly gates asin the figure below (approximate coordinates X=3.37 Y=6.63).

5. Try to drop a via from the Poly path you are creating to apre-existing Metal1 path as shown.

The via will not be dropped; however, there will be some concentricrings showing the nearest valid via sites. The rings are shownbecause Via Assistance is set to Display. Click on any ring and thevia is automatically dropped into a valid via site.

If the Via Assistance setting is set to Snap, the via will be addedautomatically to the nearest site as long as there is a valid via sitewithin half the radius of the via.

With Push Routing turned on, the existing wire might be pushed andthe via is dropped.



6. Press the Esc key to get out of the Path command.

Allow Orthogonal Jogs

The Allow Orthogonal Jogs button allows orthogonal jogs.while.creating apath.



2. Click the Defaults button and click Apply.


4. Click a coordinate on the pin Q.

5. Proceed routing this path down till about six units down. (The statusbanner of the layout window should show Dist 6).

There ar orthogonal jogs created.

6. Turn the Allow Orthogonal Jogs option off.

7. Click Apply.

8. Repeat the steps above with this option disabled.

9. Press the Esc key to get out of the Path command.



Route To Cursor



2. Enable the Route To Cursor check box and select Apply.


4. Begin digitizing a path from the top pin of the second pmos devicefrom the left (approximate coordinate of the pin is X=4.15Y=10.45).

5. Continue with the path to the nearest highlighted pmos device pin onthe right (X=6.60 Y=10.45 approximately).

The path will be drawn from the cursor to the pin automatically.

6. Click on the destination pin to complete the connection

7. Enable the options Multiple Layers and Follow Layer Direction inthe Router Options form.

Bus Routing



2. Choose the option Enable Bus Routing within the Route Optionsform.


4. Select the <0> through <7> pins (top left boundary).



5. Move your cursor to the right as the tool begins routing the group ofpaths towards the control wire and its corresponding pin (fourth pinfrom bottom right).

The control wire can be identified by the highlight at the end of thebus.

Note: By default the center wire is the control wire.To cycle thecontrol, press Shift and click right (move the cursor slightlyto see the effect). Repeatedly using this command cycles thecontrol wire between the two outermost wires and thecentermost wire of the set.

6. Click one coordinate and add a M2_M1 via at X= 24.0.

7. Attempt to finish the connection.

The wire spacing between the bus wires is less than the spacing ofthe pins and so the connection can not be completed.

8. Select the Backspace bindkey in the layout window to undo thevias.



10. Click into the Bus tab of the Route Options form.

11. In the Override Spacing For Gathering Bus Wires field, select UseOverride On Next Via and give a value of 0.9 ( 0.9 is the spacingbetween the pins to be connected).



12. While digitizing the path, align the control wire to its correspondingpin and place a via at the location.

13. Click with your middle mouse to get the popup menu.

14. Select Finish Route.




Summary


■ Learned all the commands in the VXL Wire Editor.

■ Learned how to check the Wire Editor routes

■ Learned how to view some reports.

End of Lab


Labs for Module 7

Using the Cadence Chip Assembly Router

Lab 7-1 Translating from Design Framework II to Cadence Chip Assembly Router

Lab 7-1 Translating from Design Framework II toCadence Chip Assembly Router

Objective: Create a rules file that you will use to translate yourplaced design to the Cadence Chip Assembly Router.

Scenario: You have completed placing the devices into the prBoundary. Thenext step is to use the Cadence® Chip Assembly Router (CCAR) to route yourdesign. You must first create a rules file that specifies the layers, vias,boundary, and keepout information that the translator uses. Once youtranslate your design you will be working in the CCAR environment. Whenyou have completed routing the design, you will import the routed designback to Design Framework.



cd ~/VXL_50/PHYSDES



layoutPlus &

Opening a Design

In the CIW, select File—Open, then type the following values in the OpenFile form:


The device1 layout.placed cellview opens for editing.

Library Name deviceLib

Cell Name device1

View Name layout.placed


Translating from Design Framework II to Cadence Chip Assembly Router Lab 7-1

2. Select Tools—Layout XL in the layout window.

The device1 schematic appears.

Viewing the Design

Review the design before translating to CCAR.


How many incomplete nets are there?

There are 14 incomplete nets. This information is displayed at thebottom of the Show Incomplete Nets form.


3. Select Connectivity— Hide Incomplete Nets.

You can now view the components easier.

4. Select Design—Summary.

You may have to scroll the Summary window to the bottom.

How many nmos devices are there?

eight

How many pmos devices are there?

eight

How many resistors are there?

four

How many PNPS devices are there?

two

Once you are familiar with the design you can then translate thedesign.



Creating a New Rules File

Any Design Framework design that you translate to CCAR must have a rulesfile. There is not an existing rules file. You will have to create one yourselfusing the New Rules command.

1. In the layout window select Route—Rules—New Rules.

The New Place and Route Rules form appears.

2. Select deviceLib and click OK.

The Rules Editor form appears.

3. In the Rules Editor form, select File—Save As.

4. Specify the name of this file to be:

deviceLib.rules

Defining the Layers for Translation

You must specify all layers for routing in CCAR. Set layers to either T(translated layers) or Ref (reference layers) or both. Define layers you use forviewing-only in CCAR as reference layers.

You set routing information such as layer direction, widths, and spacings inthis form. You must also specify a Palette Order which establishes theconnectivity of layers through contacts and vias.

1. Select the Add button which follows the word Layer on this form.

The Add Layer form appears.



2. Add the following layers:

Hint: to add multiple layers press the Control key and click on thelayer.

Notice that you do not add all layers to the rules file. You shouldonly add the layers that are used for routing, and layers that you needfor reference, such as spacing rules.

3. Press the OK button on the Add Layer form after selecting the layersfrom the list.

4. Set all layers except for ndiff, pdiff and pwell to T (translate option),as you may have to scroll the form.

You can route on all layers defined with the T option.

5. Set ndiff, pdiff and pwell to Ref.

Reference layers are used in boolean functions to create temporaryinternal layers in the keepout and conductor rule sections.

metal1 drawing

poly drawing

ndiff drawing

pdiff drawing

cont drawing

via drawing

metal2 drawing

pwell drawing



6. Change the Layer Function of each layer.

7. Change the Routing Direction for each translatable layer.

8. Set the Routing Width to 0 on both the ndiff, pdiff, and pwell layers.

You joined two sets of transistors to share drains. The translatorautomatically sets the ndiff, pdiff and pwell to keepout layersbecause you marked them as reference layers.

You must set the routing width of pdiff, ndiff and pwell to 0 (zero) toallow the two devices to remain together as a cluster in CCAR.

metal1 Metal

poly Polysilicon

ndiff N Diffusion

pdiff P Diffusion

cont Cut

via Cut

metal2 Metal

pwell P Well

metal1 orthogonal

poly orthogonal

metal2 orthogonal



9. The palette order represents the mask sequence for the layers. Thehighest metal layer that you are translating to CCAR will have thepalette order number of one. The router and its algorithms expectthis order.

The palette order updates for that layer once you click into the nextfield. Change the palette order to the following:

Saving the Layer Definitions

Once you have defined the layers, you need to save the information to a rulesfile. You will store the rules file in the ~/VXL_50/PHYSDES directory.

1. Click on File— Save.

The rules form saves to the file deviceLib.rules

Defining the Vias to Utilize

You specify which vias to translate for routing vias. Each symbolic via musthave the same layers defined in the Layers section. The symbolic vias(contacts) were previously defined in the library’s technology file.

1. In the deviceLib.rules form, click Vias.

The Via section is displayed.

2. Click the Add button.

Notice that the form updates in the Vias column to show anUNDEFINED via.

metal2 1

via 2

metal1 3

cont 4

poly 5

pdiff 6

ndiff 7

pwell 8



3. Select Browse in the lower right of the form.

A Library Browser form appears.

4. In the Library Browser, select:

deviceLib M1_poly1 symbolic

The M1_POLY1 symbolic cellview is a parameterized contact madeof poly and metal1.

The Via form updates.

5. Select the Add button again.

6. Add the M2_M1 contact to the Via field from the deviceLib library.

The M2_M1 via is a metal1 metal2 parameterized via.

7. Close the Library Browser form by clicking Close.

8. Select File—Save from the rules form to save the via information.

The via information is saved to the current rules file.

Defining Equivalent Layers

You specify equivalent layers for each routing layer. A single layer may usemore than one purpose. Metal1 drawing would be equivalent to metal1 pin.This task combines the layer and its multiple purposes for use in CCAR.

1. Click Equivalent Layers.

The rules form updates to display a list of available layers.

2. Select metal2 and click Add.

The Add Equivalent Layer form appears.

3. In the Add Equivalent layer form, select metal2 (pin) andmetal2 (net).

Note: Use Control and left-click on the various layers.

4. Click OK.



5. Select metal1 and click Add.


6. In the Add Equivalent layer form, select metal1 (pin) andmetal1 (net).

7. Select poly and click Add.


8. In the Add Equivalent layer form, select poly (pin) and poly (net).

9. Select File—Save to save the rules file again.

Defining Boundary Layers

You can define boundary layers for each routing layer. The boundary layeracts as an extent for each routing layer.

1. Click Boundary Layers.

The form shows all the layers you defined in the layers section.

2. Associate the routing layers with their respective boundary layer:

Layer Boundary Layer Spacing

metal2 drawing metal2 by 0

metal1 drawing metal1 by 0

poly drawing poly by 0



3. The rest of the layers are set to prBoundary by and also have aspacing value of 0. When complete, the boundary layers list shouldlike the form below:


Defining Keepouts

In this design, you will ensure poly does not route over ndiff or pdiff layers.You use Keepout operators to remove data from the ndiff and pdiff layers andreplace it with keepout areas on the poly layer.

1. Near the top of the rules window click Keepouts.



yer

awing)

awing)

2. In the lower half of the form, click Add to add each new keepoutrule.

The form displays layers and keepout creation operators. The newrules are displayed in the top half of the form as you create them.

3. Create the following keepout rules by clicking in the conductor ruleGUI at the bottom of the window.

4. Use the scroll bar to click on the layers and operator for the firstconductor. The keepout definition appears in the large pane.

5. Click Add again.

A second definition appears in the large pane.

Layers Operation Layers Keepout La

ndiff (drawing) AND NOT poly (drawing) poly (dr

pdiff (drawing) AND NOT poly (drawing) poly (dr

Click Add first

Click each item to generate your keepout rule



Layer

awing)

awing)

6. Select the layers and operator for the second keepout.

The completed keepout settings appear in the upper-half of the form.There should be two rule settings like the form below.


The keepout information is saved to the current rules file.

Defining Conductors

In this design, you will ensure poly does not route over ndiff or pdiff layers.You use Conductor operators to remove data from the ndiff and pdiff layersand replace it with keepout areas on the poly layer.

1. Near the top of the rules window click Conductors.

2. Click Add.

The form displays layers and conductor creation operators.

3. Create the following conductor rules by clicking in the conductorrule GUI at the bottom of the window.

Layers Operation Layers Conductor

ndiff (drawing) AND poly (drawing) poly (dr

pdiff (drawing) AND poly (drawing) poly (dr



4. Use the scroll bar to click on the layers and operator for the firstconductor. The conductor definition appears in the large pane.

5. Click Add again.

A second definition appears in the large pane.

6. Select the layers and operator for the second conductor.

The completed conductor settings appear in the upper-half of theform. There should be two rule settings like the form below.


You can use the rules file you are creating for translating any designof this technology. You can also store this information in thetechnology file.

Click Add first

Click each item to generate your conductor rule



8. Inspect deviceLib.rules in a UNIX window.

9. Close the form.

Translating the Design

Now you are ready to translate the design to CCAR.

1. From the layout design window, select Route —Export to Router.

The Export to Router form appears.



2. Set your Export to Router form to look like this:



3. Click OK to start the translator.

A dialog box appears asking you if you want to create the directoryccarDevice1.

4. Click OK to create the directory.

Messages concerning translation appear in the CIW.

Ignore the warnings about pins not being created on the ndiff andpdiff layers.

The translator creates a design file for CCAR called device1.dsn.

When the translation is complete, CCAR opens with the converteddesign file. All CCAR log information appears in the UNIX windowwhere you started the layoutPlus session.

5. Leave the design open for the next lab.

End of Lab


Becoming Familiar with the CCAR Environment Lab 7-2

Lab 7-2 Becoming Familiar with the CCAREnvironment

Objective: Explore the CCAR environment and understand themenu and icon structure, zooming and panning, thecolor palette, and the Layers window.

Before routing your design, you will become familiar with the CCARenvironment. You will notice that there are differences between the CCARenvironment and the Design Framework II environment.


Lab 7-2 Becoming Familiar with the CCAR Environment

Viewing the Different Sections of the Window

Look at and understand the different areas of the CCAR window.

1. Click each item on the menu bar to see how the menus areorganized.

2. Continue exploring by clicking some of the submenus from themenu bar.

Many submenus bring up forms in which you enter data that controlsthe router and routing results. Examine some of these forms.



3. Move the cursor over the menu icons.

The name of the menu command appears in a small yellow box.

4. Click each icon on the tool bar and read the command in the modestatus area to understand what they control. The commandtranscript appears in the UNIX log window in which you started thelayoutPlus session. Also, if you hold the cursor over the iconwithout clicking to execute, a popup window appears with the nameof the command.

5. When you click the Measure icon or one of the select or editingicons on the tool bar, notice that the mode status area changes toindicate the current command.

Zooming and Panning

Panning and zooming in CCAR is different from Virtuoso®-XL. In CCARyou use the middle mouse button to pan or zoom. In the Layout Editor youuse the left mouse button to pan or zoom, or use the arrow keys on thekeyboard.



1. Move the pointer to the lower-left corner of the area where you wantto zoom in.

2. Hold down the middle mouse button and drag the cursor to theupper-right corner of the zoom area and then release the middlemouse button.

3. Repeat the previous steps, and zoom in again.

4. To pan, single click with the middle mouse button in the work area.

5. The location under the pointer becomes the new center of thedisplay.

6. Hold down the middle mouse button in one location to pan thedesign dynamically. The dynamic pan feature will pan to thedirection that the cursor is closest to the edge of the CCAR window.

Note: You must hold down the mouse button for at least one secondto activate dynamic panning.

1. Click andhold themiddlemousebutton anddrag a zoom inwindow.

2. Drag tothe upperright ofzoom inwindow



7. Select View—Zoom —All, or you can click on the tool bar iconwhich resembles the world. If you hold your mouse over the icon,the command appears.

The view adjusts to fit the entire design within the work area.

8. Move the pointer to any location in the work area and zoom in.

9. Hold and drag the cursor diagonally downward and release to zoomout dynamically, starting in the upper right corner.

Using the Color Palette

The Color Palette is similar to the Display Resource Editor form. In the ColorPalette form you specify the layer, color chips, and pattern chips.

1. Select View—Color Palette from the CCAR window.

The Color Palette form appears.

2. Drag yourmiddlemouse towardthe lower right

1. Click themiddlemouse herefirst.



2. Select metal1 in the Objects List, and then select a different colorthan what is chosen in the Color Chips array.

The color of the metal1 routes will only change after you clickApply or OK.

3. Click Apply.

In the displayed design, the color of the metal1 routes change.

4. In the Color Chips array, click a blank color chip to define a newcolor, or click the color chip you want to redefine.

5. Click Define Color.

The Define Color form appears.

6. Use the Red, Green, and Blue sliders to mix a new color.

7. Click OK.

The new or redefined color displays in the Color Chips array.

Note: New fillcodes from the Pattern Chips array cannot becreated.

8. Click OK in the Color Palette window.

Using the Layers Window

The Layers window is similar to the Layer Selection Window (LSW) indesign framework. Use the Layers window to turn viewing of routing layersand design objects on and off. You can use the Layers window to set a routinglayer as the current layer when you interactively add or edit routing. You canalso set the horizontal or vertical routing direction for a routing layer.



1. Select View—Layers or click on the Layers Panel icon.

The Layers window appears.

RoutingLayers Pencil denotes

the layers toroute with.

Layers Icon:

LayerVisibilityicons arethe fillcodeboxes

LayerSelectabilityicons

PreferredDirection



2. Click the cont layer visibility button.

What happens in the design window?

The contacts are no longer visible. If you don’t see this the first time,toggle the visibility button on and off again.

3. Make cont visible.

4. Click the Guides visibility button.

What do Guides correspond to in VXL?

Guides are the netlist connectivity flightlines for unconnected nets.

5. Make Guides visible.

6. When you are done viewing the Layers window, click Close.

You will use the Layers window to set the routing direction, and theprimary layer for routing.

End of Lab


Routing Your Design Lab 7-3

Lab 7-3 Routing Your Design

Objective: Interactively and automatically route your design

The next step is to route your design. First you will route the critical netsinteractively, then you will autoroute the rest of the design.

Aligning Devices

You need to align the four large CMOS devices in the center of the design.

1. With the middle mouse button zoom into the middle of the design.

2. In the Tool bar click on the Place icon.

3. Click with the right mouse button to bring up the pull-down menu.

4. Select Align Mode.

5. Move the cursor over the edges of the transistors. Notice how theedges highlight. You can select any edge of a device shape foralignment.

6. Click on the edge of the first transistor, and then click on the edge ofthe second transistor to align it’s edge to the first transistor.



7. Repeat the step for transistors 3 and 4, but click on the top edge ofthe transistors.

Are the transistors aligned?

Yes they are now aligned.

8. Click with the right mouse button and select Exit to Move CompMode to cancel out of the Align Mode.

Pushing Components

The devices at the bottom of the design need to be moved over. Use the PushComponent command to push the devices into place.

1. Select View—Zoom —All.

2. Click with the right mouse button and select Push Comp Modefrom the pull down menu.

3. Select the device as shown below.



4. Move the device over to the left about ten microns. You don’t needto be exact.

Did any devices move with the device that you had selected?

Yes, the devices to the left of the selected devices moved also.

Moving a Single Component

You need to move the large CMOS device to the left of the design. Use theMove Comp command to move the CMOS device into place. With MPS yousee the move component changes reflected automatically in your VXL layoutwindow.

1. Click with the right mouse button and select Move Comp Modefrom the pull down menu.

2. Select a MOS device in the top of the layout similar to the examplebelow:

3. Move the device into the empty area.

How is the Move Comp Mode similar to moving in Virtuoso-XL?

In Virtuoso-XL as well as CCAR you can select an object and moveit without invoking another command. Spacing is maintained.



Clustering the Aligned Devices

Now that the devices are placed where you want them, you can clusterdevices together, so that if you do move them in the future, they will movetogether.

1. Select View—Zoom —All.

2. Ensure that the Place icon is clicked within the Tool bar, as this doesaffect which popup menus are available.

3. Click with the right mouse button and select Select Comp Modefrom the pull down menu.



4. Select the two devices as shown in the following illustration.

You can turn on the instance labels by clicking in the Layers Panelon the fillcode box next to Labels.

5. Select Define—Component Cluster—Selected.

6. Change the option to Super and click OK.

7. Click the right mouse button and select UnSelect All Objects.

8. Click with the right mouse button and select Move Comp Mode.from the pull down menu.

9. Click on one of the devices to start the move.

Do the devices move together?

Yes, because they have been clustered together.

Select these devices



Creating Pins

The I/O pins IN1, IN2, and OUT were created when you created the newlayout view. The vdd! and gnd! pins were not created because the symbolsfor these signals in the schematic were set to be ignored during layoutcreation.

There is a set size for vdd! and gnd! in this library. You will create the twopins first.

1. Switch to Route mode by clicking the Route Icon in the Tool Bar.

2. Set metal1 as the primary layer by clicking on the layer name. Youcan also accomplish this by clicking on the Pencil icon near the wordmetal1. The pencil becomes bold in comparison to the other layer’spencils.

3. Using your right mouse button, select the pop-up menuPolygon Editing Menu.

4. From the pop-up select Edit Polygon Mode.



5. Click and drag the left mouse button to draw the supply rails. Clickright and choose Finish Polygon to end the polygon. You will addconnectivity to these supply rails later in this lab.

Note: If you wish to delete a wiring polygon that you created, clickright and select:Select—Wiring Polygons—Sel Wiring Polygon Mode andchoose the polygons you wish to delete. Then select the menupulldown command Edit—Delete WiringPolygons—Selected.

Editing Wiring Polygons

Experiment with these editing tools with wiring polygons. The CCAR tooland its commands differ between wiring polygons and wires.

1. To resize a wiring polygon (versus a wire), you can stretch it byselecting the Move icon, then place your cursor on the edge youwant to stretch. Drag the edge with the left mouse button to stretch it.

2. To stretch an edge of an object while in the Move object mode:



a. Select the edge of the polygon.

The cursor changes to a letter O when you are right on the edgeof the polygon.

b. To cancel, click right, and choose Cancel if you did not selectwhat you wished.

3. To move the entire boundary while in the Move object mode:

a. Select the polygon with the left mouse button.

The cursor changes to a cross.

b. To cancel, click right, and choose Cancel if you did not selectwhat you wished.

4. To cut areas out of a wiring polygon:

a. Click right and select Cut Polygon Mode.

b. Stretch a rectangle within the polygon.

The area removed can be inside the polygon border or it canextend from an edge of the polygon.

5. To delete a wiring polygon, click right and selectDelete—Wiring Polygon Mode, then click left on the polygon youwant to delete.



Adding Connectivity to the Pins

The two pins you just created are wiring polygons that have no signal nameintelligence. Use the Change Net Connectivity Mode command to add thisnet name.

1. Click right in the CCAR window to bring up the Polygon Editingmenu.

If the popup menu is not titled Polygon Editing Menu choose thatoption in the popup.

2. Select Change Net Connectivity Mode from the popup menu.

The Change Connectivity Setup form appears.

3. In the Nets field select:

gnd!

4. Click Apply.



5. Click on the new pin that you created at the bottom of the design.

A guide appears that connects to the new pin and assigns it the netname gnd!.

6. Within the Change Connectivity Setup form in the Nets field select:

vdd!

7. Click OK.

8. Click on the new pin which you created at the top of the design.

A guide appears and connects to the new pin and assigns it the netname vdd!.

Redefining the Boundary

Before you start to route the design, you can redefine the boundary to besmaller than the existing boundary.



1. From the menu pulldown select Define—Route Boundary—DrawMode.

2. Create a new boundary as shown below by clicking and draggingwith the left mouse button. After clicking three or more coordinates,you can finish the boundary by clicking a right mouse button andselect Define Polygon as Boundary.

Make sure you enclose all of the design objects:

An Add Polygon As Route Boundary window opens.

3. Turn All Signal Layers on.

4. Click OK.

Setting Timing Rules for a Class

1. Select Define—Class—Define/Forget by List



2. Click on Create Class.

3. Click on OK in the Create Class form to accept the name of class1.

4. In the Nets list, click on net52 and net68.

The nets move to the Nets in Class category.

5. Click on Close in that window.

6. From the menu bar, select Rules—Class—Timing.

The Class Timing Rules form appears.

7. Set the Pick Class button to be class1.

8. Within the Length tab, click on Match Net.

9. Set Length Tolerance:

.5

10. The form should look as follows:



e .5))

11. Click OK in the form.

The rule is reported in the UNIX window:

12. To review the rules you just created, select Report—Rules—Specify.

The Report Routing Rules form opens.

13. Select Class Rules and click OK.

The report window appears.

14. Close the report when you’re finished.

Removing Interlayer Rules

Some interlayer rules in the DF-based libraries are not appropriate for CCAR.These steps show how to remove those rules.

1. Select Rules—IC—Interlayer—By Layer Pair.

The Clearance Rule form appears.

2. For Pick Layer select poly.

3. Select cont for the other Pick Layer.

4. Set the All field:

-1

This turns off the established dimensions set in the form. -1 meansthat this rule “does not apply”.

circuit class class1 (match_net_length on (toleranc



5. Click Apply if your form has poly and cont selected as the layers.Also make sure that -1 is set for the all values in this form:

6. Cancel the Interlayer Clearance Rules form.

Note: These rules are kept in device1.str of the device1 directory.Another way to remove the rules is to delete them from thatfile before opening the design.

Running the Router

In this section you start the autorouter.



1. In the CCAR command entry window, enter:

route 25 ; clean 2

This runs the router for 25 passes and then follows by invoking theclean algorithm for two passes to clean up any unnecessary bends ornotches. The semicolon gives the user the ability to stack commandsinto the command entry window.

Note: You can also enter these commands into a do file and executethat file.

2. Check the final route status by selecting Report—Route Status orclick the icon on the left of your CCAR window:

3. After viewing the report, click Close.

4. Depending on how you setup your design’s route boundary andother rules, you may not get the design routed with a 100%completion. We will examine different items about the routed designin the next few sections.

Using Split View to Examine the Connections

1. To view the different layers used for routing selectView—Split View.

2. Change the number of views to 3 and click Apply.

Note: You can not zoom your viewing area when in Split Viewmode.

3. When you are finished viewing the routing on the different routinglayers, change the number of views back to 1 and click OK.

Examining the Tolerance Rule Routing

In this section you inspect the nets for conformance to the tolerance you set.



1. Select the two nets that you set the length tolerance rule on with theSelect—Nets—By List menu command. Use the Control key toselect multiple items in the list. The nets to select are:

net52

net68

Note: Accordion routing that aids in matching wire lengths.

2. Click Close on the [Un]Select Nets form.

3. Check the tolerance value by selecting Report—Specify.

4. Click on Length.

Your numbers may vary from the chart above, but was the tolerancemet for the Routed Length in your design?

5. Click on Close at the bottom of the Report form when you’re done.

6. Deselect the nets with the menu pulldown commandSelect—UnSelect All Routing Objects.

Net Name Manhattan Routed Len-------- --------- ----------net52 34.6000 74.8000net68 73.2000 75.3000



Wire Redundancy

After autorouting you may want to do further interactive editing on theexisting routing paths. You may need to clear out areas of congestion in orderto complete more connections or you may need to resolve length violationsby changing connection lengths.

To change an existing path you don’t necessarily have to use the deletefunction. Instead you add the new path into existing connections. When youadd back into the connection at a new location, CCAR recognizes that youhave created a redundant wire and automatically deletes the redundancy.

1. Click the Edit Route icon from the tool bar.

2. Find a path that you would like to change and begin by adding aT-junction into the existing connection as shown.



3. Continue adding the new path until you join the new path back intothe original path:

When you join the new path into the original path, CCAR recognizesthat you have formed a redundant wire. The older portion of theredundant wire is automatically deleted, leaving the new wire asshown.

4. Try making a few more path changes. Add vias in the new path. Aslong as you connect back into the original path on the appropriatelayer, CCAR will recognize the redundant wire and its related vias.

Protecting Nets

After interactively editing critical connections you can protect them frombeing moved by future autorouting routines. By protecting wires or nets youprevent them from deletion and any subsequent movement.



1. Select Edit—[Un]Protect—Wires By Net.

2. Click on By List.

3. Click on the net name that you want to protect.

Notice there are buttons near the bottom of the list window that letyou choose between Protect, Soft Protect, and UnProtect.

■ Protect prevents any movement or deletion of the wire. It doespermit other wires to be connected to it either interactively orthrough the autorouter.

■ Soft Protect prevents the router from replacing wires but doesallow wire movement.

4. Choose Protect or Soft Protect.

5. Click OK or Apply if you have more nets to protect.

A white highlight is displayed on the protected net.

6. Run the router again.

Notice the wires are not moved or replaced.

7. In the CCAR command entry window, enter:

clean 2

Manually Creating Keepouts

If you want to block routing over devices in the design you can add additionalkeepouts.

For example, the resistor devices are ndiff resistors. If they do not block poly,another MOS device will be formed. You can manually create keepouts overany device. Add keepouts with the following steps, then reroute to see thedifferences.



1. Zoom the view in on device |Q1.

You can turn on the instance labels by clicking in the Layers Panelon the fillcode box next to Labels.

2. To create a keepout, select Define—Keepout—Draw Mode.

3. Click and drag with the left-mouse button to stretch a rectangle thesame size as the device.

Note: When creating keepouts you can create rectangles by using adraw-through operation with the mouse. If polygons arerequired, you can click each vertices to draw the shape byindividual segments.

4. To complete your Keepout Boundary, click your right mouse button,and from the popup menu select Define Polygon as Keepout. Thetool will complete the boundary automatically for you when youexecute this command.

The Add Polygon as Keepout form appears.



5. Select All Signal Layers except metal1, then accept the other fieldsand click OK.

6. Create an all-layer keepout for the other PNP device, |Q0.

7. Create a poly keepout over the ndiff layer of each resistor device.

Routing with Keepouts

As you add constraints to the design, like rules or keepouts, you restrict therouter. The router run time will be longer and nets may not find a path if thefloorplan is too tight. Try rerouting the design with the keepouts you justcreated.

1. Select Edit—Delete—Wires—All Wires to remove the previousrouting.

2. Click Yes to confirm.

3. In the CCAR command entry window enter:

route 7; clean 2

If the router seems hampered by the keepouts, you may need toadjust the floorplan to make room for routing.

Deleting Keepouts

You may need to delete keepouts. This is how they are removed:

1. Select Define—Keepout—Forget.

The Forget Keepout form appears.

2. Click on the keepouts you want to remove (forget).

3. Click OK.

The keepouts disappear.



Adding Angles to the Routing

The miter command changes 90 degree corners to 45 degree chamferedcorners.

Before mitering wires, turn on same_net_checking. This allows the mitercommand to include notch checks when building mitered corners.

1. Enter this in the Command field:

set same_net_checking on

Note: You will also use the Rules menu to set this checking option.

2. In the CCAR command entry window enter:

miter

All wires now enter and exit corners at 45 degree angles.

3. Enter this in the Command field:

set same_net_checking off

Perform Same Net Checking

Same Net Checking finds notch errors. The router runs slower with thisturned on. For this reason you turn Same Net Checking on and check rulesonly after routing is complete.

1. Select Rules—Check Rules—Setup and Check.

The Setup/Check Rules form appears.

2. Turn on Same Net and click Setup and Check.

3. Click on Close in the Setup/Check Rules form.

4. Select Rules—Check Rules—Route.

The rule checking takes a moment and updates information to theUNIX window.

5. From the menu pulldown select View—Visit.

The Visit form appears. Move the form to the side of your display.



6. Within the Conflicts tab, select Clearance.

The Visit window zooms you to the first of several notch conflicts.Cycle through the conflicts. You can use the Zoom Scale slide barto adjust the viewing visit area.

If the Clearance button is already selected and the Next andPrevious buttons are not available, turn the Clearance button offthen on.

7. Click the Next button to view the next clearance conflict.

8. You can turn off the errors by clicking on the visibility icon in theLayers Panel as shown:

Using Critic and Miter Setbacks

To remove the notch conflicts you use critic and miter.

1. Select Autoroute—Post Route—Critic.

2. In the Visit form, click the Clearance button off then back on aftercritic is done.

There are now less conflicts.

3. Select Autoroute—Post Route—[Un]Miter Corners.

The [Un]Miter Corners form appears. Move the form to the side ofthe display so you can see the results of the command.

4. Select Use layers and pick a layer which creates a notch violation.Use the Control key to select more than one.

5. Select UnMiter and click Apply.

The corners become orthogonal.



6. Select Slant and set Slant Setback to 1.5, then click OK.

The wire returns to a miter and will not create any violations.

You have completed the routing of your design.

Closing the CCAR Window

In preparation for returning the updated design to Design Framework youmust save the session file. The session file is used by the translator.

1. To save the design and quit, select File—Write—Session.

2. Click OK to write the session file. If one exists to overwrite, selectYes.

3. Select File—Quit to close your CCAR session.

Translating Back to Design Framework II

You will translate device1.ses session file to device1 layout.new cellview.

Important

Your session file from CCAR should already be translated backautomatically via the MPS utility. Redraw your layout window of the device1layout, as you should see your work from CCAR updated in this window. Ifthis is true, then you can choose Design—Save of your layout window andskip the remaining steps of this lab.

If your design is not translated back to your layout window automatically,then follow the remaining few steps.

1. In the VXL layout window, select Route—Import from Router.

The Import from Router form appears.

2. Set the View field to: layout.new

3. Verify the Import Router File field is:

./ccarDevice1/device1.ses



4. Click on Use Pin Purpose.

5. Click OK in the Import from Router form.

When the messages in the CIW indicate the translation hasSuccessfully Completed you can open the cellview.

6. Open the cellview device1 layout.new and view the design.

If you wish to complete this design, you would add the pwell, welltaps, and substrate taps using Virtuoso-XL commands.

7. To save the design select Design—Save.

8. Close the layout window by selecting Window—Close.

9. You do not need to exit your session. Leave your CIW active for thenext lab.

Summary for the Module

In these labs you:

■ Created a device-level design

■ Translated the design to CCAR

■ Used a design flow to create a device-level design

■ Translated back to Design Framework II

End of Lab


Labs for Module 8

Analyzing and Updating Data

Lab 8-1 Engineering Change Order


Objective: Given a new schematic, update the layout to matchthe schematic.

Opening a Cellview



The latch layout.routed cellview opens for editing. This design isplaced and routed.

Press the bindkey Shift-f to view all levels of hierarchy andControl-f to view just zero-level data.

Invoking the Virtuoso-XL Setup

1. In the layout view, select Tools—Layout XL

The schematic window opens and the windows are arranged in theVirtuoso®-XL setup.

Changing the Schematic

Scenario: Another engineer in your design team has created a new schematicfor this design in a new cell and has passed the new schematic to you.

In the layout view, select Connectivity—Update—Source, then enter thefollowing values in the form:

Library Name overview

Cell Name latch

View Name layout.routed

Library overview

Cell latch.new

View schematic


Engineering Change Order Lab 8-1

1. Click OK in the Define Connectivity Reference form.

The latch.new schematic cellview opens for editing.

Starting Virtuoso-XL Again

1. In the layout view, select Tools—Layout.

2. Select Tools—Layout XL.

Toggling between Tools—Layout and Tools—Layout XL turnsVirtuoso® XL off and on again, triggering the extractor which willhave the design check against the source schematic.


Verifying the Design

The Check Against Source command will show you any differencesbetween the schematic and layout.

1. Select Connectivity—Check—Against Source.

A Virtuoso XL Info window opens with information on thedifferences between the layout and the new schematic.

Notice that there are two instances that are missing, and that some ofthe nets are hooked up incorrectly.

2. Look at the layout window for any flightlines or any markers.

Markers indicate the location of devices in the layout with nocorresponding devices in the schematic.

3. Close the Virtuoso XL Info window.

Updating Components and Nets

Update the layout from the schematic. Any new devices will be placed belowthe prBoundary.

1. Select Connectivity—Update—Components and Nets.



2. Click OK in the Layout Generation form.

Notice that two devices are added below the prBoundary. You willhave to zoom out in order to view the second device.

Updating Parameters

Update the layout parameters from the schematic. Since this layout designcontains parameterized cells, the devices will change in size if the width orlength has been changed in the schematic.

1. Select Connectivity—Update—Layout Parameters.

2. Press the F3 key to open the Update Layout Device List form.

3. In the Update Layout Device List form, drag your cursor over thedevice names to select all devices.

4. Scroll down until you can see the rest of the devices that have notbeen selected.

5. Press Control and drag your cursor over the remainingunhighlighted devices until they are all selected.

6. Click on Apply in the Update Layout Device List form.

A Virtuoso XL Info window appears with information about whichdevices have been updated. Notice that the ‘w’ on figure |N10 hasbeen updated to 5. Also the width on P11 has been changed.

7. Select Cancel in the Update Layout Device List form.


9. To find the devices select Connectivity—XL Probe and in theschematic window click on device N10.

Can you find the corresponding device in the layout?

10. To find the corresponding device in the layout, change the Showoption to Devices in the Probe Options form.



11. Probe the N10 and P11 devices.

Notice that the connection for the N10 device is broken because thedevice parameters have been changed to a smaller value.

Deleting the Extra Devices

Two devices have markers placed on them when you invoked the CheckAgainst Source command. These devices have no corresponding symbols inthe schematic and need to be deleted.

1. Two devices have large markers that indicate these devices areextra. Delete these two devices.

Notice that the markers are removed automatically.

Deleting Wiring

Before you place the new devices into the prBoundary, you need to delete allwiring, except for the vdd! and gnd! wiring.

1. In the LSW turn off Inst and Pin.

2. Select all of the wiring inside of the design, except for the wiring tovdd! and gnd!.

3. Delete the wiring.

4. In the LSW turn back on Inst.

5. Select all of the contact instances and delete them.

You should only have wiring to gnd! and vdd!.

6. Turn Pin back on in the LSW.



Placing the New Devices

1. Move the two new devices from below the prBoundary into thedesign area. The design will look something like the following:


3. Select Select All.

You should have ten incomplete nets in the design.


5. Select Design—Save.



Translating the Design

Translate the placed design to CCAR to route the design.

1. Select Route—Export to Router.

2. Scroll down to the bottom of the form and select Load Defaults.

3. In the Load Defaults form select eco.file and click OK.

4. Click OK to start the translation.

The translation succeeds and the CCAR tool starts.

Routing the Design

1. In the CCAR window command text field, type:

route 25

Remember to press the Return key following this command or elsenothing will happen.

2. Select File—Quit.

3. In the Save and Quit form save the Session File to latch.ses.

4. Select Save and Quit.

5. Select Yes in the warning box.

The routing does not have to be perfect for this example.

Translating to DFII

The MPS utility should have automatically translated your data back to yourlayout window. (You can check by redrawing your layout window.) If not,follow the few steps here to import your design; otherwise, go on to Verifyingthe Design.

1. In the layout window select Route— Import from Router.




3. Select ecoback.file and click OK.

4. Click OK to start the translation.

The design is translated successfully.

Verifying the Design

Check to see that there are no routing errors in your design.

1. Select Connectivity—Check—Shorts and Opens.

A Virtuoso XL Info window opens. There are no shorts, overlaps, orincomplete nets reported.


3. Close the layout window and schematic window withWindow—Close for each window.

4. Leave the Command Interpreter Window (CIW) open.



Steps for Updating the Design

Review the basic steps for updating a design:

■ Use Connectivity—Update—Components and Nets to updatethe layout with the new schematic connectivity.

■ Use Connectivity—Update—Layout Parameters to update thelayout with the new schematic parameters.

■ Delete any extra devices.

■ Move new devices into place.

■ Delete wiring shapes associated with shorts.

■ Use Route—Export to Router to translate to the router.

Use the cmosecho.rules file.

■ Route the design using the CCAR tool.

■ Within the CCAR tool, save your latest routing data andplacement information with File —Write—Session.

■ Translate the design back to design framework (VXL) by usingthe Route—Import from Router pulldown command fromwithin the VXL layout window.

■ Verify that the design is complete and correct.

Once you update the design, go to the step on examining designinformation at the end of the lab.

Summary

■ You updated a design after receiving changes to the schematic.

End of Lab


Labs for Module 9

Working with Hierarchical Designs andVariables

Lab 9-1 Lay Out a Hierarchical CMOS Design


Objective: Given a hierarchical schematic, create and route thelayout.

This lab uses a typical CMOS circuit for the design example.

Opening a Cellview



The muxes schematic cellview opens for editing. This is ahierarchical schematic.

Library Name hierarchy

Cell Name muxes

View Name schematic


Lay Out a Hierarchical CMOS Design Lab 9-1

Before going on to use Virtuoso®-XL to generate the layout for this design,examine the design and answer the following questions:

Are there any iterated instances in this design?

The inverter is the only iterated instance. Notice the instancename I<0:1>.

What do you expect to see in the layout for these iterated instances?

Two nmos and two pmos devices will be placed in the designinstead of one nmos and one pmos device.

Were NLP expressions used to specify any parameters? Where?

The NLP expressions are added in the schematic. Descend downinto one of the instances using theDesign—Hierarchy—Descend Edit command. Notice that thelength l = .6 and width w = 3.

Will the generated layout use all nmos and pmos cells or will therebe any other cells placed?

Notice that instance I11 in the schematic uses the cellviewcmos.layout layout. This is specified through the lxStopList. Thiscellview is a completed nand design complete with interconnect.

Invoking the Virtuoso-XL Setup

1. In the schematic view, select Tools—Design Synthesis—LayoutXL.

2. Select Open Existing and click OK.

3. Click OK in the Open File form to open the layout.

4. Select Design—Gen from Source.

5. Make sure the IO Pin Layer is set to poly1 pin for all pins.

You might want to turn on pin labels also.


Does the generated layout have the devices you expected based onyour examination of the schematic?



Building the Layout

1. Using all of the Virtuoso-XL commands, complete this design.

2. Translate the design to the CCAR tool and route the design. Createa new rules file or use the same rules file from lab 6-1.

3. Run DRC checks to verify there are no design rule violations.

4. When you have finished, report your final design size to theinstructor.

5. You might want to experiment with changing the schematic andupdating the layout to reflect those changes.

Summary

■ You created a layout for a hierarchical design.

End of Lab


Lay Out a Hierarchical CMOS Design Lab 9-1


Labs for Module 10

Virtuoso Custom Placer

Lab 10-1 Defining Component Types


Objective: To define component types for your library to usewith Virtuoso Custom Placer.

You define component types for two reasons:

■ To identify PMOS and NMOS cells to enable chaining andfolding

■ To identify component types for each row. When you define rowsusing the Placement Style form, component types are part of eachrow definition.


1. Make sure all previous VXL sessions are closed.

2. In a UNIX window, change into the lab directory:

cd ~/VXL_50/VCP/VCPref


Starting Virtuoso Layout Editor


1. To start the Cadence® Design Framework II software, enter:

layoutPlus &


Defining Component Types Lab 10-1

Opening a Schematic

In the CIW, select File—Open, then enter the following values in the OpenDesign form:




The Virtuoso XL Startup Option form appears. This form lets youopen an existing cellview or create a new cellview.




3. Ensure the following values are set in the Create New File form:

4. Click OK in the Create New File form.

The layout window is opened and the windows are rearranged sothat you can see the schematic, layout, CIW and LSW all at once.

5. If the warning appears asking to overwrite the cell, select Yes in theoverwrite form.

The schematic window resizes and the layout view also opens.

Library Name 50TRO

Cell Name encode

View Name schematic

Library Name 50TRO

Cell Name encode

View Name layout




The next step is to place design elements, such as instances and pins, from theschematic into the layout window.



2. Review the default settings


All of the components which make up this design have beengenerated. These components will be classified with ComponentTypes in the following steps. Typically defining Component Typesis performed by the CAD engineer as a library function.

Defining Component Types

You define component types to direct the placement of the layout devices.

1. Select the menu window command Connectivity—ShowIncomplete Nets.

2. Now that we see the connectivity, select Cancel in the ShowIncomplete Nets form.



3. In the layout window select Design—Component Types.

The Edit Component Types form opens:

4. Make sure Scope is set to Lib, so the changes are reflected in theentire library.

5. In the Type section notice that two component types have alreadybeen defined for you by toggling the cyclic field: fillc and standcell.Enter in the field below Type:

myPMOS



6. Click Add just to the right of the Type field.

Note: This is a user-defined name. Theoretically you can use anyname you want for Type. Later you use this Component Typeas part of your row definition. You name it myPMOS for thisexercise. You will choose which component type belongs ineach row that you define using the Placement Style form(User-Defined mode) later in this lab.

7. At the bottom of this form, set Component Class to PMOS.

Notice that the Width Par Name field above becomes editable.

The Component Class field has seven predefined choices and thenames cannot be altered. The Component Class information is usedfor folding, chaining and placement.

The Estimator in Component Assisted mode looks at thisinformation when determining the percent utilization.

You can have multiple Component Types belong to the sameComponent Class. For example, you can have component types suchas: myPMOS, bigPMOS, smallPMOS, all belong to the PMOScomponent class.

8. Under Cells in Design, select 50TRO spcpmos, then click the >>>button.

This places 50TRO spcpmos in the Components in Type field. Thisis the only entry you should see in this field.

9. Under Edit Parameters for Width Par Name enter w.

10. Under Edit Parameters, toggle to Fold Threshold and enter 8.

This information is used for device folding.

11. Under Edit Parameters, toggle to Active Layer and enter:

pdiff drawing

Note: These are the only parameters that are required to be set inthis section. The rest of the parameters such as,lxSourceName, lxDrainName, are optional.



12. Click Apply in the Edit Component Types form.

You have defined all the pmos devices in the design as a myPMOScomponent type. You will now define all the nmos devices asmyNMOS component types.

13. In the Type section, enter myNMOS, then click Add.

14. Under Cells in Design, select 50TRO spcnmos, then click the >>>button.

50TRO spcnmos is now in the Components in Type field.

15. Under Edit Parameters, set the following:

Note: These are the only parameters that are required to be set inthis section. The rest of the parameters such aslxSourceName, lxDrainName, are optional.

16. Set Component Class to NMOS.

17. Click OK in the Edit Component Types form.

You have now defined all the nmos devices as a myNMOScomponent type.

Generating the New Design

1. In the layout window, select Design—Gen from Source.

2. This time turn on the Transistor Chaining and Transistor Foldingfields (at the top of the form).

Width Par Name w

Fold Threshold 6

Active Layer ndiff drawing



3. Click OK in the Layout Generation Options form (use the defaultsetting for the rest of the fields).

Have all the components been successfully folded, in accordancewith the lxMaxWidth values you set in your Component Typedefinitions, and chained?

If so, then you have correctly defined your Component Types andyour devices should be ready for the placer as well.

4. Select Design—Save from the menu window.

Important

It is essential at this point that you have correctly defined the ComponentTypes. If you have any uncertainty about this please contact the instructorbefore continuing the lab.


6. Do not close your Cadence session.

End of Lab


Labs for Module 11

Pin Placement

Lab 11-1 Pin Placement


Objective: To generate prBoundary and pins

In this lab you will generate a prBoundary and pins which you will use in adesign using customized settings for the Layout Generation Options form.

Continue within the same Cadence® session, as you don’t have to startanother one at this time.

Opening a Design



This form controls what data is to be created — for example, pins,instances, or boundary information. It also defines the pin layer, sizeand the number of pins per net, aspect ratio, and percent ofutilization for routing. You can also set the default pin layerinformation if needed.

2. Next to Defaults in the I/O Pins section of the form, set theLayer/Master value to metal3.

3. Click on Apply just above the word Defaults on the left.

This sets all the nets to have a single pin created on metal3.

4. Change the vdd! and gnd! nets Layer/Master value to metal2.

In the I/O Pins section above the list of net names and theirproperties is an entry field titled Select.

5. Enter vdd! in the Select field

Notice the net is highlighted in the Net Name Properties field. Thenet properties are now available for editing just below the Updatebutton.

6. Change the Layer/Master value to metal2 in the update area.

7. Set Height to 1.0 and Num to 2.


Pin Placement Lab 11-1

8. Click on Update.

9. Notice the vdd! properties change in the highlighted properties listarea.

10. Set the same properties for gnd!

Note: You have the option of saving this information to a templatefile so you can reload at a later time if you so desire. You arenow going to load a template file that was previously created.

11. At the bottom of the form click on Load Template File for LayoutGeneration.

The template entry field is enabled.

12. Browse and choose ./templates/encode.lxt.

13. Click Load.

The form shows the settings from the template file.

This creates four metal2 pins on vdd! and two metal2 pins on gnd!.These pins have a height of one micron. The rest of the pins are onmetal1 and have a height of .35 micron. Also note that prBoundaryheight and width are set.

14. Make sure Transistor Chaining and Folding are on.


16. In the layout window select Connectivity—Show IncompleteNets.

17. Click the Select All button and click OK.

All the incomplete nets highlight.



Using the Pin Placer

1. In layout window select Place—Pin Placement.

The Pin Placement form appears.

Review the options of the Pin Placement form.

Important

Please follow the steps below closely as the pin positions are important laterin the lab when you use CCAR to route the design.

2. Click on the vdd! pin in the Pin Name column to select it.



3. Change Edge to Left, set Order to 0, set Location to Floating, andclick Apply.

4. Click on the gnd! pin in the Pin Name column to select it.


6. Click on the vdd!.2 pin in the Pin Name column to select it.


8. Click on the gnd! pin in the Pin Name column to select it.

9. Click on HRAIL button to create a rail.

10. Create HRail for vdd! and vdd!.2

11. Select AO, A1 and A2 in the Pin Name column.

12. Change Edge to Top, set Order to 0, set Pin Pitch to 10.0 microns,and click Apply.

Note: You must have ordered the pins to set the pitch.

13. Select S1 through S6 in Pin Names column.

14. Change Edge to Bottom, set Order to 0, set Pin Pitch to 8.00microns, and click Apply.

15. In the layout window select Connectivity—Hide Incomplete Nets.

Highlighting is removed from all the incomplete nets.

It is a good idea to save the design at this point.

Do not close the design, just save it. You can look at thelayout.pins.bck view to check your design.

16. From the menu window select Design—Save.



17. Do not close your layout windows or your Cadence session.

Summary


■ Generated your prBoundary for your circuit

■ Placed your pins using the pin placer form

End of Lab


Labs for Module 12

Placement Planning and AutoPlacer

Lab 12-1 Placement Planning and AutoPlacer


Objective: User-Defined Mode

Continue the same Cadence® session you used in the last lab.

Defining the Rows

1. In the layout window select Place—Partitioning.

This will open the Partitioning form.

2. In the layout window create a rectangle on the soft-fence drawinglayer. Draw this as close to the prBoundary as possible.

The placer requires the partition to be on soft-fence drawing layer.

3. In the Partitioning form enter myPart under Choose or type apartition name.

4. Click on Link.

5. Click on the Create Partition button.

This will enable the Attach Shape and Delete Partition buttons.


Placement Planning and AutoPlacer Lab 12-1

6. In the layout select the soft-fence shape.

7. In the Partitioning form, change Display By to Target Master.

8. Select both of the displayed components.

9. Change the Target Partition entry in the bottom of the form tomyPart and click on Move.

10. Click Close in the Partitioning form.



MOS Device Level Placement

1. In the layout window select Place—Placement Planning.



2. In Style field of Placement Planning form, change Assisted CMOSto Manual User-Defined.

Note: Assisted CMOS is the automated approach to defining rows(what-if analysis) and Manual User-Defined is the manualapproach. We will first show you a manual way to define therows in the design. Once we define these rows, we will deletethem and then show you a faster semi-automatic way todefine your rows.

3. In the LSW click on Row.

This is the layer expected to define the rows.

4. Select Draw in the Placement Planning form to initialize the firstrow definition.

Notice the CIW prompt Point at the first corner of the regionsrectangle.

5. In the CIW enter 1:1 then press Return.

6. In the CIW enter 89.0:9.0 then press Return.

The first row area has been defined.

You could have also entered the area by clicking the mouse to createthe rectangle.

7. Enter 5 for spacing between rows.

8. Enter 4 for Number of Rows to Create.

9. Click Create New near the bottom of the form.

After clicking on Create New notice that information about all therows we created is displayed. You can also create rows by drawingthem in the layout window and using Choose from Layout to addthe row definition.

10. Click the Types tab to specify the Row Type properties.

11. Click on row1 in the bottom of the form to select it.



12. Change Allowed Orientation to only R0 and R180.

13. Click Edit on Component Types.

This will open the Choose Component Types form.

14. Select myPMOS.

15. Click OK in the Choose Component Types form.

16. Click on Create.

Note: Notice that the Type Field gets filled with a type definition.

17. Click Update to add this information to the row definition.

18. Similarly, update the information for row 4 for myPMOS.

19. Similarly, update the information for row 2 and row 3 for myNMOS.

Now four rows have been generated with a spacing of 5.00. Thiscombination is larger than the prBoundary, so we will have to adjustthe rows. Our nmos devices were folded to a maximum of sixmicrons so our nmos rows need to be only six microns. The spacingbetween the rows is also large. We will show you how to easilyadjust it.

20. Select row2 and row3.

21. In the General tab change height to 6.

22. Click Update Selected.

After the Update Selected button was clicked, notice the changeswere updated in the Row Definition section. Now lets update thespacing of the rows from 5.0 to 2.5

23. Select rows 1-4.

24. Set Spacing between rows to 4.



25. Click on Update Selected.

Notice that the row spacing was reduced and now all rows fit intoprBoundary.

26. In the Placement Planning form click on Select All.

27. In the Placement Planning form click on Delete Selected.

This will delete all rows you created.

You can also delete the rows by selecting them in the layout anddeleting with the delete key.

MOS Device Level Placement – Component Assisted Mode

First we showed you a manual way to define the rows in the design. Now wewant to show you a faster semi-automated way to define your rows. Be awarethat typically you would run the Component-Assisted Mode first and dosome what-if analysis before using User-Defined mode. In this lab, since weare going to use the rows generated by Component-Assisted Mode to placethis design, we ran through the steps of manually creating the rows first.

1. Change Style to Assisted CMOS.

2. Make sure Partition is myPart.

3. Click the Row tab and set Number of Rows to Maximum.

Setting Placement Styles for Power Supplies

1. In the Rails tab click on the Layer cyclic button for Power Rail andchange to metal 2.

2. Under Net Name (for Power Rail) type in vdd!.

3. Set Width to 1.0.

4. Click on the Layer cyclic button for Ground Rail and change tometal 2.



5. Under Net Name (for Ground) type in gnd!.

6. Set Width to 1.0.

7. Change Position to Inside.

This will set the position of the metal 2 power and ground rails forall the rows.

8. Set Pattern to P-N-N-P.

Doing this will place the PMOS in the first row, NMOS in the next,then NMOS, and then PMOS.



9. Click on Calculate Estimates.

Note: There should be four rows with power rails. However wehave already created power rails during pin placement. Letus regenerate the rows without the rails.



10. In the Rails tab change the Ground Rail and Power Rail frommetal 2 to None.

11. Click on Calculate Estimates.

Four rows were generated and the horizontal percentage is ~90. Wecan change this by resizing the partition, creating a region, andresizing it.

Placing the Components Using Auto Placer

1. In the layout window select Place—Placer.

This will bring up the AutoPlacer form.

2. At the bottom of the Placer form in the Rules File region click on SetFile.

3. This will bring up the Open File form.

4. Select ./vcr/rules/mos50TROdigital.rules.




6. Click on Save As.

Note: You'll always want to do this. This will input placer data intoanother layout window such as Library 50TRO Cell encodeview layout.plc.

7. Click OK in Placer form.

The Virtuoso Placer Status window comes up. This window displaysinformation on wire lengths, what passes the placer is on, and thenumber of components placed and unplaced. Now the data has beenplaced and imported back into thel ayout window called layout.plc.Check your results against the layout.plc.bck view.

8. Close all cellviews and move to next section.

Standard Cell Placement

Component Assisted User-Defined Mode



Opening a Schematic

In the CIW, select File—Open, then enter the following values in the OpenDesign form:




The Virtuoso-XL Startup Option form appears. This form lets youopen an existing cellview or create a new cellview.




3. Ensure the following values are set in the Create New File form:

4. Click OK in the Create New File form.

The layout window is opened and the windows are rearranged sothat you can see the schematic, layout, CIW, and LSW all at once.

5. If the warning appears asking to overwrite the cell, select Yes in theoverwrite form.

The schematic window resizes and the layout view also opens.

Library Name 50TRO

Cell Name line_decode_64mixed

View Name schematic

Library Name 50TRO


View Name layout



6. In the layout window select Options—Layout XL.

7. Under Generation click on Layout Instance Views Type instdlayout.

8. Click the Add button and OK the Layout XL Options form.

Note: The above steps are very important. If these steps are notdone you may not get the standard cells for the inverters.


The Layout Generation Options form opens.

10. In the bottom of the form select Load Template File. This enablesthe field and the Load and Browse buttons.

11. In the bottom of the form select Browse.

12. Click on the following from the right list box:

./templates/line_decode_64bit.lxt

13. Select OK on the Open File form.

14. At the bottom of the Layout Generation form click on the Loadbutton.

15. Select OK on the Layout Generation Options form.

16. In the layout window select Place—Pin Placement.

The Pin Placement form opens.

17. Type B* in the Select field and press Tab to select the B pins.

Notice the choices now available for the Edge Radio Button.Whenever you have more than four sides for your prBoundary, thisfield will change from listing left, right, top, bottom boundary edgesto numbered edges. Cycle through the edges to notice that thecorresponding edge gets highlighted in the layout.

18. Click on Select edge from layout.



19. In the layout window select the top edge (edge 4).

20. Type 0 under Order and click Apply.

21. Close the Pin Placement form.

Defining the Rows

1. In the layout window Place—Placement Planning. This will openthe Placement Planning form.

2. Set Partition to Boundary and Style to Assisted Standard-Cell.

3. Choose the Row tab.

4. Select Within Row in Utilization and set this field to:

100% Utilization

5. Click on Use Filler Cells.

6. Click on Choose Type.

This will bring up the Choose Filler Component Type form.

7. Select fillc.

8. Click OK in the Choose Filler Component Type form.

9. Choose the Rails tab.

10. In Rail Pattern choose P-G. This will make the placer place thecells so that the power and ground rails of the cells alternate.

11. Set the layer for the rails to be Metal2 and a width of 1.0.



12. Click Calculate Estimates button in the bottom of the form. Thiswill generate the rows.

Note: We need some area to place the capacitors We will reshapethe prBoundary and create a partition for the capacitors.

13. In the layout window select the lower top edge of the prBoundaryand stretch it vertically to approximately a y coordinate of 100.

14. Click on softFence drawing in the LSW and draw arectangle in theavailable area of the layout window.

15. In the layout window select Place—Partitioning.

This will open the Partitioning form.

16. Type CapPart for the Partition Name click on Create Partition.

17. Enable Select in the Partitioning form.

18. Click on Link.

19. Click on Attach Shape.

20. In the layout window select the softFence shape.

21. In the Partitioning form, change Display By to Target Master.

22. Select the capacitor.

23. Change the Target Partition to CapPart and click Move.

24. Click Close to close the partitioning form.

Setting the Auto Placer Form

1. In the layout window select Place—Placer.

This will bring up the AutoPlacer form.



2. At the bottom of the Placer form in Rules File click on Set File.

The Open File form appears.

3. Select ./vcr/rules/std50TROdigital.rules.


5. Click on Save As.

6. Click on Add Filler Cells.

7. Click Apply in the AutoPlacer form.

Check if the placed view has filler cells and if the capacitors areplaced in the CapPart partition.

8. Close all the placer forms, the schematic window, and all layoutwindows.


10. Close the layout window by selecting Window—Close.


End of Lab

Library Name 50TRO


View Name schematic


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