fdxcellerator and the growing 22fdx ecosystem dr. gerd ... · parasitic extraction post-layout...

FDXcellerator and the growing 22FDX ® ecosystem

Dr. Gerd Teepe, Director Marketing for Europe

Technology Effects are Accelerating

© 2017 GLOBALFOUNDRIES 2

GLOBALFOUNDRIES Dual Track Roadmap


Markets Servers

HPC / core networking

Graphics

High-end smartphones

Premium Tier

Features High performance

Balanced cost

Markets Low & mid-end

smartphones

Wireless

IoT

Autonomous vehicles

Mobile cameras

Volume Tier

Features Low power

Cost-effective performance

RF

Embedded memory

Wireless,

Battery-powered Computing

High Performance

Computing

EUV

eNVM

eNVM

7nm FinFET

22FDX®

40/55nm

12FDXTM

7.5T RF

Auto 12/14nm FinFET

28nm

22FDX® Markets: Targeted To Serve Key Segments

Mobility AP/MPU/AI

Body-bias equivalent to +1 node

• Cortex®-A53 w/ 40% lower power

vs. 28HKMG

• Roadmap to 7nm perf. w/

12FDX™

IoT BLE / NB-IoT / GPS / NFC

Natural migration from 55/40nm

• Lower active (-80%) and standby

(1pA/cell) power than 40nm

• PA, Switch, PMIC, eMRAM

• Only 36 masks

RF & mmWave 5G / LTE / WiFi

Enables new RF architectures

• Highest ft/fmax

• Up to 30-50% area savings vs.

28nm

• mmWave PA via SOI-stacking

Automotive MCU/Radar/ADAS/IVI

Integration for car of tomorrow

• MCU w/ integrated eMRAM and

5v MOS device for ADC

• mmWave for long-range radar

• Low power ADAS

Value Extends Across Multiple Product Lines

4 © 2017 GLOBALFOUNDRIES

GF Digital Design Reference Flow

Digital Reference Flows, PDK Enablement with Foundation IP

Color-Aware DFM-Aware Variability-Aware

Path Depth

Varia

bili

ty

Includes sample block tested at all

RTL-to-GDS steps with Sign-off

Tape-out

proven Flow

FDSOI-Aware Implant-Aware

IC Compiler, IC Compiler II IC Validator (In-design)

Design Compiler

Formality (RTL vs Gate Netlist)

Formality (Gate \vs Routed Netlist)

StarRC

PrimeTime

Genus

Quantus

Tempus

7LP 7LP, 14LPP,

22FDX® 12FDX®

22FDX® 12FDX® 7LP, 14LPP,

22FDX® 12FDX®

7LP, 14LPP,

22FDX® 12FDX®

SADP-Aware

7LP, 14LPP,

22FDX® 12FDX®

Ansys

Cadence

Mentor

Synopsys

Place & Route

LVS

PEX

DRC

SPICE

Fill

EM/IR

Custom Design

*Some by request

*Additional vendor support available

SYNTHESIS

FORMAL

VERIFICATION

PLACE & ROUTE

FORMAL

VERIFICATION

PEX

STA

Conformal (RTL vs Gate Netlist)

Innovus PVS (In-design)

Conformal (Gate vs Routed Netlist)

Std cell lib

PDK

SYNTHESIS

FORMAL

VERIFICATION

PLACE & ROUTE

FORMAL

VERIFICATION

PEX

STA

Synopsys Certified Reference Flow Cadence Certified Reference Flow

5

AMS Reference Flow

Ansys

Cadence

Mentor

Synopsys

*Some by request

*Additional vendor support available

Pre-Layout Functional Verification

Custom Layout

Accelerated Custom Layout

MSOA Interoperability

Physical Verification

Parasitic Extraction

Post-Layout Functional Verification

EM/IR

Fill, DFM

ADE-XL/MMSIM, Hspice

Virtuoso/CustomCompiler

Schematic-XL/Layout-XL Layout-LDE Layout-EAD

Virtuoso/INNOVUS

Calibre, PVS, ICV

StarRC, QRC, xRC*

ADE-XL/MMSIM, Hspice

Totem, Voltus-Fi

Calibre, PVS, ICV

Prelayout Ver

Custom Layout

Virtuoso

MSOA Interop

Physical Verification

Paras Extraction

Post Layout Functional

Ver

EMIR

FILL, DFM

AMS Design Capabilities

6 © 2017 GLOBALFOUNDRIES

Ecosystem Partnering for Growth

Reduce time to market

and facilitate FDX™

SoC product design

Easy access to plug and

play solutions

Minimizes customer

development costs

Lowers barriers of

migration

Design

Services

Embedded

Software

EDA

IP

ASIC

System

IP

OSAT


Building Global Scale for FDX™

GLOBALFOUNDRIES Confidential 8

From Substrates to Fabs

Dresden, Germany Fab 1

Expanding 22FDX® FD-SOI

capacity by 40% by 2020

Developing 12FDX™ FD-SOI

technology Chengdu, China Fab 11

New 300mm fab

Partnership w/ Chengdu

Municipal Government

Existing 180 / 130nm nodes,

22FDX ramp in 2H 2019 Multi-fab sourcing

Multiple substrate supply

Long term supply agreement

Bernin, France

FD-SOI substrates

400kw/ year capacity

Already qualified, in mass production

Pasir Ris, Singapore

FD-SOI substrates

SOI HVM qualified in 2007

FD-SOI production line started

End customer qual, in 1H 2019

Full capacity of 800kw/ year

GF and SOITEC Partnership

Manufacturing Strength: Europe’s Largest & Most Advanced Fab


Phase 3 ~ 14.000 m²

(2005)

Phase 5 ~ 12.000 m²

(2011) Phase 1 ~ 14.000 m²

(1999)

Phase 2 ~ 2.500 m²

(2002)

• ~3,400 employees

• ~2x indirect jobs regionally

• Main engine of “Silicon Saxony“ Cluster

• Investment of ~$12B since 1996

• ~$6B invested from 2009 alone

• Extensive R&D network

Phase 4 ~ 10.000 m²

(2007)

FDXTM Ecosystem: Collaborative European Supply Chain Model


Design Mask Sets Substrates Wafer Fab Bump Probe Thin, BSI

Assembly & Test

Design & EDA Partners Memory & OSAT Partners

Summary

• Market: Growing Client Device Data Traffic requires next Generation Technologies

• GLOBALFOUNDRIES Dual Roadmap

• Design Readiness and -Ecosystem

• 22FDX Supply Chain


The information contained herein is the property of GLOBALFOUNDRIES and/or its licensors.

This document is for informational purposes only, is current only as of the date of publication and is subject to change by GLOBALFOUNDRIES at any time without notice.

GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions.

Other product or service names are for identification purposes only and may be trademarks or service marks of their respective owners.

© GLOBALFOUNDRIES Inc. 2017. Unless otherwise indicated, all rights reserved. Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.

Thank you

fdxcellerator and the growing 22fdx ecosystem dr. gerd ... · parasitic extraction post-layout...

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