tutorial11 solution

38
Technische Universität München Chip Multicore Processors Tutorial 11 Institute for Integrated Systems Theresienstr. 90 Building N1 www.lis.ei.tum.de S. Wallentowitz

Upload: bobby-beaman

Post on 19-Oct-2015

6 views

Category:

Documents


0 download

DESCRIPTION

cc

TRANSCRIPT

  • Technische Universitt Mnchen

    Chip Multicore Processors Tutorial 11

    Institute for Integrated Systems

    Theresienstr. 90

    Building N1

    www.lis.ei.tum.de

    S. Wallentowitz

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 2 S. Wallentowitz

    Organizational Matters

    Exam: August 5th

    5 pm

    N1190

    Allowed: calculator, 1 A4 sheet

    Next week: Practical demonstration

    LIS projects and open theses

    Exam preparation: Use the moodle forum for any questions!

    Repitutorium hour will be announced soonly: Questions and Discussion of old exam

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 3 S. Wallentowitz

    Task 10.3: Turn Model

    a) What is the difference between XY-routing and west-first-routing?

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 4 S. Wallentowitz

    Task 11.1: Routing

    a) Given is a Network-on-Chip with West-First Routing. Give all routes

    from A to B. How many of them are minimal?

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 5 S. Wallentowitz

    Task 11.1: Routing

    b) How does the number of routes change for communication from C

    to A? How many of those routes are minimal?

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 6 S. Wallentowitz

    Task 11.2: Virtual Channels

    a) Shortly describe the functionality of virtual channels. What differentiates virtual

    channels from physical channels? Give reasons for the usage of virtual channels.

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 7 S. Wallentowitz

    Router

    Virtual Channels (VCs)

    Sharing one physical link by multiple virtual channels One independent input and/or output queue per virtual channel chip area

    Output arbiter: Round robin, Priorization, ...

    Change of VC within switch possible

    route

    Sw

    itch

    arbitr.

    route arbitr.

    route arbitr.

    route arbitr.

    Router

    Physical channel/ Link

    Virtual channel 0

    Virtual channel 1

    Output arbiter

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 8 S. Wallentowitz

    Difference to physical channels Virtual channels share a link

    One link per physical channel

    Usage of virtual channels Reduce the impact of contentions on latency (today)

    Deadlock avoidance

    In the network

    message-dependent deadlocks

    a) Shortly describe the functionality of virtual channels. What differentiates virtual

    channels from physical channels? Give reasons for the usage of virtual channels.

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 9 S. Wallentowitz

    b) To enable virtual channels, buffers are required. The number of its which can be

    stored in the buffers increases the required memory. According to you, why are 1-flit

    buffers disadvantageous?

    Router

    Router

    D

    Router

    D D Flit is transfered if Flit is in buffer this cycle

    Next buffer can take the flit

    Decision within one cycle

    No dependency from next buffers transmission to this buffers allowed!

    1-flit buffer: Stop & Go When flit in buffer we cannot take another one

    Cannot take the transfer status in account (combinational path)

    Toggling transfers

    Need at least 2 flit buffers

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 10 S. Wallentowitz

    c) In the following sketch, you find the subnetwork of a Network-on-Chip. The NoC

    routers are buffered on the input with 2-flit buffers. Three communication streams

    flow through the NoC. The communication streams consist of four it long packets.

    These packets are generated every 12 cycles. Assume that no other traffic exists.

    The timing relation among the packets is that packets 1 and 2 are generated at the

    same time, that is identical to the time that packet 3 enters router 2. Give the minimal

    latency of stream 1 and 2.

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 11 S. Wallentowitz

    d) Complete the timing diagram. All required buffers are given. Additionally the links

    between the routers are given to ease filling it out. What are the latencies of packet 1

    and 2? Shortly describe the situation at time step 3. Also give the effective utilization

    rate of each link.

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 12 S. Wallentowitz

    0

    1

    2

    3

    T=0

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 13 S. Wallentowitz

    0

    1

    2

    3

    T=1

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 14 S. Wallentowitz

    0

    1

    2

    3

    T=2

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 15 S. Wallentowitz

    0

    1

    2

    3

    T=3

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 16 S. Wallentowitz

    0

    1

    2

    3

    T=4

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 17 S. Wallentowitz

    0

    1

    2

    3

    T=5

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 18 S. Wallentowitz

    0

    1

    2

    3

    T=6

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 19 S. Wallentowitz

    0

    1

    2

    3

    T=7

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 20 S. Wallentowitz

    0

    1

    2

    3

    T=8

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 21 S. Wallentowitz

    0

    1

    2

    3

    T=9

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 22 S. Wallentowitz

    0

    1

    2

    3

    T=10

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 23 S. Wallentowitz

    0

    1

    2

    3

    T=11

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 24 S. Wallentowitz

    0

    1

    2

    3

    T=12

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 25 S. Wallentowitz

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 26 S. Wallentowitz

    e) The NoC is extended with virtual channels. For each stream one virtual channel is

    allocated. The following table is extended accordingly. Repeat the procedure for

    virtual channels. What are the differences?

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 27 S. Wallentowitz

    0

    1

    2

    3

    T=0

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 28 S. Wallentowitz

    0

    1

    2

    3

    T=1

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 29 S. Wallentowitz

    0

    1

    2

    3

    T=2

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 30 S. Wallentowitz

    0

    1

    2

    3

    T=3

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 31 S. Wallentowitz

    0

    1

    2

    3

    T=4

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 32 S. Wallentowitz

    0

    1

    2

    3

    T=5

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 33 S. Wallentowitz

    0

    1

    2

    3

    T=6

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 34 S. Wallentowitz

    0

    1

    2

    3

    T=7

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 35 S. Wallentowitz

    0

    1

    2

    3

    T=8

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 36 S. Wallentowitz

    0

    1

    2

    3

    T=9

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 37 S. Wallentowitz

    0

    1

    2

    3

    T=10

  • Technische Universitt Mnchen

    Institute for Integrated Systems Chip Multicore Processors Tutorial 10 38 S. Wallentowitz