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1Abstract—This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper firstly establishes the equivalent common-mode circuit of the proposed inverter. And the impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. Index Terms—Control method, current source inverter, leakage current, transformer-less photovoltaic inverter.

I. INTRODUCTION With the rapid development of photovoltaic (PV) industry

[1], extensive PV inverter topologies have been developed and studied to enhance system performances, such as reliability, efficiency, cost, and power density [2-5]. PV inverters can mainly be categorized into voltage source inverters (VSIs) and current source inverters (CSIs). Nowadays VSI with an additional boost converter is the most common PV interface as a result of the trade-off among wide input voltage range, low current stress, and moderate switching stress [6].

Alternatively, CSI utilizes inductors to limit the dc-link current ripple and the aluminum electrolytic capacitors (AECs) are eliminated [7]. Therefore, current source based PV inverters may have a longer operation life. Moreover, the inherent voltage boosting capability makes the frond-end boost converter used in VSI unnecessary. Then, the grid-tied inverter can be a simple single stage structure. Another merit of CSI is the continuous dc-link current, which is beneficial for maximum power point tracking (MPPT) operation in PV application[8]. Besides, the newly developed reverse-blocking

1 Manuscript received April 11, 2016; revised May 20, 2016, June 13, 2017, and August 20, 2017; accepted October 23, 2017. This work was supported by the National Natural Science Foundation of China under Grants 61622311 and 61573384, Natural Science Foundation of Hunan Province of China under Grant 2016JJ1019, and the Project of Innovation-driven Plan in Central South University. Corresponding Author: Yonglu Liu.

Y. Sun, Y. Liu, M. Su, H. Han, and X. Li are with the School of Information Science and Engineering, Central South University, Changsha 410083, China(e-mail: [email protected]; [email protected]; sumeicsu@ mail.csu.edu.cn; [email protected]; [email protected]).

X. Li is with the College of Electrical and Information Engineering, Hunan University, Changsha 410082, China (e-mail: [email protected]).

insulated-gate bipolar transistors (RB-IGBTs) [9-11] also promote the proliferation of CSI in distributed and renewable energy systems.

Applications of CSI in PV systems have been investigated recently in [7, 8, 12-19]. These studies are mainly focused on pulsating power decoupling [12, 13], dynamic modeling and performance analysis [8], control methods [14, 15], and common-mode voltage (CMV) reduction [16-19].

The CMV leads to a large common-mode current (CMC), which is also termed as the leakage current, in the absence of isolating transformers. The leakage current could deteriorate power quality and electromagnetic compatibility (EMC), reduce module lifetime, and bring potential safety threat [20]. Thus, it must be limited to comply with the grid standards [21]. The key to suppress the leakage current is to eliminate or reduce the CMV. For CSIs, the goal is usually achieved by modifying modulation schemes [16] or circuit structures [17-19].

Literature [16] proposed a modified space vector PWM for reducing the CMV by properly selecting zero states [16]. Besides, two X2-type capacitors were used for further reducing the leakage current. However, such method is only suitable for the case that the values of the PV parasitic capacitors (50-150nF/kW for glass-face modules and 1uF/kW for thin-film modules [20]) are much smaller than those of X2-type capacitors. Otherwise, high frequency currents cannot be bypassed by the X2-type capacitors and will flow through the parasitic capacitors. A four-leg CSI [17] and a CH7 inverter [18] were proposed to reduce the CMV by adding a zero vector with zero CMV. In both of them the CMV is reduced. However, high frequency components cannot be completely eliminated. To fully eliminate the CMV, literature [19] proposed a split-capacitor based four-leg current source PV inverter. However, the added leg increases cost and control complexity. Moreover, the neutral-point voltage balance problem is not considered. On the other hand, the split-capacitor four-wire voltage source based inverter [22, 23] has been widely investigated in terms of various applications [24-27], control methods [28, 29], capacitor voltage balance [29], and voltage utilization ratios [30].

In this study, a split-capacitor four-wire CSI is proposed. Though the topology is the dual of the split-capacitor four-wire VSI, there are still no reported studies about it as far as we know. As the midpoint of the dc-link is tied to the neutral of the grid (Y-connected), the voltages between the dc bus and the ground are almost constant. Then the leakage current issue is well dealt with. Compared with the four-leg CSIs proposed in [17-19] the

Yao Sun, Member, IEEE, Yonglu Liu, Student Member, IEEE, Mei Su, Hua Han, Xing Li, and Xin Li

Topology and Control of a Split-Capacitor Four- Wire Current Source Inverter With Leakage

Current Suppression Capability




2

Fig. 1. Proposed three-phase transformer-less PV inverter.

Fig. 2. Equivalent circuit model of the proposed converter. proposed inverter needs fewer semiconductors. In this paper, both the differential and common mode equivalent circuits for the proposed inverter are analyzed. The effect of parasitical inductance of neural wire on CMV is studied. To obtain good performances, some nonlinear control methods are developed.

The remainder of this paper is organized as follows. Section II illustrates circuit description and analysis. Section III discusses the control design. Section IV presents simulations and experimental results to verify the theoretical analysis. Finally, section V concludes the main points of this paper.

II. CIRCUIT CONFIGURATION AND ANALYSIS The proposed split-capacitor four-wire CSI is shown in Fig.

1. Compared with the conventional CSI, a neutral line is added to connect the midpoint of the dc-link capacitors (O) and the neutral point of ac filter capacitors (E). LN represents the parasitic inductance of the wire between points O and E. LE and Ro represent the inductance and resistance of the wire between the grid ground and the neutral point of ac filter capacitors.

For the sake of analysis, the equivalent circuit model is shown in Fig. 2. The voltages up and un are expressed as

1 3 5[ ] =

ca

p cb

cc

uu S S S u

u

(1)

2 4 6[ ] =

ca

n cb

cc

uu S S S u

u

. (2)

Currents ia, ib and ic are expressed as follows,

1 1 2 2

3 1 4 2

5 1 6 2

= − = − = −

a dc dc

b dc dc

c dc dc

i S i S ii S i S ii S i S i

(3)

where

{ }1, when on

, 1, 2,3, ,60, when off

= ∈ ⋅⋅⋅

iS i .

When studying the common mode circuit, the influences of differential mode circuit can be neglected. Thus up, un, ia, ib, and ic are treated as independent sources. Because the leakage current is mainly caused by the high frequency components of the CMV, C1, C2, and Cf are treated as short circuit for simplicity. Then the common mode circuit is obtained, as illustrated in Fig. 3(a). By using the equivalent conversion of circuits a simplified common mode circuit is derived, as shown in Fig. 3(b) [31]. The CMV (ucm), CMC (icm), and impedances Z1 and Z2 are expressed as

(a)




3

(b)

Fig. 3. Circuit model by only considering CMV. (a) Common mode circuit model. (b) Simplified version.

( )2 1

1 2 1 2

+=

+ +N dc p dc n

cmdc dc dc N dc N

L L u L uu

L L L L L L (4)

11 2 j+ +

pv

cmcm

EC

uiZ Z Rω

=+

(5)

1 21

1 2 1 2

=+ +

dc dc N

dc dc dc N dc N

L L LZL L L L L L

(6)

2 3 //( )= +fLE oZ L R . (7)

From (4), it is found that the CMV depends not only on the voltages up and un, but also the system parameters Ldc1, Ldc2, and LN. According to (1), (2), and (4), it is clear that ucm contains numerous high frequency harmonics, which are the major causes for the leakage current.

A. CMV in Traditional CSI When the value of LN is infinite, the studied system becomes

the conventional CSI. From (5), the CMV is expressed as follows.

2 1

1 2

( )2 2( )+ −

= ++

p n dc dc pncm

dc dc

u u L L uu

L L (8)

where upn=(up-un) is the differential-mode voltage (DMV). The second term on the right side of (8) is caused by asymmetrical differential-mode filter inductors, which increases the CMV. Therefore, it is important to keep a symmetrical circuit to reduce the CMV and the leakage current [2, 3, 5, 31]. If Ldc1= Ldc2, the CMV becomes (up+un)/2, which is usually defined as the CMV in current source converters [16-18, 32].

B. CMV in Proposed CSI In the proposed inverter, the parasitic inductance LN is far

less than the differential common filter inductors Ldc1 and Ldc2. Then (5) can be further simplified to

1 2( )p n

dc dc

u ucm N L Lu L= + (9)

Clearly, in the ideal case where LN=0, ucm will be eliminated completely and the leakage current can be well suppressed. Though the value of LN in practice can never be zero [24], it could be very small through the optimum design of the main circuits. Besides, the unbalance between the filter inductors Ldc1 and Ldc2 has little impact on ucm as the multiplier LN is very small.

III. MODELING AND CONTROL DESIGN FOR DIFFERENTIAL MODE CIRCUIT

There are three control targets for the PV system: 1) to maintain capacitor voltage balance, 2) to regulate the dc-link voltage, 3) to obtain the desired sinusoidal grid currents. In the process of designing controllers, assume LN=0 and C1=C2=C.

This section firstly introduces the averaged circuit model and modulation strategy to pave the way for the controller design. Then current and voltage balance controllers and dc-link voltage controller are designed in time domain. And the stability is guaranteed in design process.

A. Averaged Modeling According to Fig. 2, the averaged model for the differential

mode equivalent circuit of the studied converter is expressed as follows:

Differential equations on dc side: 1

1= −dcdidc pdtL u u (10)

22= +dcdi

dc ndtL u u (11) 1

1dcdu

dc dcdtC I i= − (12) 2

2dcdu

dc dcdtC I i= − (13)

1 3 5

2 4 6

+ ++ +

=

=

p ca cb cc

n ca cb cc

u d u d u d uu d u d u d u

(14)

Differential equations on ac side: = −cadu

f a gadtC i i (15)

= −cbduf b gbdtC i i (16)

= −ccduf c gcdtC i i (17)

1= − −gadi

f ca ga E EdtL u u u (18)

1= − −gbdi

f cb gb E EdtL u u u (19)

1= − −gcdi

f cc gc E EdtL u u u (20)

1

( ) ( )+ += + + +ga gb gcd i i i

E E E o ga gb gcdtu L R i i i

(21)

1 1 2 2

3 1 4 2

5 1 6 2

= − = − = −

a dc dc

b dc dc

c dc dc

i d i d ii d i d ii d i d i

(22)

where di is the duty ratio of the switch Si during each switching cycle.

Taking the zero-sequence components into consideration, summing (15)-(17) yields

00 0= −cdu

f gdtC i i . (23) where

0 3 , ( , , )+ += ∈a b cx x xc gx x u i i , 1 2

0 3dc dci ii −= .

Similarly, summing (18)-(20) leads to g0

0 0( 3 ) 3+ = −di

f E c o gdtL L u R i . (24) To study the dynamics without the zero sequence

components, subtracting (23) from (15)-(17) leads to: ' ' '= −cadu

f a gadtC i i (25) ' ' '= −cbdu

f b gbdtC i i (26) ' ' '= −ccdu

f c gcdtC i i (27)

where '0 , ( , , )= − ∈j jx x x j a b c .

Similarly, subtracting (24) from (18)-(20) yields




4

' '= −adif ca gadtL u u (28)

' '= −bdif cb gbdtL u u (29)

' '= −cdif cc gcdtL u u . (30)

B. Modulation scheme Any open-circuit must be avoided in the CSI, so the duty

ratios should satisfy the following constraints: 1 3 5+ + 1=d d d (31)

2 4 6+ + 1=d d d . (32) On the other hand, according to voltage second balance of

inductors Ldc1 and Ldc2, up and un should be constants in the steady state. According to (14), (31), and (32), di is designed as:

''1 1

''3 1

''5 1

1 31 31 3

a

b

c

d m ud m ud m u

= +

= + = +

(33)

''2 2

''4 2

''6 2

1 31 31 3

= −

= − = −

a

b

c

d m ud m ud m u

(34)

where m1 and m2 are the modulation indexes for the upper and bottom switches. And they are limited to be not larger than 1/3 to ensure all duty ratios are not less than zero. ''

ju is expressed as:

''

'' 23

'' 23

ˆcos( )ˆcos( )ˆcos( )

a o

b o

c o

u

u

u

π

π

φ ϕ

φ ϕ

φ ϕ

= + = + −

= + +

(35)

where oφ is the estimate of phase angle of filtering capacitor

voltages ( oφ ), which is usually obtained by a phase locking loop (PLL). And φ is used to regulate the reactive power.

C. Current Balance (Voltage Balance) Control To ensure normal operation, the split dc-link capacitor

voltages udc1 and udc2 and dc-link currents idc1 and idc2 should be balanced.

Subtracting (11) from (10) and (13) from (12) lead to

( )= − +

dcdc p n

diL u u udt

(36)

dcdc

duC idt

= −

(37)

where 1 2= −dc dc dcu u u and 1 2= −

dc dc dci i i . Substituting (33)-(35) into (36), we have

1= −

dcdc

diL u vdt

(38)

where 3

1 0 1 22

' 2 ' 2 ' 2

2 ( ) cos( )

( ) ( ) ( )ˆ

ϕ φ

φ φ φ

= + − + = + +

= −

c m o

m ca cb cc

o o o

v u u m m

u u u u .

To balance the currents idc1 and idc2, v1 is designed as

1 =

dcv ki (39) where k is a positive gain. According to (39), we have

032

21 2 cos( )

dc c

m o

ki u

um m

ϕ φ

−

+− =

. (40)

To prove the stability of the subsystem which is comprised of (37) and (38), a Lyapunov function is constructed as follows

2 212 ( )= +

dc dcV Cu Li . (41) Taking the derivative with respect to time, we have

2 0dcV ki= − ≤ . (42)

According to La Salle's theorem, ( ) 0dcu t → and ( ) 0dci t → when →∞t . Thus, the goal of current balance and

voltage balance is achieved. It can be seen that the voltage balance is realized as long as

the current balance has been achieved. On the other hand, according to (37) the current balance is realized as long as the voltage balance has been achieved. Therefore, it is enough to consider either current balance control or voltage balance control. That simplifies the controller design and reduces the number of sensors.

Note that the zero sequence components are contained in (38). Thus the stability of the zero dynamic system, which is comprised of (23) and (24), will be proved as follows:

A Lyapunov function is constructed as 2 210 02 [ ( 3 ) ]= + +z f c f E gV C u L L i . (43)

Taking the derivative with respect to time and considering ( ) ( ) 0dc dci t i t= =

, we have 2

03 0= − ≤

z o gV R i . (44) By similar derivations, it can be found that the zero dynamic

system is asymptotically stable.

D. DC Voltage Control The dc voltage controller is designed to regulate the dc-link

voltage (udc). The reference is obtained according to MPPT technique in PV applications [33]. In this study, the adaptive back-stepping control [34] is adopted for dc voltage control.

Summing (10) and (11) and summing (12) and (13) yield 2dcdu

dcdtC I i∑= − (45)

( )∑ = − −didc p ndtL u u u (46)

where 1 2dc dci i i∑ = + . Substituting (14) and (33)-(35) into (46), we have

2∑ = −di

dcdtL u v (47) where

32 1 22 ( ) cos( )ϕ φ= + + m ov u m m .

Assume Idc is an unknown slowly changing parameter and *dcu is the dc-link voltage reference. A new variable is defined

as *

1 = −dc dcz u u , (48) then

*1 2 ∑= − + dc dcCz Cu I i . (49)

i∑ is taken as a virtual control input. And if

∑ ∑=i i (50) where




5

Fig. 4. Block diagram of the control scheme.

*1 1

ˆ2∑ = − + −dc dci Cu I k z , k1 is a positive gain and

dcI is the estimate of Idc, it is obvious that z1 is stable. In fact, i∑ is not the real control input, another new variable is defined as

2 ∑ ∑= −z i i . (51) Then (49) is rewritten as

1 1 1 22= − +

dcCz I k z z (52) where ˆ

dc dc dcI I I= − . Taking the derivative of both sides of (51), then

*2 2 1 1

ˆ( 2 )= − + − +

dc dc dcLz L u v Cu I k z . (53) Let

21 1 2* 1

2 1 2ˆ2 ( ) ( )= + − + − + +

k k kdc dc dc L C C Lv u Cu I z z ,

then 12

2 1 2 2= − − +

k LdcCLz z k z I (54)

where k2>0. Based on the derivation above, we have 2

* 1 1 1 21 2

32

ˆ2 ( ) ( )1 2 cos( )

k k kdc dc dc L C C L

m o

u Cu I z z

um m

ϕ φ

+ − + − + +

++ =

. (55)

To verify the stability of the system, a Lyapunov function is constructed as

2 2 21 1 12 1 22 2 2γ= + +

dcV Cz Lz I (56)

where1 1 2

ˆ2( / )γ += −

dcIz Lk z C .

Taking the derivative of both sides of (56) leads to 2 21

2 1 1 2 22 0= − − ≤V k z k z . (57) It is clear that *( )dc dcu t u→ when t →∞ . According to (40) and (55), it is easy to get m1 and m2.

Finally, the duty ratio di could be calculated according to (33) and (34). The overall control diagram of the control scheme is shown in Fig. 4. The phase information is obtained by a PLL and φ is designed according to the required reactive power.

E. Small Signal Stability Analysis of Grid Side Dynamics In this sub-section, the stability of the grid side dynamics

(zero dynamics) will be studied. Based on the analysis above, it is reasonable to assume that idc1=idc2=Idc in the steady state. Substituting (33)-(35) into (22), we have

' ''1 2

' ''1 2

' ''1 2

( )( )( )

= +

= + = +

a dc a

b dc b

c dc c

i m m I ui m m I ui m m I u

. (58)

The dynamic equations of the grid side in the stationary reference frame are given as follows:

'

'

'

'

= − = −

c

g

duf gdt

dif c gdt

C i i

L u u. (59)

For convenience, (59) is written in a synchronously rotating

reference frame, which is tied to the vector oje φ . Then, it is decomposed into d-axis and q-axis as follows:

'

'

'

'

' '31 22

' '31 22

' '

' '

ˆ( ) cos

ˆ( ) sin

ˆ

ˆ

ϕ φ

ϕ φ

φ

φ

= + − +

= + − − = − + = − −

cd

cq

gd

gq

duf dc gd f o cqdt

duf dc gq f o cddt

dif cd gd f o gqdt

dif cq gq f o gddt

C m m I i C u

C m m I i C u

L u u L i

L u u L i

. (60)

where φo is obtained by the PLL which is expressed as

'ˆ 2 φφ π= +

o grid cqf k u (61) where fgrid is a feed-forward term with the value of 50Hz in this study and 0φ >k .

In the rotating reference frame, um can also be expressed as: ' 2 ' 2( ) ( )= +m cd cqu u u . (62)

Substituting (55), (61), and (62) into (60) leads to '

' 2 ' 2

'

' 2 ' 2

'

'

cos ' '

( ) ( ) cos( )

sin ' '

( ) ( ) cos( )

' '

' '

'

ˆ

ˆ

ˆ

ˆ

ˆ 100

ϕ

ϕ φ

ϕ

ϕ φ

φ

φ

φ

φ

φ

φ π

+ +

+ +

= − + = − −

= − +

= − −

= +

cd v

cd cq o

cq v

cd cq o

gd

gq

du Pf gd f o cqdt u u

du Pf gq f o cddt u u

dif cd gd f o gqdt

dif cq gq f o gddt

o cq

C i C u

C i C u

L u u L i

L u u L i

k u

(63)

Here Lyapunov's indirect method is used to investigate the stability of the zero dynamics described by (63). The Jacobian matrix A of (63) around the steady-state operating point is at the bottom. ' ' ', ,cd cq gdU U I and '

gqI are the state variables in steady-state operation point and Pv indicates the power extracted from the PV arrays. Taking Pv and kϕ as two variable parameters in matrix A, their effects on the system stability are studied by the root locus technique.

3

2

3cos' ' 2 ' 2 '2

cos( )cos ' 2 ' 2 '

cos( )

3sin sin' 2 ' 2 ' ' ' 2 '2

cos( ) cos( )

100 2 [( ) ( ) ] 1

[( ) ( ) ] 100 [( ) ( )

[( ) ( ) ] 0ϕ

φ ϕ φϕ

ϕ φ

ϕ ϕφϕ φ ϕ φ

π

π

−

− +

+

−

+ +

+ − +

+ + + +

+− −

− −=

f o

f f cq v cd cq cqov cd cq cdC f f

v cd cq cd f f cq v cd cqo o

f

C k C U P U U U

C C

P U U U C k C U P U U

C

P U U U

A

32 ' '2

''

' '

] 1

1001

1 100

0

0

0 0

φ

φφ

φ φ

π

π

−+

+

− +

− −

cq f cd

f f

f f cqgqf f

f gd f f cq

f f

U k C U

C C

L L k UL L

L k I L L k UL L

k I

(64)




6

The root locus is shown in Fig. 5(a) when Pv varies from 100 to 10000 while kϕ is fixed at 1. As seen, the closed-loop poles are always located in left half-plane. Fig. 5(b) shows the root locus when kϕ varies from 1 to 100 while Pv is fixed at 500. As seen, by proper selection of parameters, the zero dynamics on grid side are stable in the sense of small signal stability.

(a)

(b)

Fig. 5. Root locus (a) when Pv varies from 100 to 10000 while kϕ is fixed at 1 and (b) when kϕ varies from 1 to 100 while Pv is fixed at 500.

IV. SIMULATIONS AND EXPERIMENTAL RESULTS

A. Simulations Results Simulation studies are carried out in Matlab/Simulink

environment to verify the proposed topology and control method. Main parameters are listed in Table I.

Fig. 6 shows the waveforms of phase voltage uga, three phase grid currents iga, igb, and igc, and the modulation indexes m1 and m2. As can be seen, the grid currents are sine shaped and the power factor is almost unit. Fig. 7 shows the effectiveness of the developed voltage balance control. In the beginning the capacitors are charged to be different voltage levels but the voltages become balanced quickly after the system starts up.

The voltage difference between dc-link point P and the neutral point of the filter capacitors E and the leakage current iE are shown in Fig. 8. With the proposed topology, the voltage upe is clamped to udc1 without little high frequency components. That means the voltage across the parasitic PV capacitor Cpv is almost constant. Therefore, the leakage current is very small. That confirms the effectiveness of the proposed scheme to suppress the leakage current.

Sometimes grid converters are expected to provide certain reactive power to help stabilize the grid voltage. Fig. 9 shows the waveforms when the grid currents lag and lead the grid voltages 20°. Fig. 10 shows the dynamic response when the load power changes suddenly. As seen, there is no overshoot on

dc or ac currents with the proposed control algorithm. Therefore, the dynamic process is smooth.

TABLE I PARAMETERS USED IN SIMULATION AND EXPERIMENT

Fig. 6. Simulation waveforms of phase voltage uga and three phase grid currents iga, igb and igc.

Fig. 7. Simulation waveforms of dc-link voltages udc1 and udc2 and currents idc1 and idc2.




7

Fig. 8. Voltage between the dc-link P point and the neutral point of filter capacitors uPE and leakage current iE.

Fig. 9. Simulation waveforms with φ being -20° and 20°.

Fig. 10. Dynamic simulation waveforms showing 1000 W to 1500 W step-up power change.

B. Experimental Results An experimental prototype based on the circuit configuration

shown in Fig. 1 has been built for experimental verification. The experimental parameters are the same as those used in the simulations. The PV array is simulated with a dc voltage source of 220V. The selected insulated-gate bipolar transistors (IGBTs) and diodes are IKW40N120H3 (1200V, 40A) from Infineon and DSEI 60 (1200V, 52A) from IXYS, respectively. The control algorithm of the converter is realized by a combination of digital signal processor TMS320F28335 and field programmable gate array FPGA EP2C8T144C8N. Differing from literatures [16] and [19], this paper use no large DC common mode inductors to further suppress the leakage current. Two groups of experimental results are presented. One is

composed of Figs. 11-16, which are used to validate the effectiveness of the proposed control method. The other includes Figs. 17-19, which are used to verify the performance of reducing the CMV and the effects of the parasitic inductance LN.

Fig. 11 shows the steady-state experimental waveforms of the ac grid voltage uga and grid currents iga, igb, and igc. As seen, under the developed control method the grid currents are sine shaped (the total harmonic distortion is 3.99%) and the power factor is 0.98. Experimental results are consistent with those in the simulation except that a distortion exists in the practical grid currents. That is caused by the limit of the minimum duty ratio (determined by the characteristic of the used active switches) and the overlapping communication of the one whole switching leg (avoiding open-circuit of dc-link inductor current).

Fig. 12 shows waveform of the neutral line current iN. The RMS value is 546 mA. However, it doesn’t cause the drifting of the midpoint potential of the dc-link voltage thanks to the proposed balance control. As shown in Fig. 13, the capacitor voltages udc1 and udc2 are almost equal. In addition, it also can be seen that the dc-link currents idc1 and idc2 are the same. The transient experimental waveforms during start-up are shown in Fig. 14. Before start-up the capacitor voltages are charged to be different voltage levels for purpose and both the dc currents are zero. After start-up, it can be seen that the voltage balance is achieved quickly and the dc-link currents are equal to each other, which is consistent with the simulation results.

Fig. 11. Experimental waveforms of phase voltage uga and three phase grid currents iga, igb and igc.

Fig. 12. Phase voltage uga and the neutral line current iN.




8

Fig. 13. Experimental waveforms of dc-link voltages udc1 and udc2 and currents idc1 and idc2.

Fig. 14. Experimental waveforms during start-up.

(a)

(b)

Fig. 15. Experimental waveforms with φ being (a) -20° and (b) 20°.

Fig. 16. Dynamic experimental waveforms showing 1000 W to 1500 W step-up power change.

Fig. 15 shows the waveforms when φ=±20°. Fig. 16 shows the dynamic response when the load power raises. As seen, the experimental results are in accordance with those in the simulation.

Figs. 17 shows common-mode behavior with the propsoed topology. As seen, uPE is almost constant (110V) and the RMS of the leakage current is only 48 mA, which complies with the relevant standards. The experimental results indicate that the proposed scheme can suppress the leakage current effectively. Fig. 18 shows the experimental results with a 3.2 μH parasitic inductance (LN) in the neutral line. As seen, the high frequency components in uPE increase obviously, compared with those in Fig. 17. And the leakage current increases to 55 mA. The experimental results show that the parasitic inductance will deteriorate the common-mode performance, which is in consistence with the analysis in section II.

Fig. 19 shows the common-mode behavior of the traditional three phase CSI (without an electrical line between the midpoint of the dc-link and the ground). It can be found that the high frequency CMV is obvious and the leakage current is up to 363 mA, which will trigger the residual current device (RCD). So the proposed circuit has an advantage of suppressing the leakage current over the traditional three phase CSI. However, it also has some weaknesses. The extra current balance (voltage balance) controller increases the control complexity. Moreover, from (58), the maximum usage ratio of the dc-link current (the ratio between the amplitude of the grid current and the dc-link current) is 0.667. While it is 0.866 in the traditional three phase CSI. On the whole, the proposed circuit can be a good candidate for PV application.

Fig. 17. Experimental results of uPE and iE in the proposed CSI (with the neutral line).

Fig. 18. Experimental results of uPE and iE with LN=3.2uH.




9

Fig. 19. Experimental results of uPE and iE without the neutral line.

V. CONCLUSION To address the CMV issue in three-phase PV grid-connected

inverter, the works of this paper are summarized as follows: 1) A split-capacitor four-wire CSI is proposed to reduce the

leakage current. As the midpoint of the dc-link voltage and the neutral point of the filter capacitors are connected, the CMV is reduced significantly. So the leakage current is well suppressed. The circuit topology is easy to realize without additional semiconductor devices.

2) The impact of the neutral line inductance on the leakage current is studied. It is apparent that the leakage current has a positive correlation with parasitical inductance LN. Therefore, the neutral line should be as short as possible to decrease the parasitical inductance in practice.

3) Nonlinear control methods are developed to accomplish the balance of dc-link voltages and currents as well as dc bus voltage control. The system stability has been proved by a constructive way.

4) Simulations and experiments were carried out to verify the correctness of the theoretical analysis.

The proposed transformer-less CSI is suitable for PV application due to small dc film capacitors, single stage circuit topology, and low leakage current. Meanwhile, it is also a good candidate for 3-phase 4-wire uninterruptible power supplies (UPS).

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Yao Sun (M’13) was born in Hunan, china, in 1981. He received the B.S., M.S. and Ph.D. degrees from the School of Information Science and Engineering, Central South University, Changsha, China, in 2004, 2007 and 2010, respectively. He has been an associate professor with the School of Information Science and Engineering, Central South University, China.

His research interests include matrix converter, micro-grid and wind energy conversion system.

Yonglu Liu (S’16) was born in Chongqing,

China, in 1989. He received the B.S. and M.S. degrees in electrical engineering from Central South University, Changsha, China, in 2012 and 2015, respectively. He is now pursuing Ph.D. degree in electrical engineering, Central South University, Changsha, China.

His research interests include matrix converter and AC/DC converter.

Mei Su was born in Hunan, China, in 1967. She received the B.S., M.S. and Ph.D. degrees from the School of Information Science and Engineering, Central South University, Changsha, China, in 1989, 1992 and 2005, respectively. Since 2006, she has been a Professor with the School of Information Science and Engineering, Central South University.

Her research interests include matrix converter, adjustable speed drives, and wind energy

conversion system.

Hua Han was born in Hunan, China, in 1970. She received the M.S. and Ph.D. degrees from the School of Information Science and Engineering, Central South University, Changsha, China, in 1998 and 2008, respectively.

Her research interests include microgrids, renewable energy power generation systems, and power electronic equipment. She was a visiting scholar at the University of Central Florida, Orlando, FL, USA, from April 2011 to April 2012.

She is currently an Associate Professor with the School of Information Science and Engineering, Central South University.

Xing Li was born in Hunan, China, in 1988. She received the B.S. degree in Automation, in 1989, M.S. and Ph.D. degrees in electric engineering, in 2009 and 2014 respectively, all from the School of Information Science and Engineering, Central South University. She is currently an Assistant Professor with the College of Electrical and Information Engineering, Hunan University, China.

Her research interests include power electronic converter and wind energy conversion system.

Xin Li was born in Shaanxi Province, China,

in 1994. He received the B.S. degree from the Central South University, Changsha, China, in 2015, where he is currently working toward the M.S. degree in electrical engineering.

His current research interests include matrix converters and ac/dc converters.

topology and control of a split-capacitor four- wire ...pe.csu.edu.cn/lunwen/topology and control of...

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