tm low inductance capacitor in organic...

2009NTK Confidential -1-

iNEMI Packaging Substrate Workshop

LICOPTM

Low Inductance Capacitor in Organic Package



Electrical performance

Fine designFine C4 bump pitch

Thin core

FPPTH

LIVAC (Low Inductance Via Array Capacitor)

Fine Alignment

Fine L/S

Technology Roadmap

Multi layers core

Tight tolerance

High reliability

Via integrity on stacked via

Anti HAST on fine design

Low warpageHybridCore-less

Alternative BU process

CTE matching



Electrical requirement

Requirement summary

Need enormous cost & time to develop new material system

Low cost substrate

Mechanical requirement



Concern/Gap

Need low inductance and rigid substrate solution

Need high-C and low-L decoupling capacitorNeed to reduce number of conventional chip capacitor.

Gap #1/Electrical

Gap #2/MechanicalNeed warpage controlCTE matching to low-k die material



Concept

• Chip capacitor• Organic substrate

Current

BU layerCore layer

Power source

IC chip CC

• Array type ceramic capacitor• Organic substrate

BU layerCore layer

Power source

IC chip

Array type capacitor

HybridOrganic and Ceramic technology combination

Low Inductance Capacitor in Organic PackageLICOPTM



Diesubstrate

LIVAC

• FeatureArray type capacitor can be located right under the die.

Short distance

Hybrid structure

• Cross section

Capacitor inside

Die



LIVAC

Low Inductance Via Array CapacitorR



Via Array type

MLCC

IC ChipSubstrate

NTK had developed the array-type capacitor,“LIVAC”, with low inductance.LIVAC can achieve high speed power delivery.

Array type decoupling capacitor

Power source

Conventional2T type

Peripheralarray type

LW-reversedtype

LIVAC

Current structure



Electrical featureElectrical property

Low inductance: ~ 1 pH

Structure of LIVAC

- Hundreds of via/termination- Matrix-like arrangement (mutual inductance effect)

Via structure giving extremely low inductance

Multi-layer structure for high capacitance

Via electrode(Ni-based)

Cross-sectional image

-+Ni inner electrode

Dielectrics(BaTiO3)

-+ -+ +

Diesubstrate



Mechanical features

• Cu plating “Clam-armor” structure• “Peripheral toughening metal layers”

Toughened structure for mechanical reliability

Surface metal structure for adhesion reliability w/ resin material and via connectivity

• Full metal Cu plating surface layer (Roughened w/ chemical etching)



Young’s modulus

(GPa)

Poisson’s ratio

CTE(10-6/K)

Dielectric material 102 0.35 40 – 120oC: 6.3

140 – 300oC: 11.3

LIVAC 118 0.33 40 – 120oC: 10.1140 – 300oC: 11.9

Item Method Sample size

Young’s modulusPoisson’s ratio

Sing-around(Ultrasonic)

X: 11 mmY: 14 mmt: 0.8 – 0.9 mm

CTE TMAX: 4 mmY: 10 mmt: 0.8 – 0.9 mm

(CTE in Y direction)

t

XY

< Measurement method and sample size >

Mechanical properties of LIVAC



Electrical Performance



Electrical characteristicSubstrate ele. characteristic.

C = 37.1 uFL = 2.0 pH

Current Substrate(CC mounted)

Concept

C = 3.5 uFL = 42.1 pH

Schematic comparison

LICOP substrate by embedded ceramic array type capacitor achieves lower inductance and higher capacitance.

DieSubstrate

Low Inductance Via Array Capacitor

Die

Conventional C/Cx 16pcs

37.1 uF1.0 pH

0.22 uF / pc300 pH / pc

Low InductanceCapacitor inOrganic PKG

LICOPTM

LIVACR



AC voltage drop simulation

Die

Main Board

V.R. LICOPDecuplingCapacitor

LICOP

LIVAC

DieV.R.

Current Substrate

Current SubstrateC/C

Main Board

DecuplingCapacitor



AC voltage drop simulation

Iload [A]

t0.55 nsec0

8

Vcc : Tr :

Max current : dI/dt :

NTK assumption

1 V0.55 nsec8 A14.5 A/nsec

Simulation input : die load current



Current Substrate(Inductance : 42.1pH)

AC voltage drop : 96mV AC voltage drop : 29mV

AC voltage drop waveform

Simulation software : Ansoft Designer

LICOP(Inductance : 2.0pH)

LICOP shows much lower AC voltage drop than current substrate due to its lower inductance. (ratio is about 30%)

Volta

ge

1.0

0.8

1.2

[nsec]40 800 20 60

[V]

100

1st drop = 96 mV

Volta

ge

1.0

0.8

1.2

[nsec]40 800 20 60

[V]

100

1st drop = 29 mV



100

50

0

150

200

250

Current Substrate(Inductance : 42.1pH)

LICOP(Inductance : 2.0pH)

Impedance profile simulation result

LICOP shows much lower Impedance peak than current substrate due to its lower inductance. (ratio is about 23%)


|Z|

100

50

01 10 100 1000

Freq [MHz]

[mΩ]

150

|Z|

01 10 100 1000

Freq [MHz]

Impedance peak43mΩ @ 302MHz

[mΩ]Impedance peak

187mΩ @ 135MHz

200

250



Electrical performance summary

LICOP Current Substrate

Capacitance 37.1 uF 3.5uF

Inductance 2.0pH 42.1pH

AC voltage drop(dI/dt = 14.5 A/nsec , VDD = 1 V) 29mV 96mV

Impedance peak 43mΩ(@302MHz)

187mΩ(@132MHz)

We confirmed that LICOP shows much better electrical performance due to its lower inductance.



Mechanical Performance



Mechanical warpage

-0.080-0.070-0.060-0.050-0.040-0.030-0.020-0.0100.000

0 6 12 18Diagonal distance from Center [mm]

War

page

[mm

]

-0.080

-0.060

-0.040

-0.020

0.000

0.020

0.040

0.060

0 6 12 18

War

page

[mm

]w/array capacitor : 18um

current: 30um

Warpage - Top of Die Warpage - Bottom of Substrate

Warpage of substrate is reduced by LICOP structure.

Diagonal distance from Center [mm]

Current: 71um

Top of Die

Bottom of Substrate

Die

LIVAC Condition: 220 25 deg. CDie Size : 11mm SQ.

(Simulation)

w/array capacitor : 19um



Warpage after under fill cure

Warpage of substrate is reduced by LICOP structure.It is same as simulation result.

War

page

(um

)

0

0.025

0.05

0.075

0.10

0.125

0.15

LICOP CurrentPKG structure

Warpage16um

Warpage71um

N=20

Warpage measurement results

Warpage

Substrate

Die

PKG Structure•Substrate size: 37.5mmSQ. x 0.8mmt

•Layer count: 4 / 2 / 4*12mmSQ. x 0.8mmt LIVAC embedded

in case of LICOP



Next step for mechanical investigationWe will conduct 1st level reliability performance comparison..

Input#1 : Substrate structure (LICOP vs control)• Temp cycle killer test • Visual observation• With dummy die attach

Input#2 : Core material properties • Ultra low CTE material effect



Reliability



Cond. B -55 - 125 deg.C x 500cycles

Cond. C -65 - 150 deg.C x 90cycles

0/20 unit NGCross sectionCond. A

0 – 100 deg.C x 4000cyclesT/C

(w/ Die)3

0/50 unit NGR shift

0/50 unit NGL shift

0/50 unit NGR shift

0/50 unit NGL shift

T/C(w/ Die)

2

0/50 unit NGIR shift130deg.C、85% R.H.

No bias x 96hr.HAST4

T/S(w/ Die)

1

ResultCheck itemCond.Item#

NTK test vehicle

Summary

Board

Die

PKGBGA ball

UF

LIVAC

Stiffener

Heat spreader

•LICOP 4 / 2 / 4 Structure•LIVAC Size: 12mmSQ. x 0.8mmt

•Core Substrate: 37.5mmSQ. x 0.8mmt



Board

Die

PKG

BGA ball

UF

LIVAC

Stiffener

Heat spreader

Substrate Structure•LICOP 4 / 2 / 4 Structure•LIVAC Size: 12mmSQ. x 0.8mmt

•PKG Size: 37.5mmSQ.•Core Substrate: 37.5mmSQ. x 0.8mmt

Cross Sectional Observation

Ball integrity

X100

Via integrity on LIVAC pad

LIVAC X1,000

Adhesion b/wLIVAC & molding resin

X500

Bump integrity

X500

LIVAC



Board

Die

PKG

BGA ball

UF

LIVAC

Stiffener

Heat spreaderSubstrate Structure



X500

1st. Level Connection Checkafter T/C-cond.A (0deg.C - 100deg.C) x 4000cycles

X500 X500

Checked 1540 bumps (77 bumps x 20 units) and no issue have been observed.

Left Center Right



Board

Die

PKG

BGA ball

UF

LIVAC

Stiffener




Via Integrity Checkafter T/C-cond.A (0deg.C - 100deg.C) x 4000cycles

Checked 80 vias (4 vias x 20 units) and no issue have been observed.

X500 X500 X500



Board

Die

PKG

BGA ball

UF

LIVAC

Stiffener




Adhesion Check b/w LIVAC & Molding Resinafter T/C-cond.A (0deg.C - 100deg.C) x 4000cycles

Checked 40 corner of LIVAC (2 corner x 20 units) and no issue have been observed.

X1000 X1000 X1000

LIVAC LIVAC LIVAC

Moldingresin

Moldingresin

Moldingresin



Board

Die

PKG

BGA ball

UF

LIVAC

Stiffener




2nd. Level Connection Checkafter T/C-cond.A (0deg.C - 100deg.C) x 4000cycles

Checked 920 balls (46 balls x 20 units) and no issue have been observed.

X100 X100 X100

Left Center Right



SummaryDeveloped Hybrid structure organic substrate with ceramic via array capacitor inside.

Electrical investigation1. Confirmed advantage on low-L decoupling capacitor. 2. Simulation indicated system level noise can be reduced significantly. 3. Z peak also could reduced.

Mechanical investigation1. Simulation indicated warpage can be reduced by hybrid structure.2. Confirmed good reliability performance including 1st and 2nd

connection.



Next stepLICOP is ready for customer evaluation. It has been tested

in various condition, and proven reliability and performance.

Develop low cost solution to utilize LICOP substrate formiddle/low end products. (Ex. Standardize array cap size)



Back Up



AC Voltage Drop Wave Form

1st Drop : AC voltage drop(caused by Substrate inductance)

Stable Area(caused by Substrate resistance)

2nd Drop (caused by Substrate capacitance)

Idie

tVdie[ V ]1.0



Core Die modelMain BoardVR Substrate model

Equivalent Circuit Model for Voltage Drop Analysis

0mΩ

1.0V

Cdie

Rdie Iload

L

vr

Rbrd

Ldecap

Rdecap

Cdecap400uF

0.1mΩ

30pH

60pH 0.2mΩ

V

R

VDD

0pH

1.0V

GNDGND

VSS VSS

VDD VDD

2 portS-parameter

Model( Port2 )( Port1 )

(1.0V)


L

vr

vr

brd



AC Voltage Noise Analysis

AC voltage drop is proportional to dI/dt up to 100 [A/nsec].In each dI/dt condition, AC voltage drop ratio of LICOP substrate compared to current substrate is the same value such as 30%.



Impedance Profile Overview

Z0(f) : On Die Capacitor (only capacitance curve)Z1(f) : On Substrate Capacitor

(Current Substrate : LSC mounted , LICOP : LIVAC embedded)Z2(f) : Mid-Frequency Capacitor on MBZ3(f) : Bulk Cap on MB

|Z|

freq

Z2(f)

Z3(f)

Z1(f)

Z0(f) Impedance peak(cross point of Z0(f) and Z1(f) )

Capacitance curve of die capacitor

Inductance curve of Substrate capacitor

Mag

nitu

de

Board capacitance curve Substrate capacitance

curveDie capacitance

curveOverall PD Impedance (Impedance Profile)



(Agilent 8753ES)

Measurement ProbeCascade Microtech

ACP40-GS-250,ACP40-SG-250

Measurement Frequencystart : 30kHz , stop : 6GHz

Network Analyzer

Gore cable

Air Coplanar probe

LICOP

Measurement Padprobing one Vdd bump and

one Vss bump

ESL is extracted frommeasured S-parameter

Electrical Measurement System of LICOP Substrate ESL



@1GHz

Measurement and Simulation Resultsof LICOP Substrate ESL

Simulation2( To probe all VDD bumps

and all VSS bumps )

Simulation1( To probe one VDD bump

and one VSS bump )

Measurement result( To probe one VDD bump

and one VSS bump )

74.9 pH

ESL (pH)

2.0 pH

ESL (pH)

73.8#3

72.7#4

75.6#5

75.3 pH

78.5

75.8

ESL (pH)

Average

#2

#1

Sample #



LIVAC Back Up



Cu-post for Reliability on Via Connection

There is thk gap b/w core substrate and LIVAC because of thk variation and warpage of them. This gap causes issue on via process capability and connectivity.

Our LIVAC can have Cu-post on BGA side in order to eliminate the thk gap. Cu via

LIVAC

50um

Cu-post

50um

Void

LIVAC

Cu via

Issue on via connectivity

NTK solution: Cu-post

Cu post



3 – 15 mm

0.5 – 1.0 mmt

Dielectrics(BaTiO3-based)

Permittivity: ~ 3,000

Ni inner electrode

Ni outer electrode

Cu plating (20 umt)

Ni-based viaDia.: 90 – 110 umResistivity: 14 x 10-6 ohm cm

Min. 350 um

Min. 500 um

< Typical electrical properties >

C: 20 – 40 uF/cm2 (*)L: ~ 1 pH.cm2

* Depending on LIVAC thk.

Typical LIVAC Design and Properties



3.6 x 3.6 5 x 5 8 x 8 10 x 10 12 x 12 24 x 24(under development)

Can connect to plural pwr nets.

Taylor-made LIVAC

Various size and design

Plane (pwr) division

LIVAC has flexibledesign capability andcan be customizedindividually.



+ - + -

In via array type, the loop inductance canceling effect caused by mutual inductance of current flow is much larger.

+ -Current flow

Via Array TypePeripheral Array Type

Mutual inductance effect



Electrode Peripheral array type Via array type

Size (mm) 3.2 x 1.6 2.0 x 1.25 ~ 10 x 10

Pad # 2 8 265

Out view

L [pH/pcs] 200 110 1.0

C [µF/pcs] 2.2 2.2 10.0

L [pH/cm2] 10.2 2.8 1.0

C [µF/cm2] 43 88 35

Comparison of inductance

tm low inductance capacitor in organic...

Documents