timings training 2005/03/15 bca158 kobe nieh 6793 foxconn confidential1
TRANSCRIPT
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Timings Training2005/03/15
BCA158
Kobe Nieh 6793
FOXCONN CONFIDENTIAL 1
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Outline• Preface
• Input Set-up time, Input Hold-time, Delay time
• Timing Verification Example
• Examples of Real Interfaces
FOXCONN CONFIDENTIAL 2
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Preface
FOXCONN CONFIDENTIAL 3
• This training provides some technical background on the timing-aspects of a digital interface.It describes the basic concepts of the timing-verification, point of interest and some example of real interfaces.
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Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 4
• Overview Digital Interface
• The digital interface between IC A and IC B is a synchronous interface and consists of 3 signals.
– IC A drives the clock (CLK). (IC A output the clock, the CLK is an input of IC B)
– IC A drives Data1. (Data1 is outputted by IC A, and is an input to IC B)
– IC B drives Data2. (Data2 is outputted by IC B, and is an input to IC A)
CLK
Data1
Data2
IC A IC B
CLK out CLK in
Dout Din
Din Dout
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• Delay Time
• The datasheet of IC A will specify the delay-time (Tdelay, A, Data1) between the rising edge (or falling edge) of the clock (CLK), which is also outputted by IC A, and a change in the Data1 signal (rising or falling edge).
• The datasheet of IC B will specify the delay-time (Tdelay, B, Data2) between the rising edge (or falling edge) of the clock (CLK), in this case the CLK is an input to IC B, and a change in the Data2 signal (rising or falling edge).
• In some cases (e.g. utopia interfaces) the output delay time will be specified as “minimum hold time” and data “valid time” .(just a different naming)
Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 5
CLK
Data1
Data2Tdelay, A, Data1
Tdelay, B, Data2
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• Delay Time
• The datasheet of IC A and IC B will specify a delay between a maximum and a minimum value.
• This means that the Data-signal (Data1 and Data2) will always be put on the line after Tdelay (min) but always before Tdelay (max).
• E.g. : Tdelay, A, Data1 (min,max) = (9ns, 15ns)
Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 6
CLK
Data1
Data2Tdelay, A, Data1
Tdelay, B, Data2
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• Input Set-up Time, Input Hold Time
• An Input set-up time is a requirement. This means that the signal that is inputted to a chip needs to be stable Tsu time before the rising edge of the clock on which it is sampled.
• An Input hold time is a requirement. This means that the signal that is inputted to a chip needs to be stable at least Th time after the rising edge of the clock on which it is sampled.
• The (Input) set-up time requirement and the (Input) hold time requirement can be found in the datasheet of the chip where the signal is inputted.
Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 7
CLK
Data1
Data2Tsu. B. Data1
Tsu. A. Data2 Th. A. Data2
Th. B. Data1
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• Timing Verification Example
• Datasheet A mentions the following:– CLK (output) : period = 30ns
– Data1 (output) : T delay (min,max) = (6,8)
• Datasheet B mentions the following:– Data1 (input) : Tsu(min) = 10
– Data1 (input) : Th(min) = 7
Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 8
CLK
Data1
Data2
30ns
Tdelay, A, Data1
Tdelay, A, Data1
Tsu. B. Data1
Th. B. Data1
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• Timing Verification Example
• Data1:– Setup-time requirement : (Tsu, B, Data1)
– Tsu = 30ns – max delay Tdelay, A, Data1
– Tsu = 30 – 8 = 22ns
– Tsu = 22ns > Tsu, B, Data1 = 10 ns Ok
– Hold-time requirement : (Th, B, Data1)
– Th = min. delay Tdelay, A, Data1
– Th = 6ns < Th, B, Data1 =7ns Not OK
Input Set-up Time, Input Hold Time, Delay Time
FOXCONN CONFIDENTIAL 9
CLK
Data1
Data2
30ns
Tdelay, A, Data1
Tdelay, A, Data1
Tsu. B. Data1
Th. B. Data1
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 10
• Synchronous Interface : SDRAM (IC42S324000-7T)
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 11
CPU SDRAM
1. Command from CPU
2. Address from CPU
3. SDRAM delay 3 clock latency
4. Data from SDRAM
• Synchronous Interface : SDRAM (IC42S324000-7T)– Reading Process
• SDRAM parameter:– System CLK =100Mhz from CPU– T (1 Cycle) = 10ns – CL= 3 cycle CLK latency
• CPU parameter:– T delay (max, min) = (6.8ns, 2ns)
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 12
• Synchronous Interface : SDRAM (IC42S324000-7T)– Reading Process
• Reading Command and Address from CPU to SDRAM:
– 1. SDRAM is synchronous interface, so all signals will refer to “CLKIN1” to define setup time and hold time. Therefore, we can assume the setup & hold time of CLKIN1 as 0.
– 2. T –= 10-6.8 = 3.2 .
– 3. R=31ohm, C=4pF, RC(delay) = 0.124ns. For EMI solution, we must consider the worst case.
– 4. Trace length = 3cm , 3cm / (3*108m*ε) 0.102ns. But according to our ≒experience, the delay time on 6mil trace is 0.14~0.15ns/inch, so we use 0.15ns to simulate it.
CPUP300
SDRAMICSIStage1
RC delayStage2Trace delay
1. Command from CPU
2. Address from CPU
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 13
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 14
CPUP300
SDRAMICSIStage1
RC delayStage2Trace delay
• Synchronous Interface : SDRAM (IC42S324000-7T)– Reading Process
• Data output from SDRAM to CPU
– T - Tac = 10 – 5.5 = 4.5ns
– Toh = 2.5ns
– Trace length = 3cm , 3cm / (3*108m*ε) 0.102ns. But according to our ex≒perience, the delay time on 6mil trace is 0.14~0.15ns/inch, so we use 0.15ns to simulate it.
Data from SDRAM to CPU
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 15
• Synchronous Interface : SDRAM (IC42S324000-7T)– Reading Process
• Data output from SDRAM to CPU
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 16
• Synchronous Interface : SDRAM (IC42S324000-7T)– Reading Process
• Timing Diagram:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 17
• Synchronous Interface : SDRAM (IC42S324000-7T)– Writing Process
• Timing Diagram:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 18
• Synchronous Interface : SDRAM (IC42S324000-7T)– Writing Process
• SDRAM parameter:– System CLK =100Mhz from CPU– T (1 Cycle) = 10ns – CL= 3 cycle CLK latency
• CPU parameter:– T delay (max, min) = (6.8ns, 2ns)
CPUP300
SDRAMICSI
1. Command from CPU
2. Address from CPU
3. Data from CPU
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 19
• Synchronous Interface : SDRAM (IC42S324000-7T)– Writing process timing analysis
– 1. SDRAM is synchronous interface, so all signals will refer to “CLKIN1” to define setup time and hold time. Therefore, we can assume the setup & hold time of CLKIN1 as 0.
– 2. T –= 10-6.8 = 3.2 .
– 3. R=31ohm, C=4pF, RC(delay) = 0.124ns. For EMI solution, we must consider the worst case.
– 4. Trace length = 3cm , 3cm / (3*108m*ε) 0.102ns. But according to our ≒experience, the delay time on 6mil trace is 0.14~0.15ns/inch, so we use 0.15ns to simulate it.
CPUP300
SDRAMICSI
Stage1RC delay
Stage2Trace delay
1.Command and address from CPU
2. Data from CPU
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 20
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 21
• Asynchronous Interface : Flash (MX29LV320ABTC-90) – The signals of an asynchronous interface are not necessarily reference to a clock.– In an asynchronous interface, set-up time, hold time and delay time will be refer
enced to the rising or falling edges of other signals than clock.– A flash Read-access is a special case in the asynchronous interfaces. For Read a
ccesses the address does not get latched in (flip-flops). That is why you will not find any setup and hold time requirements for the address and OE. [In other interfaces, the address will be sampled (flip-flop latch) on the falling edge of the OE(=Rd)]
– For timing verification of Read-access that the data will be valid on the Flash data bus after
• Tacc-time the address is atable• Toe-time the OE-signal is low• Tce-time the CE-signal is low
– The requirement of the flash for a Read-access:• Trc (minimum address width requirement from the flash)• Toeh (time between WE high and OE low (=next access))
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 22
• Asynchronous Interface : Flash (MX29LV320ABTC-90) – A Flash Write-access look more like a general asynchronous interface. Here, t
he address is latched-in (flip-flops) into the flash on the falling edge of WE.
– In addition you will find some setup and hold time requirements for the data (Writedata is inputted to the flash) : Tds and Tdh. This data is latched-in (flip-flops) on the rising edge of the WE.
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 23
• Asynchronous Interface : Flash (MX29LV320ABTC-90)
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 24
CPUP300
FLASHMX29LV320
1. Command from CPU
2. Address from CPU
3. Flash delay timing “tOE”
4. Data from FLASH
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 25
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
• Command and address timing simulation:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 26
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
• Data output timing simulation:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 27
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
• Timing diagram: The rise-edge of CE, OE and address signals are at the same time in the following timing diagrams.
– OE signal for read command:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 28
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
• Timing diagram: The rise-edge of CE, OE and address signals are at the same time in the following timing diagrams.
– CE signal for read command:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 29
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Reading process
• Timing diagram: The rise-edge of CE, OE and address signals are at the same time in the following timing diagrams.
– Address signals for read command:
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 30
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Writing process
CPUP300
FLASHMX29LV320
1. Command from CPU
2. Address from CPU
3. Data to FLASH
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 31
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Writing process
• Writing process timing analysis
• Command and address timing simulation
CPUP300
FLASHMX29LV320Stage1
Trace delayStage2RC delay
1. Command and address from CPU
2. Data from CPU to FLASH
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Examples of Real Interfaces
FOXCONN CONFIDENTIAL 32
• Asynchronous Interface : Flash (MX29LV320ABTC-90)– Writing process
• Command and address timing simulation