The Design and Linearization of 60GHz

Injection Locked Power Amplifier

A Thesis Presented by

Luhao Wang

A Thesis Submitted toLund University

in Partial Fulfillment of the Requirements forthe Degree of Master of Science

in Electrical EngineeringAugust 2016, Lund, Sweden

Supervisor: Leijun XuExaminer: Prof. Henrik Sjöland

Keywords: Power Amplifier, Injection-locking, Adaptive biasing, Predistortion

I

Abstract

The RF power amplifier is one of the most critical blocks of transceivers, as it is

expected to provide a suitable output power with high gain, efficiency and linearity.

In this paper, a 60-GHz power amplifier based on an injection locked structure is

demonstrated in a standard 65 CMOS technology. The PA core consists of a cross-

coupled pair of NMOS transistors with an NMOS current source. This structure can

achieve large output power and high PAE, but with poor linearity performance. In

order to improve the linearity, several linearization techniques are investigated,

including adaptive biasing and predistortion. The results show that the adaptive

biasing technique can enlarge the linear operation region, but results in poor AM-PM

performance. By instead using the predistortion technique, the AM-PM performance

can be improved, but the linear region only extends slightly. Considering theses two

techniques different advantages, we combine them together to improve not only the

linear region but also the AM-PM performance.

Finally, a common source amplifier is added as the first stage. With proper bias, the

linear operation region is then effectively extended by 7.3 dB. This two stage power

amplifier achieves large output power, high linearity and high PAE simultaneously. It

delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.

II

Acknowledgements

|I would like to take this opportunity to express my gratitude to all those who gave

me a lot of supports during this master thesis.

First of all, I am greatly indebted to Professor Henrik, who has offered my valuable

instructions and suggestions in the academic studies.

I would also gratefully acknowledge the help of my supervisor Xu Leijun, for his

constant encouragement and guidance. Without his patient instruction and expert

guidance, it is impossible for me to complete this thesis.

I also feel grateful to all the teachers and classmates in Lund University. I learned a

lot form all of you.

Finally, I would like to express my gratitude to my beloved parents and girlfriend

who have always been helping me out or difficulties and supporting without a word of

complaint.

III

Contents

Abstract........................................................................................................................................i

Acknowledgements ....................................................................................................................II

Contents ....................................................................................................................................III

Chapter 1 Introduction ................................................................................................................1

1.1 Motivation for 60 GHz CMOS Power Amplifiers ...............................................................1

1.2 About this thesis work ..........................................................................................................4

1.3 Organization .........................................................................................................................4

Chapter 2 RF Power Amplifier Basics .......................................................................................5

2.1 Introduction...........................................................................................................................5

2.2 Performance metrics of power amplifiers.............................................................................5

2.2.1 Power gain and Bandwidth .........................................................................................6

2.2.2 Stability.......................................................................................................................6

2.2.3 Power Efficiency ........................................................................................................8

2.2.4 Linearity......................................................................................................................9

2.3 Class of PA operation .........................................................................................................12

2.3.1 Linear power amplifiers...............................................................................................12

2.3.1.1 Class-A Power amplifier........................................................................................13

2.3.1.2 Class-B Power Amplifiers .....................................................................................15

2.3.1.3 Class-AB Amplifier ...............................................................................................16

2.3.1.4 Class-C Amplifier ..................................................................................................17

2.3.2 Switching-mode PA..................................................................................................18

2.3.2.1 Class-D PA ............................................................................................................19

2.3.2.2 Class-E Power Amplifier .......................................................................................20

2.3.2.2 Class-F Power Amplifier .......................................................................................22

2.3.3 Summary......................................................................................................................23

2.4 Linearization of RF power amplifier ..................................................................................24

IV

2.4.1 Power backoff ...........................................................................................................24

2.4.2 Feedforward..............................................................................................................25

2.4.3 Feedback linearization ..............................................................................................26

2.4.4 Predistortion..............................................................................................................27

Chapter 3 Power Amplifier Design ..........................................................................................28

3.1 Power Amplifier specifications .......................................................................................28

3.2 Injection locked power amplifier technique ....................................................................28

3.3 Circuit design...................................................................................................................30

3.4 Balun design ....................................................................................................................32

3.5 PA Simulation Results ........................................................................................................37

Chapter 4 Power Amplifier Linearization ................................................................................40

4.1 Adaptive biasing technique..............................................................................................40

4.2 Pre-distortion technique...................................................................................................45

4.3 Two-stage PA ..................................................................................................................52

Chapter 5 Conclusion and the future work ...............................................................................56

Reference ..................................................................................................................................58

1

Chapter 1

Introduction

1.1 Motivation for 60 GHz CMOS Power Amplifiers

Since the invention of radio-frequency (RF) wireless communication more than 100

years ago, mobile phones and other wireless communications products for civilian

consumption have developed rapidly, especially in recent years. From the view of the

personal mobile communication, the personal-oriented commercial mobile

communication technology has expanded from Advantage mobile phone system

(AMPS) to today’s Time division long term evolution (TD-LTE), Frequency division

duplex long term evolution (FDD-LTE) and so on. As another application for wireless

communication, the accessing technology of broadband network is developing rapidly

and it becomes a very active area. In recent years, new technologies are constantly

emerging such as Bluetooth, Ultra wideband (UWB), Radio frequency identification

devices (RFID) and Near field communication (NFC). There are two developing

trends: one is towards low power consumption, including the RFID and NFC

technologies; another is towards high bandwidth such as UWB technology.

Nowadays, with the rapid development of the communication system, the demand

for larger volume and high data rate also rises sharply. The traditional wireless

bandwidth is no longer able to meet some high-rate applications requirement. Based

on Shannon’s theorem, the maximum possible date rate of the communication channel

is given by:

) (1. 1)𝐶 = 𝐵𝑊𝑙𝑜𝑔2(1 + 𝑆𝑁

Where C is the maximum possible data rate, BW is the bandwidth of the channel, S

is the total received power over the bandwidth, and N is the total noise power. It is

obvious that the maximum data rate increases with increasing channel bandwidth.

2

Nowadays, the spectrum around 60GHz is available in various region over the world

shown in Table 1. This available spectrum can enable a huge channel bandwidth

(2500 MHz) compared to other wireless communication standards. Hence, it will take

tremendous push function to the development and expansion. The 60GHz-band short-

distance communication technology has become the hot topic of applied research. An

enormous amount of research effort goes into designing mm-wave CMOS circuits for

the up to 7 GHz unlicensed wide band around 60GHz and it brings not only

opportunities but also challenges.

However, the free-space loss in 60 GHz band is high due to the oxygen absorption.

This limits the maximum distance of communication. While this limit distances also

offers interference and security advantages which make 60GHz band has prevailed for

short-range, high data rate and high security wireless communication[1][2][3].

The 60Ghz band is developing under the IEEE standard 802.15.3c, 802.15.11ad,

and the European Computer Manufacturers Association (ECMA) standard 387. And

there are a lot of usages for communication at the band, such as the wireless personal

area networks (WPANs) and wireless local area networks (WLANs). The application

areas is including borne radar, cordless telephone, military use, medical endoscopes,

high-definition TV (HDTV) and so on.

Region Low frequency High frequency Bandwidth

USA 57 GHz 64 GHz 7 GHz

Canada 57 GHz 64 GHz 7 GHz

Europe 57 GHz 66 GHz 9 GHz

Japan 59 GHz 66 GHz 7 GHz

Australia 59.4 GHz 62.5 GHz 3.1 GHz

Table 1. Allocation of spectrum around 60 GHz in the various region around the world[4]

Traditionally, technologies based on SiGe and III-V semiconductor are widely

used in millimeter-wave circuits and communication system. A direct advantage is

that the high power gain and output can be achieved, and solve the signal attenuation

3

problem in such a high frequency band. However, its obvious disadvantage is the high

cost manufacturing and low integration. This greatly limits the mass production and

integration in system level and it can’t realize the real SOC(system on chip). Hence,

CMOS technology due to feasibility, low cost, low power consumption and high

integration has become a trend. Moreover, with the increasing technological

sophistication, the maximum frequency of operation ( ) for the 90nm technology fT

node is above 100GHz and it continues to increase for smaller nodes. The continuous

progress of the CMOS technology make it possible for the millimeter wave

communication system.

As we have seen, the RF power amplifier as the last building block before the

antenna is critical for wireless communications system. In order to achieve high data

rate, some complex digital modulation schemes are needed, which require highly

linear transmitter to minimize both error vector magnitude (EVM) and spectral

regrowth[5][6]. At the same time, the power amplifier contributes the most of power

consumption of the whole transceiver, which means the efficiency of the power

amplifier is significant, it directly determines the quality of the whole system. Besides

the efficiency and linearity, the size, gain, output power level are also very important.

However, it is impossible to maximize all the design criteria at the same time, some

tradeoffs should be made.

Moreover, the power amplifier design realized by CMOS process at millimeter

wave faces great challenges, such as the low breakdown voltage, parasitic capacitance

and limited gain due to the low transconductance. And with the dimensions of the

CMOS scaling down, the supply voltage dropping results in the low output power and

bad performance as well. For example, with the breakdown voltage dropping, the

supply voltage decreases. In order to maintain the same power as before, the current

has to be increased. The increased current will result in reduction of the gain and

efficiency due to the parasitic resistor; Moreover, to obtain larger DC current, we

need to increase either the amplitude of the input signal or size of the transistor.

4

However, this will reduce the gain and much more parasitic capacitance will be

introduced.

1.2 About this thesis work

This thesis is carried out at the Department of information and Electrical

Technology (EIT) at Lund University. The main objective of this thesis project is to

design a 60 GHz-Band injection locked power amplifier and increase linearity while

maintaining the power gain and efficiency. In this thesis, all the circuits are designed

by using the STM 65nm CMOS process.

1.3 Organization

This chapter provides a background based on RF wireless communication system at

60 GHz band frequency, and poses the motivation for CMOS power amplifier.

Chapter 2 reviews the basic structure and performance metrics of RF power

amplifier. And different classes of power amplifiers are discussed as well.

Chapter 3 introduces a power amplifier based on the injection locked structure and

explain its principle of operation.

Chapter 4 describes the linearization theory; several techniques are used to extend

the linear operation. And the simulation results of each techniques are described and

analyzed.

Chapter 5 summarizes the thesis and further work is also discussed.

5

Chapter 2

RF Power Amplifier Basics

2.1 Introduction

RF power amplifier is widely used in the wireless communication system. It is used

to provide the output signal at a desirable gain with high linearity and efficiency. It

should fulfill the output power requirement, which is the greatest different from

small-signal amplifier. Due to the high power output, the transistor normally operates

in large-signal model, and non-linear phenomenon is obvious. The characteristic of

RF power amplifier is low power and large current. In order to withstand large

current, the chip area must be increased. At the same time, parasitic capacitance and

resistance increases as well and it results in degraded operating frequency and

efficiency. Furthermore, the impedances of the input and output are complex number

and it is hard to perform impedance matching. In order to get maximum output power

and efficiency, the matching network is indispensable. A complete RF amplifier is

normally consists of input matching network, DC biasing circuit, transistor amplifier

circuit and output matching network. The basic block of RF power amplifier is shown

in Fig. 2.1.

Signal Source

Input Impedance Matching Network Core Circuit

Output Impedance Matching Network Load

Bias Circuit

Fig. 2. 1Basic block of RF power amplifier

6

2.2 Performance metrics of power amplifiers

Many metrics are used to evaluate the performance of power amplifiers. In this

section, some of the important metrics are discussed, such as the power gain,

efficiency and linearity.

2.2.1 Power gain and Bandwidth

Power amplifier is required to amplify the power of the input signal. Hence, the

level of the gain is power gain which is defined as the ratio of the output power

delivered to the load to the input power.

(2. 1)𝐺 = 𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝑙𝑜𝑎𝑑

𝑃𝑜𝑤𝑒𝑟 𝑎𝑡 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡 =𝑃𝑜𝑢𝑡

𝑃𝑖𝑛

If the input is sinusoidal signal and the load is a resistor, the power can be written

as:

𝑃𝑜𝑢𝑡 = 𝑣і

2 = 𝑣2

2𝑅 = і2𝑅2

(2. 2)

Where and are the amplitudes of voltage and current swing respectively. And 𝑣 і

for most of the case, the output impedance is equal to 50 Ω.

The power amplifier bandwidth is the range of frequency for which the PA can

obtain acceptable performance. Normally, it is defined as the frequency range for

which the corresponding gain can be maintained at least 0.7 times of the peak value

and is also called 3-dB bandwidth.

2.2.2 Stability

Stability is an important criteria that should be considered in power amplifier

design. This is important because oscillation is a highly undesirable phenomenon. In

such cases the amplifier performance may change strongly and it may lead to circuitry

damage.

7

Input Impedance Matching Network

Output Impedance Matching Network

Power Amplifier[ S ]

Zs

ZL

s Loutin

Fig. 2. 2 Block diagram of a one-stage PA

Fig.2. 2 shows the two-port system of power amplifier, Γ in and Γ out can be

expressed in terms of transistor S-parameters and reflection coefficients ( Γ S and Γ L )

as given:

(2. 3)

L

Lin S

SSS

22

211211 1

(2. 4)

S

Sout S

SSS

11

211222 1

Oscillations are possible when resistance at the input or output are negative. And

the power amplifier is unconditional stability when it meet the following conditions.

(2. 5)1S

(2. 6)1L

(2. 7)1

1 22

211211

L

Lin S

SSS

(2. 8)1

1 11

211222

S

Sout S

SSS

Another way to mathematically express the necessary and sufficient conditions

for unconditional stability is:

(2. 9)1

21

2112

2222

211

SSSS

K f

(2. 10)121122211 SSSS

8

2.2.3 Power Efficiency

Power efficiency is one of the most important PA performance metrics. It

measures the ability of converting the DC power to the RF power at the output. An

efficient PA will deliver most of the power drawn from the supply to the load. On the

other hand, power amplifier with low efficiency will result in high level of heat

dissipation. In the wireless transceiver, the power amplifiers are the most power-

consuming components. Hence, to preserve the battery lifetime, the efficiency of PA

is of great importance.

There are three definitions are commonly used: the drain efficiency, the power

added efficiency and the overall efficiency.

The drain efficiency of PA is defined as:

(2. 11)

Where PDC is the DC power supplied to the amplifier, and Pout is useful signal

power delivered to the load. The DC supply power can be written as:

(2. 12)DCDCDC IVP

An ideal PA has η=100%, which implies that the entire supply power is delivered

to the load. However, this is practically impossible to obtain. The drain efficiency

ignores the input power to the PA, and in most of case, especially the high-frequency

power amplifier, the overall power gain is low, the input power may become a

substantial portion of the output power. The results we got from this definition will be

higher than the real efficiency. In this case, the power added efficiency and the overall

efficiency will be introduced to provide a more accurate measure of PA performances.

Power added efficiency (PAE) is defined as:

(2. 13))11()11(

GPP

GPPP

PAEDC

out

DC

inout

Where Pin is the power of the input signal, and G is the overall power gain of the

DC

Outdrain P

P

9

PA. The power added efficiency is less than the drain efficiency, considering the input

RF power. If the power gain is higher than 20dB, the input power can be ignored and

at this time PAE is the same with drain efficiency. While the overall efficiency (

) is defined as:overall

(2. 14)

inDC

outoverall PP

P

To achieve a high efficiency, the power amplifier is always operated to a point near

its point of saturation. Unfortunately, at the same time, the distortion will occur.

Doherty amplifier circuit topology and Envelope-tracking power supply methods can

be employed to improve the efficiency without sacrificing linearity.

2.2.4 Linearity

Besides efficiency, linearity is another key parameter for evaluating the

performance of the power amplifier. For all the power amplifier, the relationship

between the input and output is non-linear, especially when the signal is large.

Assume the amplifier is a memoryless system, the transfer characteristic can be fit by

the third order function approximately.

(2. 15)𝑦(𝑡) = 𝛼1𝐴𝑐𝑜𝑠𝜔𝑡 + 𝛼2𝐴2𝑐𝑜𝑠2𝜔𝑡 + 𝛼3𝐴3𝑐𝑜𝑠3𝜔𝑡

If the input signal is sinusoidal waveform, , the output signal 𝑥(𝑡) = 𝐴𝑐𝑜𝑠(𝜔𝑡)

is:

𝑦(𝑡) = 𝛼1𝐴𝑐𝑜𝑠𝜔𝑡 + 𝛼2𝐴2𝑐𝑜𝑠2𝜔𝑡 + 𝛼3𝐴3𝑐𝑜𝑠3𝜔𝑡

(2. 16) =

𝛼2𝐴2

2 + (𝛼1𝐴 +3𝛼3𝐴3

4 )cos (𝜔𝑡) +𝛼2𝐴2

2 cos (2𝜔𝑡) +𝛼3𝐴3

4 cos (3𝜔𝑡)

where , and are the fundamental (𝛼1𝐴 +3𝛼3𝐴3

4 )cos (𝜔𝑡) 𝛼2𝐴2

2 cos (2𝜔𝑡)𝛼3𝐴3

4 𝑐𝑜𝑠(3𝜔𝑡)

component, second harmonics and third harmonics respectively. As we have seen,

because of its nonlinear characteristics, the amplifier not only amplifies the input

signal but also produce the harmonics. The amplification of the input signal is

10

. If A is small enough, the amplification approximately equals to 𝑎1 + 3𝑎3𝐴3/4 𝑎1

which is constant. This means the gain of the amplifier is constant and the amplifier

has a good linear behavior. However, as the input signal level increase, 3𝑎3𝐴3/4

becomes a substantial portion of this part, and the amplification drops, because , 𝑎3 < 0

( would mean that the amplifier oscillates, or that the quiescent point is close to 𝑎3 > 0

the breakdown voltage)[7]. This gain compression phenomena is also called AM-AM

distortion. And the concept of 1-dB compression point is proposed, which is defined

as the power level where the amplification is 1dB less than the linear gain. 1-dB

compression point is often used to measure the linearity of the amplifier and we can

obtain this by measurement of output vs. input power. (see Fig. 2. 3).

Out

put p

ower

(dBm

)

Input power (dBm)

1dBP1dB

1dB compression point

Non-linear region

linear region

Figure 2. 4 Output vs. input power and 1-dB Compression point

Besides the AM-AM distortion, the amplifier nonlinearity will also cause the AM-

PM distortion which is a phenomenon that the phase of the output depends on the

level of the input. The AM-PM distortion is caused by the parasitic capacitance

variation, especially the input gate capacitance. In other words, the output phase will

follow the level of the input signal due to the variability of the capacitance and due to

11

this distortion, the modulation schemes such as OFDM is badly affected.

When the amplifier has two input signals with the same amplitude and similar

frequency simultaneously, i.e. for . The output can be 𝑋𝑖(𝑡) = 𝐴cos 𝜔1𝑡 + 𝐴cos 𝜔2𝑡

calculated by submitting the input signal into the transfer characteristics equation.

𝑦(𝑡)= (𝛼1𝐴 + 9

4𝛼3𝐴3)𝑐𝑜𝑠𝜔1𝑡 + (𝛼1𝐴 + 94𝛼3𝐴3)𝑐𝑜𝑠𝜔2𝑡 + 3

4𝛼3𝐴3𝑐𝑜𝑠(2𝜔1 ‒ 𝜔2)𝑡 + 34𝛼3

𝐴3𝑐𝑜𝑠(2𝜔2 ‒ 𝜔1)𝑡 + 12𝛼2𝐴2𝑐𝑜𝑠2𝜔1𝑡 + 1

2𝛼2𝐴2𝑐𝑜𝑠2𝜔2𝑡 + …

(2. 17)

As can be seen, the output not only consists of the fundamental component

(frequencies , , their harmonics ( frequencies , , but also the result of 𝜔1 𝜔2) 2𝜔1 2𝜔2)

mixing of the input tones (frequencies , ). Except for the 2𝜔1 ‒ 𝜔2 2𝜔2 ‒ 𝜔1

fundamental parts, the additional signal are generated due to the PA nonlinearity. Of

all the possible intermodulation products, the third order intermodulation component

with the frequencies and are the most critical. Because they have 2𝜔1 ‒ 𝜔2 2𝜔2 ‒ 𝜔1

large amplitude and it is almost impossible to filter out as they are close to the carrier

frequencies and , and they can cause interference in multichannel 𝜔1 𝜔2

communication. The IMD3 increases as the input power increases, and it is a

theoretical point at which the desired output signal are equal to the third-order IM.

This theoretical points is the IIP3 and the corresponding output is OIP3. IP3 is also

widely used to evaluate the linearity of PA. A higher IP3 means lower distortion

generation and better linearity performance. Fig.2.5 shows the output spectrum

around the input tones, Fig.2.6 shows the third-order intercept point.

12

ω12ω1-ω2 ω2 2ω2-ω1

Out

put p

ower

(dBm

)

3ω1-2ω2 3ω1-2ω2

Fundamental components

IM5

IM3

IM5

Fig. 2. 5 shows the output spectrum around the input tones

Outpu

t pow

er (dB

m)

Input power (dBm)

OIP3

desired linear output

IIP3

IM3 product

Fig. 2. 6 The third-order intercept point

2.3 Class of PA operation

The power amplifier can be divided into two types: Linear amplifiers and

switching-mode amplifiers. Conventional linear amplifiers include Class-A, Class-AB,

Class-B, and Class-C amplifiers and the transistor acts as a current source. These

amplifiers can achieve high linearity with low efficiency. Switching-mode

amplifiers include Class-D, Class-E, and Class-F amplifiers and the transistor acts as a

switch. Theses amplifiers can achieve high efficiency at the price of linearity.

13

2.3.1 Linear power amplifiers

For the linear power amplifiers, the output signal is a linear function of the input

signal. Class-A, Class-AB, Class-B and Class-C amplifiers can be seen as linear

amplifiers and they have almost the same configuration which is shown in Fig 2.7.

DC blocking capacitor

Vdd

Vout

Vin

RF choke

Rload

Fig. 2. 7 Typical configuration of class-A power amplifier

This circuit consists of a transistor, a RF choke, a DC blocking capacitor, a

parallel LC tank and the load. The transistor remains in saturation region is used as a

current source, driving a controlled current into the load network, and this current has

the same shape with the input signal. The RF choke is a large inductor which provides

the constant DC current to the transistor and also prevent the AC signal leaking into

the supply. DC blocking capacitor blocks the DC current flowing into the load. The

parallel LC tank tuned to be resonant at the fundamental frequency is used to filter out

the out-of-band emission result from the non-linearity of the transistor[8][9].

2.3.1 .1 Class-A Power amplifier

Class-A power amplifier is the simplest, but has the highest linearity power

amplifier over the other classes of operation. And it is similar with the small-signal

amplifier. The main difference is the signal current in the small-signal amplifier is

14

small, it can’t affect the biasing condition. But in power amplifier, in order to

maximize the efficiency, the signal current may become a substantial portion of the

biasing current and thus the certain distortion is inevitable.

t

t

t

V0

VD

ID

Vdd

IDC

0

Fig. 2. 8 Voltage and current waveforms of an ideal class-A power amplifier

Class-A power amplifier achieve high linearity at the cost of efficiency. We

can analyze the efficiency quantitatively, assuming that the power amplifier is

perfectly linear, and the input is sinusoidal. The drain current of the transistor consists

of the quiescent current and the signal current.

(2. 18)𝐼𝐷𝑆(𝑡) = 𝐼𝐷𝑆,𝑄 + і𝑑𝑠𝑖𝑛𝜔0𝑡

Where IDS,Q is the quiescent current, is the amplitude of the signal current swing і𝑑

and is the signal frequency. The output voltage equals the signal current times load 𝜔0

resistance.

(2. 19)𝑉0(𝑡) =‒ і𝑑𝑅𝑠𝑖𝑛𝜔0𝑡

The corresponding drain voltage consists of the DC voltage and signal voltage.

(2. 20)𝑉𝐷𝑆(𝑡) = 𝑉𝑑𝑑 + 𝑉0(𝑡) = 𝑉𝑑𝑑 ‒ і𝑑𝑅𝑠𝑖𝑛𝜔0𝑡

The current and voltage waveforms is shown in Fig 2. 8. It is obvious that both the

current and voltage on the transistor are large than zero during the entire period,

which means the transistor dissipates power all the time.

15

The drain efficiency of the amplifier is:

(2. 21)𝜂𝑑𝑟𝑎𝑖𝑛,𝑚𝑎𝑥 =

𝑃𝑜𝑢𝑡

𝑃𝐷𝐶=

12і𝑑

2𝑅

𝑉𝑑𝑑𝐼𝐷𝑆,𝑄=

і𝑑𝑅

2𝑉𝑑𝑑= 50%

The class-A amplifier is the most linear amplifier and have the highest gain.

However, its biggest disadvantage is the ideal maximum efficiency of 50%., and any

loss will further reduce its efficiency. In addition, the peak voltage across the

transistor of 2Vdd is large. Therefore, the class-A amplifier is usually used in

applications requiring high linearity, high gain, high-frequency operation.

2.3.1.2 Class-B Power Amplifiers

In order to increase the efficiency, the concept of the conduction angle is proposed.

The idea is to bias the transistor with low quiescent voltage and the transistor

conducts only for part of the cycle. In other words, the voltage waveform is the same

as class-A amplifier, but the current waveform has a period time during which the

current is equal to zero. And when it occurs, the voltage always gets the maximum

value, so this technique can increase the efficiency obviously.

For the class-B amplifier, the conduction angle is π, meaning the transistor

conducts only half of the period. The waveform of the drain voltage and current is

shown in Fig. 2.9.

t

t

VDS

IDS

Vdd

t

Vin

Vth

T/2 T

16

Fig. 2. 9 Voltage and current waveforms of an ideal class-B power amplifier

As we can see, the drain voltage waveform is the same as class-A amplifier, the

drain current clipping occurs when the input signal level is less than the threshold

voltage, and it can be written by:

(2. 22)𝐼𝐷𝑆(𝑡) = {і𝑑𝑠𝑖𝑛𝜔0𝑡, 𝑖𝑓 0 < 𝜔𝑡 < 𝜋

0, 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒 �

The fundamental current is shown as below:

(2. 23)𝑖𝑓𝑢𝑛𝑑 = 2𝑇∫𝑇/2

0 і𝑑(𝑠𝑖𝑛𝜔0𝑡)(𝑠𝑖𝑛𝜔0𝑡)𝑑𝑡 =і𝑑

2

The output voltage equals to the current times resistance:

(2. 24)𝑉0 =і𝑑

2𝑅𝑠𝑖𝑛𝜔0𝑡

Since , from the equation above we can get the maximum value for 𝑉0 ≤ 𝑉𝑑𝑑 і𝑑

(2. 25)і𝑑𝑚𝑎𝑥 =2𝑉𝑑𝑑

𝑅

And the average drain current can be calculated as:

(2. 26) і𝑑 = 1

𝑇∫𝑇0𝐼𝐷𝑆(𝑡)𝑑𝑡 = 𝜔

2𝜋∫𝜋𝑤0і𝑑𝑠𝑖𝑛𝜔0𝑡 𝑑𝑡 =

і𝑑

𝜋 =2𝑉𝑑𝑑

𝜋𝑅

The maximum output voltage swing is Vdd, so the maximum output power is:

(2. 27)𝑃𝑜,𝑚𝑎𝑥 =𝑉 2

𝑑𝑑

2𝑅

The DC power is given by:

(2. 28)𝑃𝐷𝐶 =2𝑉 2

𝑑𝑑

𝜋𝑅

Thus, the maximum efficiency of the class-B amplifier is:

(2. 29)𝜂𝑚𝑎𝑥 =

𝑃𝑜,𝑚𝑎𝑥

𝑃𝐷𝐶= 𝜋

4 = 0.785

As we have seen, class-B amplifier is much more efficient than class-A amplifier,

and its maximum efficiency reaches to 78.5%. However, the linearity is worse, and

harmonic distortion will occur. Hence, the filter is necessary to eliminate the

harmonics. In other words, the class-B amplifier can achieve increased efficiency at

the cost of reduced linearity.

17

2.3.1.3 Class-AB Amplifier

The class-AB amplifier is a compromise between class A and class B amplifier in

terms of efficiency and linearity, and it has a conduction angle of The 𝜋 < 𝜃 < 2𝜋.

maximum drain efficiency is between 50% and 78.5% and the linearity is also

between class-A and class-B. The corresponding waveforms are shown in Fig. 2.10.

t

t

VDS

IDS

Vdd

t

Vin

Vth

Fig. 2. 4 Voltage and current waveforms of an ideal class-AB power amplifier

2.3.1.4 Class-C Amplifier

In the Class-C mode, the conduction angle is less than π, and the transistor

remains in the saturation region for less than half of the RF cycle. The overlapping

between the drain voltage and current decreases compared to the Class-A and Class-B

mode. However, due to the fixed maximum drain current, the amount of charge that

can be injected into the load also diminishes and the output power drops. In order to

maintain the output power level, the amplitude of input signal should be increased . In

other words, the overall power gain decreases as the conduction angle. Fig 2. 5 shows

the voltage and current waveforms of a Class-C PA.

18

t

t

VDS

IDS

Vdd

t

Vin

Vth

Figure 2. 6 Voltage and current waveforms of an ideal class-AB power amplifier

The maximum drain efficiency of the amplifier can be calculated from the

following equation:

(2. 30) 𝜂𝑚𝑎𝑥 = 1

4𝜃 ‒ 𝑠𝑖𝑛𝜃

sin (𝜃2) ‒ (𝜃

2)𝑐𝑜𝑠(𝜃2)

This equation can be also applied to all types of transconductance amplifiers.

Where is the conduction angle, which is 2π for class-A, π for Class-B, between π 𝜃

and 2π for Class-AB and less than π for Class-C.

Besides efficiency, the output power is related to the conduction angle, the

coefficient equation can be specified as:

(2. 31)𝑃𝑜𝑢𝑡 ∝ 𝜃 ‒ 𝑠𝑖𝑛𝜃1 ‒ 𝑐𝑜𝑠(𝜗/2)

It illustrates that the maximum efficiency of Class-C power amplifier is 100%.

However, there are several drawbacks for this PA. Firstly, it’s highly non-linearity,

and secondly, as the conduction angle approaches to zero, the output power delivered

to the load approaches to zero as well. Therefore, the Class-C power amplifier is only

suitable for the system with low power gain and linearization techniques are required.

2.3.2 Switching-mode PA

In contrast to linear power amplifier, where operation in the saturation region, the

19

switching-mode power amplifier is operated in the triode region in order to optimal

efficiency and output power. It is driven with a large amplitude input signal and the

transistor acts as a switch. During the ON-stage, the transistor can be modeled as a

small on-resistance and the voltage across it is zero and during the OFF-stage, the

transistor is cut off and the current is zero. In these amplifiers, the efficiency increases

by reducing the power dissipation. And we can achieve this by eliminating the drain

voltage and current overlapping time. Ideally, the switching-mode power amplifier

can achieve maximum 100% efficiency at the expense of linearity performance.

2.3.2.1 Class-D PA

Vdd

Vin

T1 M1

M2

C L

RL

T2

Vo

Fig. 2. 7 The basic configuration of Class-D power amplifier

The transformer coupled Class-D PA is shown in Fig. 2.12. The input transformer

M1 is used to convert the input signal to differential signal. The transistor M1 and M2

are driven by this differential input signal and turn on with no simultaneity. The series

LC tank is tuned to the operation frequency and it is used to remove the harmonic

components, so only fundamental signal can be delivered to the load. The waveform

of voltage and current is shown in Fig. 2.13.

Class-D PAs have some disadvantages. First of all, two transistors and transformers

are needed to implement and this introduces additional power losses. Secondly, in

20

high power and high frequency amplifiers, the devices are typically large in size, it

could result in a large output capacitance which cannot be ignored in practical design.

Furthermore, we assume that the transistors can be toggled between ON and OFF

stage instantaneously, unfortunately, it is hard to realize in practice.

t

t

ID1

Vo

t

VD1

2Vdd

Fig 2. 8 Voltage and current waveforms of an ideal class-D power amplifier

2.3.2.2 Class-E Power Amplifier

The basic configuration of Class-E power amplifier is shown in Fig 2.14.

Vdd

VoutVin

Rload

C2 L2

L1

C1

jXL

Figure 2. 9 The basic configuration of Class-E power amplifier

21

The transistor which is controlled by the input signal acts as an ON/OFF switch.

The inductor L1 prevent the AC signal flowing into the supply and provide the DC

current as well. L2 and C2 are designed to be a series LC resonator to filter out the

harmonics; The capacitance C1 consists of two parts, and the parasitic capacitance of

the transistor Cds is also taken into account. This means the power amplifier can

tolerate much larger parasitic capacitance, so the transistor with larger size can be

used to optimize the overall efficiency.

During the time when the switch is OFF, the current flowing into the transistor is

zero; when the switch is On, the voltage across the transistor is zero.

The waveform of class-E PA is shown in Fig. 2.15. It is seen that when the switch

is ON, the voltage across the transistor has already fallen to zero, and there is no

overlapping between the voltage and the current during operation. Class-E amplifier

can achieve maximum 100% efficiency. However, class-E PA has main drawback in

terms of peak voltage. The peak drain voltage is approximately 3.6Vdd, this limited its

application, especially in high frequency system.

t

t

t

Vin

Vds

Id

Fig. 2. 15 voltage and current waveforms of an ideal class-E power amplifier

22

2.3.2.2 Class-F Power Amplifier

The configuration of Class-F power amplifier is shown in Fig 2.16. This circuits

consists of a quarter-wave transmission line and a harmonic resonator. At the center

frequency, the resonator circuit can be seen open for fundamental frequency but short

for the other frequency and the impedance at the fundamental frequency is Rload. At

even harmonics, the quarter-wave transmission line leaves the circuit as a short

circuits and at odd harmonics, the short circuit is transformed into an open circuit.

The voltage and current waveforms of class-F power amplifier is shown in Fig.2.16.

It is capable of high efficiency and it can achieve maximum 100% efficiency, which

means the voltage and current waveforms do not exist simultaneously, as shown in

Fig.2.17. However, it is difficult to design the Class-F amplifier due to the complex

output-matching network.

Vdd

VoutVin

Rload

RF chock

C L

λ/4 @ ω0

Fig. 2. 10 The basic configuration of Class-F power amplifier

23

t

t

Vd

Vout

Id

t

2Vdd

Fig. 2. 11 voltage and current waveforms of an ideal class-F power amplifier

2.3.3 Summary

The performance comparison in terms of output power, gain, efficiency and

linearity for the different classes of power amplifiers is given in Table 2.1. As

mentioned before, linearity and efficiency are the opposite requirements in power

amplifier design. The efficiency of linear amplifiers decreases from Class-A to Class

C power amplifier, however, when moving from Class-A to Class-C power amplifier,

the power gain decreases and the amplifier trends to the higher nonlinearity. When

design the power amplifier, the linearity and efficiency should be trade-off between

the linear amplifiers and switching-mode amplifiers. While Class-A amplifiers are the

most linear power amplifier, which can achieve a maximum efficiency of 50%.

Switching-mode amplifier can achieve an ideal efficiency of 100%, but it is strongly

non-linear. We can start from the Class-A or Class-AB amplifier and try to find a way

to improve the efficiency, we can also choose the switching-mode configuration as

the starting point in order to obtain high efficiency, and then use some linearization

technology to improve the linearity[10].

24

Table 2. 1 Performances comparison for different classes of PAs

Class Mode ConductionAngle

OutputPower

Ideal Efficiency Gain Linearity

A 2π Moderate 50% Large Excellent

AB π～2π Moderate 50～78.5% Moderate Good

B π Moderate 78.5% Moderate Moderate

C

Current Source

0～π Small 78.5～100% Small Poor

D π Large 100% Small Poor

E π Large 100% Small Poor

F

Switch

π Large 100% Small Poor

2.4 Linearization of RF power amplifier

The nonlinear behavior of the RF front-end, especially RF transmitters, can

significantly degrade the overall performance of the wireless systems. The power

efficiency of an RF amplifier is optimal when it is operated near saturation. An

amplifier operating in this nonlinear range generates IM distortion that interferes with

neighboring channels. Therefore, there should be compensation for the nonlinearities

and distortions of the RF transmitter.

Linearization is a systematic approach to reduce an amplifier’s distortion which is

inevitable for enhancing the linearity of an amplifier to the high input power drive

levels and achieving linearity requirements when operating the device over its entire

power range. Linearization allows a PA to generate more power and operate with

higher efficiency for a given level of distortion[11][12] [13].

2.4.1 Power backoff

Power backoff is the simplest and most common linearization technique. It does not

make any changes to the circuit configuration, just shrink the input voltage.

Its main principle can be illustrated by using Taylor series:

𝐼𝑜𝑢𝑡 = 𝐼0 + 𝑎1𝑉𝑖𝑛 + 𝑎2𝑉𝑖𝑛2 + 𝑎3𝑉𝑖𝑛

3 + …

Where Iout is the output current, Vin is the input voltage and I0 is the bias output

25

current which can be easily blocked. As can be seen that, As the amplitude of input

signal decreases, the fundamental part becomes dominant term and the higher 𝑎1𝑉𝑖𝑛

order terms is no longer important as before. And 1dB reduction of the output power

results in 3dB reduction in IM3 and 2dB linearity improvement respectively.

However, this approach also has its drawbacks, Firstly, the system can achieve high

linearity performance at the price of the efficiency. Secondly, it cannot improve the

linearity performance any more beyond a certain range. Hence, for some high

linearity requirements circuit design, this technique is not sufficient, other

linearization techniques has to be employed.

2.4.2 Feedforward

The idea of the feedforward method is to extract and remove the distortion at the

output. Fig.2.18 shows the block diagram of the feedforward linearization method.

The system consists of main amplifier, auxiliary amplifier, attenuator, couplers,

combiner, and delay lines. The couplers is used to split the input signal into two paths,

the delay lines is used for phase-matching and better signal performance can be

achieved. The auxiliary amplifier is used to amplify the error signal.

delay

∑delay

∑A0

-

inV outV

A0

1/A0

Va

Vb

Ve

-

Vc

Fig. 2. 12 The basic block diagram of the feedforward linearization

Assuming that the nonlinear distortion signal can be seen as the sum of linear signal

26

and error signal.

𝑉𝑎 = 𝐴0𝑉𝑖𝑛 + 𝑉𝑑

The voltage of node b can be express as:

𝑉𝑏 =𝑉𝑎

𝐴0= 𝑉𝑖𝑛 +

𝑉𝑑

𝐴0

This error voltage can be get by using the comparator:

𝑉𝑒 = 𝑉𝑏 ‒ 𝑉𝑖𝑛 = 𝑉𝑖𝑛 +𝑉𝑑

𝐴0‒ 𝑉𝑖𝑛 =

𝑉𝑑

𝐴0

Error voltage is amplified by the auxiliary amplifier:

𝑉𝑐 = 𝐴0𝑉𝑒 = 𝐴0

𝑉𝑑

𝐴0= 𝑉𝑑

Then the amplified signal by main amplifier is combined with amplified error voltage in opposite phase.

𝑉𝑜𝑢𝑡 = 𝑉𝑎 ‒ 𝑉𝑐 = 𝐴0𝑉𝑖𝑛 + 𝑉𝑑 ‒ 𝑉𝑑 = 𝐴0𝑉𝑖𝑛

As we can see, the distortion is cancelled out theoretically. And this method is

inherently stable However, it is depend on accurate amplitude and phase matching,

and susceptible to drift and aging. Due to the losses of delay line, couplers and

auxiliary amplifier, the system is low power efficiency.

2.4.3 Feedback linearization

The block diagram of feedback linearization method is shown in Fig.2.19.

This method is based on the feedback loop, which is widely used in control theory.

The output signal is fed back via feedback loop and subtracted from the input signal.

If the gain is high enough, the local feedback can be used for linearization. However,

in RF communication system, the gain is hard-earned, this method suffers the

drawback of gain loss. Furthermore, the delay associated with the feedback loop will

make the system unstable and limit its use to narrowband signals[14][15].

27

+

Feedback loop

PA-

Input Output

Fig. 2. 19 The basic block diagram of the feedback linearization

2.4.4 Predistortion

The block diagram of predistortion technique is shown in Fig.2.20.

Predistorter PAInput Output

+ =

Input Input Input

Out

put

Out

put

Out

put

Fig. 2.20 The diagram of predistortion technique

As we known, at high power level, the power amplifier has gain compression

which leads to signal distortion. In order to address this issue, a predistorter which has

a transfer characteristic inverse to that of amplifier is introduced to the system. The

nonlinear gain compression of the power amplifier is compensated by this predistorter

and the 1 dB compression point is extended. The RF predistortion technique is widely

used in academia community since it has a simple structure and does not suffer a

bandwidth limitation[16].

28

Chapter 3

Power Amplifier Design

3.1 Power Amplifier specifications

Supply Voltage: 1.2V

Frequency: 60 GHz

Power gain: 20 dB

Output power at 1 dB compression: > 11 dBm

Saturated output power: > 15 dBm

Power added efficiency: > 10%

Input and output impedance: 50Ω

3.2 Injection locked power amplifier technique

In order to reduce the input driving requirement and improve the efficiency, the

injection locked amplifier is investigated which is well-suited for power amplifier

design.

Injection locked technique means the condition in which another self-oscillating

circuit is forced to run at the same frequency as the input signal. A general model for

the injection locked power amplifier is given in Fig.3.1. This positive feedback loop

consists of a nonlinear gain block g(vi,vo) and linear filter H(jω), where the nonlinear

block g(vi,vo) is formed by the cross-coupled devices and H(jω) is implemented by the

matching and load network[17][18].

Without the external current flowing through the PA core, the PA core would self

oscillate at a natural oscillating frequency ω0 if the circuits satisfies the Barkhausen

criterion: The loop gain should be greater than unity and the total phase shift around

the loop has to be multiple of 2π[19].

29

(3. 1)1)( 0 jHf

(3. 2) kjHf 2)(

Where k is an integer. When the signal with the frequency injects into the iv i

circuit, the output of has a phase shift with the respect to the input signal, to f

compensate this extra phase shift, the must change its phase to ensure the )( jH

total phase along the loop keep 2kπ, which also makes the oscillator to track the

injected frequency . i

Suppose that and , where Vdc is the DC )cos( tVVv iIdci )cos( tVv oOo

point. By using the Taylor series expansion of vi around DC point Vdc. can be f

written as:

])cos[(21)cos(),(

00

0 mtmV

vA

mtmAvvf im

oIVvii

m

mmoi dc

(3. 3)

Where the coefficient Am is the function of am and VO. And the first part is the

expression for the free-running oscillator, the second term shows the mixer products

due to the presence of the injected signal.

If the first term is much smaller than the second term, g is almost in proportion to

the magnitude of the injected signal VI, so the magnitude of the output signal V0 can

be written as [20]:

0 0

0H H( )

2I

mm

VV g B j

It is obvious that the output power can be increased by the input power.

g(vi,v0)g(vi,v0) H(jω)H(jω)vi@ωi vo@ωo

Fig. 3.1 Model of the proposed injection locked power amplifier

30

The Adler’s equation can be used to establish the lock-in range [21]:

(3. 4)

sin2

010

T

INj

QII

dtd

Where is the peak current of the injected signal, is the peak current through INjI TI

the negative resistance and is the phase difference between and . At steady 0V INJV

state, and , the lock-in range is:0/ dtd 1sin

(3. 5)T

INJL QI

I2

010

This equation implies that the injection locking only occur within a finite frequency

range around the natural oscillation frequency and the locking range is positively

correlated with the injection current. Hence, to expand the locking range, we can

increase the size of the injection devices and decrease the cross-coupling pairs in

design.

3.3 Circuit design

The power amplifier based on injection-locked structure will redound to improve

gain and efficiency by means of reducing the input driving requirement. The

schematic of the implemented PA is shown in Fig.3.2.

31

Fig. 3.2 The schematic of injection locked power amplifier

This PA core circuit consists of a NMOS cross-coupling pair together with NMOS

transistors used for signal current injection. Among which M1 and M2 are driving

transistors. M3 and M4 are the key devices, this cross-coupling pairs turn the circuits

into an injection locked oscillator. An NMOS current source is used to control the free

running output voltage swing of the PA core. The circuit is free running until the

injected current is large enough to lock the output signal to the input signal.

To avoid self-oscillation, two conditions should be guaranteed. Firstly, we need to

ensure that when the PA is powered up, the input power will always be available and

large enough to make the output signal follow the input signal. Besides, a power-

down mechanism is introduced to avoid free oscillation when PA is not driven.

During power down, M5 is turned off and M6 will pull the local ground node to Vdd.,

and the entire amplifier will be shut down[22][23].

Fig.3.3 plots the power gain versus different transistor size with a fixed bias voltage.

In the left figure, the width of M3 and M4 is set to 30μm and the width of M1 and M2

is set to 60μm in the right figure. It is found that the power gain increases at first, then

decreases with increasing of the transistor size. This is because the transistor size

determines its current. For the injection transistor M1 and M2, the large width results

32

to the larger injection current and power gain. However, due to the circuit limitation,

the power gain decreases finally. As mentioned before, the locking range is positively

correlated with the injection current and inversely proportional to the core current. In

order to improve the bandwidth, we decrease the size of the cross-coupled pair.

However, the cross-coupling pairs M3 and M4 provide for a negative resistance, and

too small transistor is unable to satisfy the oscillatory condition. Hence, we need to

make our selection according to actual situation.

50 55 60 65 70 75 80

10

15

20

25

30

35

Pow

er G

ain

(dB

)

W1 and W2 (um)15 20 25 30 35 40

10

15

20

Pow

er G

ain

(d

B)

W3 and W4 (um)

Fig. 3.3 Power gain versus different device size with and VVb 3.0 VVc 8.0

According to the simulation and optimization, the width/length of the injection

driving transistors M1,M2 is 60μm/65nm, with the figure number of 50; the

width/length of the cross-coupling pair M3,M4 is 30μm/65nm, with the figure number

of 50; and for the current source M5 is 120μm/65nm, with the figure number of 120.

3.4 Balun design

As a passive component, balun plays an key role in the power amplifier design. In

practice, it performs the following functions: First of all, the differential structure is

designed in the power amplifier core in order to reject the common-mode signal and

noise, improve the output voltage swing and reduce the interference to the external

circuit resulting from the power amplifier. However, the load of the power amplifier

33

is always single-ended, A balun is necessary to transfer between the single-ended and

differential signals. Furthermore, as we known, in order to obtain the maximum

output power, matching network is needed to transform the optimum load to a 50Ω

load, and the balun can realize this function perfectly. Finally, balun also plays a role

in isolation.

The balun is a three-port device which is used to convert the single-ended signal

into differential signals. The amplitude of the output differential signals is equal and

the phase is opposite, so when analyzing the balun performance, the amplitude and

phase imbalance are the main figures of merit. Furthermore, the insertion loss is also a

important parameter which measures the energy absorbed when the signal passing

through the balun[24].

The balun is designed based on the Marchand type. The circuit diagram of

Marchand balun with centre-tap is given in Fig 3.4.

Secondly

Secondly

Bias

Output1

Output2

Primary

Primary

Input

C

C

Fig 3.4 The Schematic diagram of Marchand balun

The balun consists of two symmetrical quarter-wave coupled lines, where the

primary line is open-ended and the two secondary lines are connected to the two

output ports respectively, and the top two metal layers M6 and M7 are used as

broadside coupled lines. Center-tap for DC bias is added and two symmetrical

capacitances are connected between the center-tap and the ground to provide an AC

34

path for the signal[25]. The balun is symmetric and the layout is shown in Fig.3.5.

Fig.3.5 The layout of the balun

The carrier frequency of the balun is 60 GHz, and, the width and length of the

coupled lines are optimized by the EM simulation in ADS, and the simulated S-

parameters, insertion loss and imbalances are shown in Fig.3.6-3.8.

50 52 54 56 58 60 62 64 66 68 70

-18

-16

-14

-12

-10

-8

-6

-4

S11

(dB)

Freq (GHz)

35

Fig.3.6 S11 for the input balun

50 52 54 56 58 60 62 64 66 68 701.0

1.5

2.0

2.5

3.0

3.5

IL (d

B)

Freq (GHz)

Fig.3.7 Insertion loss for the input balun

50 52 54 56 58 60 62 64 66 68 700.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Ampl

itude

imba

lanc

e (d

B)

Freq (GHz)

Phas

e Im

bala

nce

(o )

Fig.3.8 Amplitude and phase imbalance for the input balun

The input balun is matched to the input impedance of the PA core. S11 of the

designed input balun is about -18dB at 60 GHz. The insertion loss (IL) is less than

1.5dB in the frequency ranging from 56 GHz to 64 GHz and the minimum insertion

36

loss is 1.21dB at 60 GHz. In this frequency band, the amplitude imbalance is 0.3 dB

and the phase imbalance is less than 0.25°.

Comparing with the input balun, the output balun is matched to the output

impedance of the PA core, and the width is thicker in order to flow through higher

current. The simulation results of the output balun are shown in Fig.3.9-3.11. S11 is

about -24dB at 60 GHz, the insertion loss is less than 1.5dB in the frequency ranging

from 58 GHz to 62 GHz and the minimum insertion loss is 1.32dB at 60 GHz. In this

frequency band, the amplitude imbalance is 0.9 dB and the phase imbalance is less

than 0.7°.

50 52 54 56 58 60 62 64 66 68 70

-25

-20

-15

-10

-5

S11

(dB)

Freq (GHz)

Fig.3.9 S11 for the output balun

50 52 54 56 58 60 62 64 66 68 701.0

1.5

2.0

2.5

3.0

3.5

4.0

IL (d

B)

Freq (GHz)

37

Fig.3.10 Insertion loss for the output balun

50 52 54 56 58 60 62 64 66 68 70

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.2

0.4

0.6

Ampl

itude

Imba

lanc

e (d

B)

Freq (GHz)

Phas

e Im

bala

nce

(o )

Fig.3.11 Amplitude and phase imbalance for the input balun

3.5 PA Simulation Results

The circuit is simulated by using ADS tools, and the single tone harmonic balance

simulation is done to get the transducer power gain and the power efficiency. Fig.3.12

shows the transducer power gain. As expected, the gain decreases as the output power

increases. At 1-dB compression point, the output power is 7.9 dBm.

-10 -5 0 5 10 15 205

10

15

20

Powe

r Gai

n (d

B)

output Power (dBm)

38

Fig.3.12 Power gain of PA

Fig 3.13 shows the power added efficiency of the amplifier. The efficiency is

directly proportional with the output power. The PAE can reach its maximum value of

40% at the output power of 15dBm and at 1-dB compression point, the PAE is 6%.

-10 -5 0 5 10 15 200

10

20

30

40

PA

E (%

)

Output Power (dBm)

Fig.3.13 PAE of the PA

Fig.3.14 shows the power gain reduction and phase shift as the function of the input

power. With the increasing of input power, the phase difference increases at first, and

then decreases. When the input power increases to -11dBm, the gain difference is less

than 1dB. And the phase shift increases as the input power increases. In the input

power ranging from -25dBm to -10dBm, the AM-PM characteristics drops from -0.3︒

to -3.8︒.

39

-25 -20 -15 -10-1.5

-1.0

-0.5

0.0

0.5

Gain

Variatio

n (dB

)

Pin (dBm)-25 -20 -15 -10

-4

-3

-2

-1

0

AM

-PM

(degre

es)

Pin (dBm)

Fig. 3.13 AM to AM and AM to PM versus input power

The results show that the linearity performance of the power amplifier leaves much

to be desired and cannot meet demand completely. In order to improve the available

linear output power and the overall efficiency, the linearization enhancement

technique is necessary. We will put emphasis on discussing the linearization of the

power amplifier in next chapter.

40

Chapter 4

Power Amplifier Linearization

4.1 Adaptive biasing technique

To ensure the power gain is maintained in the whole amplification process, the

bias is operated at a high quiescent point with the high output power. However, when

the power is low, due to this high voltage bias, significant amount of power is wasted

and the efficiency will be decreased greatly. Now adaptive biasing technique is

proposed to solve this problem. Fig.4.1 shows the basic block diagram of this method.

Actually, it is a feedback regulation. The dynamic bias control unit can track and

monitor the output power in real time and then adjust the bias adaptively. The bias is

lower than the normal value at low power level and it gradually increases with the

increasing of the output power. As we known, after the amplifier reaches to its 1-dB

gain compression point, the gain will be degraded. Fortunately, the increased adaptive

bias will boost the power gain in order to compensate the gain reduction. In this way,

the linear operation region extends and both the linearity and efficiency is improved at

the same time[26][27][28].

Dynamic Bias Control

Dynamic Bias Control

PA In PA Out

Vb

En

RF Power

PA

Fig.4.1 The basic block diagram of adaptive biasing technique

41

The schematic of the dynamic bias control part is shown in Fig.4.2.

R1

R2 C

M7 M8

M9

Output 1 Output 2

Ve

Vb1 To Vb

Vd1

b

Figure 4.2 Schematic of the dynamic bias control part

Where, is the bias of the injection transistor. Two low-threshold PMOS bV

transistors M7 and M8 are connected to the differential output in order to sense the

output level. These two transistors with small size and little current consuming have

little influence on PA’s performance. These transistors will turn off when the output

power is low. At this time, the feedback voltage can be expressed as the following

equation:

(4. 1)1

21

2bb V

RRRV

It is obvious that the starting point of the feedback voltage is determined by the bV

voltage and the resistor network. As the output voltage swing becoming larger 1bV

than the threshold voltage, the feedback loop turns on and the feedback voltage can be

calculated by using the following equations:

(4. 2)bbbb ZiVRR

RV

121

2

42

(4. 3)1

1

RVV

ii bbpb

(4. 4))1//()//( 21b

b CjRRZ

Where and represent the total current and impedance at the node b. It is bi bZ

apparent that the feedback voltage increases with the increasing power level. And bV

the same method is applied to , which is the bias voltage of the current source.cV

Fig.4.3 shows the power gain versus different bias voltage. As we have seen, the

power gain is proportional to the bias voltage.

0.30 0.32 0.34 0.36 0.38 0.40 0.42

20

22

24

26

28

30

Pow

er G

ain

(dB

)

Vb Bias (V)0.80 0.82 0.84 0.86 0.88 0.90

20.0

20.1

20.2

20.3

20.4

P

ow

er G

ain

(dB

)

Vc Bias (V)

Fig.4.3 Power gain versus different bias voltage

Fig.4.4 plots the bias voltage versus different input power. When the power is low,

the feedback loop doesn’t work and the bias voltage maintain its original value. When

the input power is more than -20dBm, the bias voltage and increase rapidly. As bV cV

mentioned before, the power gain is proportional to the bias voltage. Hence, the

power gain will increase greatly at the high power level by adjusting the bias voltage

and this increased power gain can compensate for the gain reduction in order to extent

the linear region.

43

-30 -20 -10 0 100.30

0.32

0.34

0.36

0.38

0.40

0.42

V

b b

ias

(V)

RFpower (dBm)-30 -20 -10 0 10

0.80

0.82

0.84

0.86

0.88

0.90

Vc

bias

(V

)RFpower (dBm)

Fig.4.4 Bias voltage versus different input power

Fig.4.5 shows the power gain of PA with and without the adaptive biasing operated

at 1.2V supply. When the output power is low, the power gain is the same as before

because the transistors M7 and M8 are closed and the feedback loop doesn’t work. As

the power increases, because of the increased bias voltage, the power gain is boosted

obviously. It starts to compress eventually until the maximum value of 21.3 dB is

experienced. However, the parasitic capacitance in the layout will mitigate this

overshoot in real design. The 1dB compression point increases from 7.9 dBm to

11.5dBm, and in this region, the power gain keep steady. In another words, the linear

operation region is effectively extended by 3.6 dB.

44

-10 -5 0 5 10 150

5

10

15

20

25

without adaptive biasing wiith adaptibe biasing

Gai

n (d

B)

Output power (dBm)

Fig.4.5 Simulated power gain with and without the adaptive biasing

Fig.4.6 compares the power added efficiency with and without the adaptive biasing.

As we mentioned before, the PAE has obviously positive correlation with the power

gain. Hence, the increased power gain results in the improvement of PAE. The PAE

can reach its maximum value of 40 % at 15dBm of the output power and it can get the

value of 17 % at 1-dB compression point. In conclusion, this technique improves not

only the performance of linearity but also the efficiency.

-10 -5 0 5 10 150

10

20

30

40 without adaptive biasing wiith adaptibe biasing

PAE

(%)

Output power (dBm)

Fig.4.6 Simulated PAE with and without the adaptive biasing

45

Fig.4.7 plots the power gain variation and phase shift as the function of the input

power. These curves represent the AM to AM and AM to PM characteristics under

different conditions when the adaptive bias is on and off, respectively. In the input

power ranging from -25dBm to -20dBm, the results of the original and adaptive

biasing is almost the same. When the adaptive bias is on, the gain variation increases

at first, then decreases with the increasing of input power and the maximum gain

variation reaches to 1.25 dB. But when relatively large changes in bias levels occur,

undesired phase shift occurs as well. The performance of AM to PM with adaptive

biasing is worse than the original power amplifier, and the maximum phase shift

reaches to -6.6 degrees.

-25 -20 -15 -10-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5 without adaptive biasing wiith adaptibe biasing

Gain

Variatio

n (dB

)

Pin (dBm)-25 -20 -15 -10

-7

-6

-5

-4

-3

-2

-1

0

without adaptive biasing wiith adaptibe biasing

AM

-PM

(de

gree

s)

Pin (dBm)

Fig. 4.7 AM to AM and AM to PM versus input power

4.2 Pre-distortion technique

As we mentioned in chapter 2, power amplifier exhibiting the gain compression at

saturation region results in distortion. And a predistorter with a gain expansion

characteristic is introduced to the system in order to compensate for the gain lost in

compression and extend the linear output region. In this paper, a predistortion

46

linearizer using a shunt cold-mode structure is proposed. The schematic is shown in

Fig.4.8.

Vp

Vs

C C

R

R

Pin PoutPA

Fig.4.8 Schematic of the pre-distortion linearizer.

This circuit consists of a cold-mode operation transistor, two resistors and two

bypass capacitors. It can be expressed as the combination of a capacitor ( ) series offC

with a small resistor ( ) and a current source in parallel. The equivalent circuit offR

model is shown in Fig.4.9.

Vds

Ids

Coff

Roff Roff

Coff

Rds

Fig. 4.9 The equivalent circuit model of predistortion linearizer

Consider that the variations of and are much smaller than the variation of offC offR

. So the and are assumed to be constants and gain ( ) can be dsR offC offR 21S

expressed by:

47

(4. 5)

))1((

112

2

0

21

offoff

ds RCj

RZ

S

Where Z0 is a 50Ω characteristic impedance and the drain to source resistor is dsR

the key element of the linearizer which can be expressed by using the equation below.

(4. 6)

ds

dsds

VI

R

1

Where the indicates the slope of its DC-IV curve. As we have seen, dsds VI /

there is negative correlation between and the slope of DC-IV curve. In Fig.4.10, dsR

when the input power is low, the transistor operates in the linear region and is dsR

constant. As the input power increases, the slop of DC-IV curve decreases especially

near the pinch-off voltage which results in the increased [29][30][31]. dsR

0.0 0.2 0.4 0.6 0.8 1.0 1.20

2

4

6

8

10

12

Ids(

mA)

Vds (V)

Fig.4.10 DC-IV curve of the transistor with V and V1pV 6.0sV

48

Fig.4.11 shows the gain expansion of the predistortion linearizer. At low input

power, is a constant. As the input power increases, due to the gain is proportional dsR

to the , the increased will result in 1.4dB gain expansion.dsR dsR

-30 -20 -10 0 10

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

G

ain

Expa

nsio

n (d

B)

Input Power (dBm)

Fig. 4.11 Gain expansion of the predistortion linearizer

Fig.4.12 shows the power gain of PA with and without the predistortion linearizer.

The result implies that the linearizer adopts insertion loss of 2 dB and at 1-dB

compression point, the output power is 9 dBm and the linear operation region is

extended by 1.1 dB. The improvement is not obvious because the original power gain

has shown a sharp decline at the high output level, and the output power with

predistortion linearizer is always less than the original power amplifier. Hence, its

improvement of the linear region is limited to the original output power level.

49

-10 -5 0 5 10 15 205

10

15

20

without predistortion linearizer wiith predistortion linearizer

Powe

r Gai

n (d

B)

output Power (dBm)

Fig.4.12 Power gain of PA with and without the predistortion linearizer

PAE versus output power has been investigated in Fig. 4.13. When the

predistortion linearizer is introduced, PAE slightly decreases. But it improves

PAE@OP1dB from 6% to 9.5%.

-10 -5 0 5 10 15 200

10

20

30

40

without predistortion linearizer wiith predistortion linearizer

PAE

(%)

Output Power (dBm)

Fig.4.13 PAE of PA with and without the predistortion linearizer

Fig4.14 shows the AM-AM and AM-PM with the predistortion linearizer. Unlike

the previous results, the result of the phase shift is positive value. The phase shift is

within the range from 0 to 1.75 degrees.

50

-20 -15 -10 -5-3

-2

-1

0

1G

ain

Variatio

n (dB

)

Pin (dBm)-20 -15 -10 -5

0

1

2

AM

-PM

(degre

es)

Pin (dBm)

Fig.4.14 AM-AM and AM-PM with the predistortion linearizer

As we mentioned before, PA with adaptive biasing technique can extend the linear

region but results in worse AM-PM performance and PA with predistortion linearizer

will improve the AM-PM performance but it is limited to the low output power. Now,

we combine these two techniques together to improve not only the linear region but

also the AM-PM performance. Due to the insertion loss, the bias voltage is required to

increase in order to maintain the gain of 20dB. Now, the gain and PAE of the power

amplifier is shown in Fig.4.15. Compared with the results we got before, the power

gain has delivered an obvious boost for the output power from 0dBm to 10dBm. This

PA delivers a P1dB of 11.5dBm, and a PAE of 13.5%.

51

-10 -5 0 5 10 155

10

15

20

25

0

5

10

15

20

25

30

35

40

Power gain

PAE

(%)

Powe

r Gai

n (d

B)

output Power (dBm)

PAE

Fig.4.15 Gain and PAE of PA with adaptive biasing and predistortion technique

Fig.4.16 shows AM-AM and AM-PM performances of PA with adaptive biasing

and predistortion technique. In the input power ranging from -20dBm to -15dBm, the

gain variation increases from 0.5dB to 1.45dB, and then it drops with the increasing

of the input power. When the input power is larger than -8.5dBm, then gain variation

is less than -1dB. And AM-PM performance is improved a lot now. The phase shift is

within the ranging from -1.75 to 0.5 degrees.

-20 -15 -10 -5

-3

-2

-1

0

1

Gain

Variatio

n (

dB

)

Pin (dBm)-20 -15 -10 -5

-2

-1

0

1

AM

-PM

(de

gree

s)

Pin (dBm)

Fig. 4.16 AM-AM and AM-PM of PA with adaptive biasing and predistortion technique

52

4.3 Two-stage PA

In this section, two-stage power amplifier is proposed and its schematic is shown in

Fig.4.17. The first stage circuit consists of a transistor, an inductor and a DC blocking

capacitor is added between the input and injection-lock PA. The transistor is used as a

current source, driving a controlled current into the load. The inductor provides the

constant current to the transistor and DC blocking capacitor blocks the DC current

flowing into the load. And the two amplifier stages are connected without any

matching network. Furthermore, a voltage bias with a DC feed is added at the gate of

the first stage. The results show that the power gain almost remains the same level and

it is little affected by this voltage bias. However, this bias had significant effect on

efficiency and linearity of the power amplifier. When this bias increases from 0.4V to

0.9V, PAE drops from 31% to 22%, but the AM-PM performance is improved

obviously. As we mentioned before, efficiency and linearity have the opposite

tendency, and a tradeoff must be made. In this thesis, we set voltage bias equal to

0.6V in order to achieve high linearity and high efficiency at the same time.

Injection locked PAPin

Pout

L1

C

V1 Vdd

L2

Fig. 4.17 The schematic of two-stage PA

Fig 4.18 shows the gain of the both two PA stages. As we can see, the first stage

and injection-locked stage deliver a gain of 8dB and 12dB respectively. In the output

53

power ranging from -10dBm to 0dBm, power gain is maintained constant. With the

increasing of the output power, the gain of the injection-locked stage decreases.

Fortunately, the first stage delivers an expansion gain at the high power level. When

the output power is 15dBm, its gain can get almost 12dBm. And the first-stage

expansion gain can boost the overall power gain in order to compensate the second-

stage gain reduction.

-10 -5 0 5 10 152

4

6

8

10

12

The first stage The Injection-locked stage

Gai

n (d

B)

Output Power (dBm)

Fig.4.18 The gain of the both two PA stages

The overall power gain is shown in Fig.4.19. It is obvious that the first-stage

expansion gain is matched to the gain reduction of the injection-locked stage perfectly.

In the output power ranging from -10dBm to 10dBm, power gain is almost maintained

constant. The results indicates that this power amplifier can deliver

and .dBmPsat 3.16 dBmOP dB 41.151

54

-10 -5 0 5 10 156

8

10

12

14

16

18

20

The original power amplifier Two-stage power amplifier

Powe

r G

ain

(dB)

Output Power (dBm)

Fig.4.19 Power gain of original and two-stage power amplifier

PAE of the two-stage power amplifier is shown in Fig.4.20. The first stage is a

linear PA. As we mentioned in chapter 2, it can get a good linear performance at the

cost of the efficiency. So the introducing of the first stage can result in the reduction

of efficiency. However, due to its linear region extended, we can get PAE from 6% to

30%.

-10 -5 0 5 10 15 200

10

20

30

40

The original power amplifier Two-stage power amplifier

PAE

(%)

Output Power (dBm)

Fig. 4.20 PAE of original and two-stage power amplifier

Fig 4.21 shows the AM to AM and AM to PM characteristics versus the different

input power. The AM-AM curve with two-stage is more flatten. Its gain variation is

less than 1dB until the input power reaches to -3dBm. In the input power ranging

from -20dBm to -10dBm, the phase shift is less than 2 degrees and its AM-PM

55

characteristic is better than the original PA as well. With the increasing of input

power, the phase difference increases at first, and then decreases.

-20 -15 -10 -5 0-5

-4

-3

-2

-1

0

1

Two-stage Power amplifier The original Power amplifierP

ow

er V

ariatio

n (d

B)

Output power (dBm)-20 -15 -10 -5 0

-4

-2

0

2

4

6

8

Two-stage power amplifier The original power amplifier

Phase

shift

(d

egre

es)

Output power (dBm)

Fig.4.21 AM-AM and AM-PM of original and two-stage power amplifier

56

Chapter 5

Conclusion and the future work

The increasing demands for high data rates are pushing systems to utilize more and

wider bands at higher frequencies. Now, the 60GHz-band short-distance

communication technology has become the hot topic of the wireless researches. As

the last building block before the antenna, RF power amplifier is critical for wireless

communications system.

In this thesis, we have presented the design of a power amplifier based on the

injection-locked technique in 60GHz band. First of all, the basic principle of the

proposed injection locked power amplifier is analyzed. And then, the balun based on

the Marchand type with centre-tap is introduced. Finally, the simulation results of this

type of power amplifier are got. The results show that the amplifier delivers a gain of

20dB, a Psat of 15dBm and a OP1dB of 7.9 dBm under a 1.2V supply voltage. At 1-dB

compression point, the power added efficiency is 6%.

Moreover, several methods are used to linearize this injection-locked power

amplifier. First of all, adaptive biasing technique is introduced, and the simulation

results show that the linear operation region is extended by 3.6 dB. Next, the pre-

distortion technique is used and due to the output power limitation, the linear

operation region is extended slightly, but its AM-PM performance is improved

obviously. Considering the advantage of these two techniques respectively, we

combine them together to improve not only the linear region but also the AM-PM

performance. The simulation results show that the PA delivers a OP1dB of 11.5dBm, a

PAE of 13.5%, and phase shift is within the ranging from -1.75 to 0.5 degrees. Finally,

two-stage power amplifier is proposed. The first stage and the injection-locked stage

deliver a gain of 8dB and 12dB respectively. At the high output power level, the first

stage produces a boost gain, and this expansion gain compensates the second-stage

57

gain reduction perfectly. The simulation results show that the power amplifier delivers

a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.

In this thesis, single tone harmonic balance simulation is used to simulate the

amplifier and tuning for harmonic frequency components was discarded. The future

work will focus on two-tone measurements and a good extension of this thesis would

be to make further discussion of IM3.

Furthermore, for the two-stage power amplifier, we analyze and discuss the results

but the operational principle is unknown and the next work is to figure out the reason

and explain how it works.

Finally, we just give the pre-simulation results in this thesis, and the future work

will focus on layout, post-simulation and test.

58

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