testability of analogue macrocells embedded in system-on-chip workshop on the testing of high...
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Testability of Analogue Macrocells Embedded in System-on-Chip
Workshop on the Testing of High Resolution Mixed Signal Interfaces
Held in conjunction with the European Test Symposium 2004
Sunday 23rd May 2004Danielle Casanova Room, Congress Center
AJACCIO, Corsica
Sponsored by Fr. V-IST project 34283 “Testability of Analogue Macrocells Embedded in System-on-Chip” TAMES-2
Testability of Analogue Macrocells Embedded in System-on-Chip
TAMES2 : addressing embedded high Resolution Analog Macro Cells Test
Challenges
Christophe GaillardDolphin Integration, France
Testability of Analogue Macrocells Embedded in System-on-Chip
Objectives
• The work will respond to three key industrial demands: – Test cost reduction through minimization of test time
and test development cost– Improvements in test coverage and outgoing quality,
to address the industrial trend for higher quality product at lower cost.
– Development of test reuse concepts and integration of the associated advances in test engineering into the design flow for new interface designs in SoC applications.
Testability of Analogue Macrocells Embedded in System-on-Chip
KEY FIGURES, PARTNERS
2.5 Years Project Duration4 Partners (2 academic, 2 industrial)
DOLPHIN Integration
Testability of Analogue Macrocells Embedded in System-on-Chip
Description of the work : main steps
• The work to be carried out to achieve the advances proposed in converter test engineering will be driven by industrial user’s requirements.
• The main steps of the TAMES-2 project are proposed in the following slides
Testability of Analogue Macrocells Embedded in System-on-Chip
Study of the requirements for industrial mixed-signal test
• A detailed review of test strategies for HR converters has been carried out.
• Reference test plans have been worked out
• Circuit level failure mode analysis, correlation with design specification
• Specification testing effectiveness
Testability of Analogue Macrocells Embedded in System-on-Chip
Definition of suitable innovative Test Techniques
• Innovative Test Techniques have been studied using both BIST and black box approaches
• Decision Matrix : a tool for performance evaluation and comparison was developed to provide a rational metrics
Testability of Analogue Macrocells Embedded in System-on-Chip
Validation of the objectives through the design of
industrial SIP
• an audio codec and an automotive interface, both representing macrocells for use in much larger SoC designs and having complementary test requirements.
• this design includes specification and architecture of the SIP blocks, development of robust schematics for the analogue part
• implementation of DfT techniques and layout in advanced CMOS processes
Testability of Analogue Macrocells Embedded in System-on-Chip
Design and fabrication of test chips including the two SIP
blocks
45 kgatesDigital section
w/ spRAM
Stereo DAC
Stereo ADC
CODEC Demonstrator 25 mm2
Testability of Analogue Macrocells Embedded in System-on-Chip
Characterization and test of the testchips
• Characterization– laboratory test
benches – efficiency of the
DfT solutions– performances of
the SIP blocks
Testability of Analogue Macrocells Embedded in System-on-Chip
Use Plan
• Use of the SIP blocks – by AMI Semiconductors – by Dolphin through inclusion in its SIP
catalogue
• This will include the packaging of the test techniques to allow usage by SoC integrators
Testability of Analogue Macrocells Embedded in System-on-Chip
Dissemination of results
• Result dissemination through academic courses and international conferences
• Web site• http://www.imse.cnm.es/tames2
Testability of Analogue Macrocells Embedded in System-on-Chip
Decision Matrix
Open tool for Test Techniques evaluation and comparison
Testability of Analogue Macrocells Embedded in System-on-Chip
Outline
• Purpose and goal• List of Criteria• Explanation of some key criteria• Example of Decision Matrix• Alternative Test Plan
Testability of Analogue Macrocells Embedded in System-on-Chip
Decision Matrix
• Goal– Measure the impact and performance
of the studied Test Techniques– Assess the Test Techniques relevance
with respect to a reference test plan– Assess the Test Techniques relevance
against TAMES2 targets– Cost computation
Testability of Analogue Macrocells Embedded in System-on-Chip
Decision Matrix : 9 criteria
• 1. Test time in second• 2. Penalty for the test of the rest of the SoC• 3. Test cost saving• 4. Silicon area overhead in sq.mm.• 5. Cost of the test solution• 6. Cost of design and risk of degradation of
performance• 7. Packaging of Test Technique• 8. Package over cost due to additional pins• 9. Specification/functional coverage
Testability of Analogue Macrocells Embedded in System-on-Chip
1. Test time in second
• Time required to perform a test or set of tests
• Parameters– Test time: acquisition + transfer +
computation– Cost per second of the industrial
tester
Testability of Analogue Macrocells Embedded in System-on-Chip
2. Penalty for the test of the rest of the SoC
• The analog ViC insertion may prevent usage of pure digital tester
• Therefore this bring a cost penalty due to higher cost for mixed signal tester
• Parameters– Estimated SoC test duration (default value
is 2 s)– Cost per second of the industrial tester
Testability of Analogue Macrocells Embedded in System-on-Chip
4. Silicon area overhead in mm2
• On chip requirements for test implementation may introduces silicon area overhead
• Parameters– Estimated silicon area overhead– Cost of silicon per mm2 (default value
is 10 cts/mm2)
Testability of Analogue Macrocells Embedded in System-on-Chip
7. Packaging of Test Technique
• The test technique must be properly documented to allow its usage by SoC integrator.– Test specification (hardware and software
requirements)– Application notes– Models including the test technique
• Parameters– Estimated man power, Cost of man power
Testability of Analogue Macrocells Embedded in System-on-Chip
Example of Matrix
Value Cost (cts) Value Cost (cts) Value Cost (cts) Value Cost (cts)
Test time (s) 10,4 0,884 0,2145 0,9438
Cost per second of the tester used (cts/s) 6 6 6 6
Cost per second of the tester which would have been used if the ViC was not embedded (cts/s)
3 3 3 3
Test time of the rest of the SoC (s) 2 2 2 2
Area overhead (sq.mm.) 0 0,5 0,1 0
Silicon cost (cts/sq.mm.) 10 10 10 10
7
Packaging of Test Technique: difficulty for the SoC integrator to use the ViC with embedded Test Technique
Test specification development time (man.week) 14 3,5 14 3,5 14 3,5 14 3,5
Cost (cts)
Criteria ParametersCODEC ref Plan
1 Test time in second 62,4
2Penalty for the test of the rest of the SoC due to the embedding of the Virtual Component
6
4 Silicon area overhead in sq.mm. 0
80,4
Distortion meter
5,304
6
5
29,304
ADC Gain
1,287
6
1
21,787
Walsh
5,6628
6
0
23,6628
Testability of Analogue Macrocells Embedded in System-on-Chip
Alternative Test Plan
• Will be build using new T.T. according to a given test strategy
List of tests of the reference test plan
Test plan #1 Test plan #2 Test plan #3
Test #1Test #2Test #3Test #4Test #5 ReferenceTest #6Test #7Test #8 ReferenceTest #9 ReferenceTest #10Test #11
new TT 5
new TT 1new TT 4
Reference
new TT 4
new TT 1
new TT 2
Reference
new TT 3
Testability of Analogue Macrocells Embedded in System-on-Chip
Example of cost savings
Value Cost (cts) Value Cost (cts) Value Cost (cts)
10,4 0,884 5,725
6 6 6
Cost (cts)
CriteriaCODEC ref Plan
1 Test time in second 62,4
80,4
Distortion meter
5,304
11,304 52,35
Rest of Test Plan
34,35
16.8 cts / deviceare saved!
Testability of Analogue Macrocells Embedded in System-on-Chip
Conclusions
– Decision Matrix is a general and open tool: parameters must be considered from today’s perspective and shall be reviewed according to technological progress
– Test strategy will drive the usage of given T.T. and use the Matrix as decision tool
– The reference testplan may be simplified during production after a learning curve or an intensive characterization of samples and correlation with standard measurements. The proposed Test techniques may play a significant role in this simplification.
– In the market of Virtual Component, the customers are very sensitive to the ease of use of the proposed solution, e.g. BIST (they have often no skill in the field of analog test) even if the test time is higher. The decision parameters need then to be adjusted accordingly
Testability of Analogue Macrocells Embedded in System-on-Chip
That’s it …