design for testability design for testability

Design For Testability Design For Testability -- OrganizationOrganization

�� Overview of DFT TechniquesOverview of DFT Techniques

�� AdAd--hoc techniqueshoc techniques

��ExamplesExamples

��I/O PinsI/O Pins

�� Scan TechniquesScan Techniques

��Full & Partial ScanFull & Partial Scan

C. Stroud 9/09 Design for Testability 1

��Full & Partial ScanFull & Partial Scan

��Multiple Scan ChainsMultiple Scan Chains

�� Boundary ScanBoundary Scan

�� BuiltBuilt--In SelfIn Self--TestTest

�� Evaluation Criteria for DFT TechniquesEvaluation Criteria for DFT Techniques

Overview of DFT TechniquesOverview of DFT Techniques

�� AdAd--hoc techniqueshoc techniques��Target “difficultTarget “difficult--toto--test” test” subcircutssubcircuts to improve to improve

��ControllabilityControllability��ObservabilityObservability

�� Scan techniquesScan techniques��UpUp--front & topfront & top--down structured techniquesdown structured techniques��Enforce general design style & require following design rulesEnforce general design style & require following design rules


��Enforce general design style & require following design rulesEnforce general design style & require following design rules��CAD tools for automatic implementation & vector generationCAD tools for automatic implementation & vector generation

��Full scan design Full scan design -- best overall DFT techniquebest overall DFT technique��Partial scan designPartial scan design��Boundary scan Boundary scan -- for testing device I/O interconnectfor testing device I/O interconnect

�� BuiltBuilt--In SelfIn Self--TestTest��Internal test circuitry incorporated within chip/boardInternal test circuitry incorporated within chip/board

AdAd--Hoc DFT Techniques: Basic IdeaHoc DFT Techniques: Basic Idea

�� Add MUXs to provide access to/from internal circuitryAdd MUXs to provide access to/from internal circuitry

��Controllability & Controllability & ObservabilityObservability

�� Add gates to provide control to internal circuitryAdd gates to provide control to internal circuitry

��Controllability onlyControllability only

�� Add these “test points” only where needed in circuitAdd these “test points” only where needed in circuit

��Low area overhead penaltyLow area overhead penalty


��Low area overhead penaltyLow area overhead penalty

��Little (if any) performance impactLittle (if any) performance impact��Critical paths can often be avoidedCritical paths can often be avoided

��Target difficult to test Target difficult to test subcircuitssubcircuits��Potential for significant increase in fault coveragePotential for significant increase in fault coverage

�� Creative testability solutions on a caseCreative testability solutions on a case--byby--case basiscase basis

��But we have to figure out what & where those areBut we have to figure out what & where those are

AdAd--Hoc DFT Techniques: Some BenefitsHoc DFT Techniques: Some Benefits

�� Provide test points for controllability & Provide test points for controllability & observabilityobservability

�� Provide easier initializationProvide easier initialization

��For logic simulation and design verificationFor logic simulation and design verification

�� Partition the logic into easier to test piecesPartition the logic into easier to test pieces

��Provide access to embedded blocksProvide access to embedded blocks

��Core tests can be reCore tests can be re--usedused


��Core tests can be reCore tests can be re--usedused

�� Bypass clock generation Bypass clock generation cktsckts (oscillators, one(oscillators, one--shots, etc.)shots, etc.)

�� Avoid or bypass asynchronous logicAvoid or bypass asynchronous logic

�� Break feedback loops (when they are a problem)Break feedback loops (when they are a problem)

�� Break up large counters into smaller onesBreak up large counters into smaller ones

�� Disable intentional redundant logic for testingDisable intentional redundant logic for testing

AdAd--Hoc Techniques: ExamplesHoc Techniques: Examples

�� Add pin(s), MUX(s), gate(s) to change Add pin(s), MUX(s), gate(s) to change mode of operationmode of operation

�� Use test mode to modify structures detrimental to testUse test mode to modify structures detrimental to test

��Breaking unBreaking un--initializableinitializable feedback loopsfeedback loops��Helps prevent potentially detectable faultsHelps prevent potentially detectable faults

��Bypassing internal oscillatorsBypassing internal oscillators


0

1

0

1

TestModeTest

Mode

TestClockTestClock

DD QQ

QQ

InternalOscillatorInternal

Oscillator0

1

TestMode

TestClock

D Q

Q

InternalOscillator

DD QQ

QQ 0

1

0

1

TestModeTest

Mode

TestDataTestData

UninitializableFeedback LoopUninitializableFeedback LoopD Q

Q 0

1

TestMode

TestData

UninitializableFeedback Loop

AdAd--Hoc Techniques: Examples (cont.)Hoc Techniques: Examples (cont.)

�� Sometimes gates can replace MUX (gate is smaller)Sometimes gates can replace MUX (gate is smaller)

��Asynchronous resets/presetsAsynchronous resets/presets�� MUX to bypass vs. gate to blockMUX to bypass vs. gate to block

��Breaking up large countersBreaking up large counters�� MUX/gate in carryMUX/gate in carry--chainchain

��Reduces test time from 2Reduces test time from 2NN to 2to 2NN/2/2

NormalReset

NormalReset

0

1

0

1TestResetTestReset

DD QQ

QQ

asyncresetasyncreset

NormalReset

0

1TestReset

D Q

Q

asyncreset


TestModeTest

Mode

ResetReset

TestMode

Reset

TestModeTestMode

DD QQ

QQ


NormalReset

NormalReset

TestMode

D Q

Q

asyncreset

NormalReset

Cin CounterCoutCin CounterCoutCin CounterCoutCin CounterCout

0

1

0

1

Test ModeTest Mode

TestDataTestData

Cin CounterCoutCin CounterCout

0

1

Test Mode

TestData

Cin CounterCoutCin CounterCoutCin CounterCoutCin CounterCout

Test ModeTest Mode

Cin CounterCoutCin CounterCout

Test Mode


Partitioning into easy to test Partitioning into easy to test subcircuitssubcircuits using MUXsusing MUXs�� Each Each subcircuitsubcircuit can be tested independentlycan be tested independently

��this may require many MUXsthis may require many MUXs�� Example of partitioning pipelined structure Example of partitioning pipelined structure (works for (works for

almost any almost any cktckt))��T1=0, T2=1 T1=0, T2=1 ⇒⇒ normal system mode of operationnormal system mode of operation��T1=0, T2=0 T1=0, T2=0 ⇒⇒ testing testing cktckt AA��T1=1, T2=0 T1=1, T2=0 ⇒⇒ testing testing cktcktBB AA BB CCA B C


��T1=1, T2=0 T1=1, T2=0 ⇒⇒ testing testing cktcktBB��T1=1, T2=1 T1=1, T2=1 ⇒⇒ testing testing cktckt CC

BeforeDFT

BeforeDFT

AA BB CC

BeforeDFT

A B C

AfterDFTAfterDFT

AA BB CCM

UX

MU

X

MU

XM

UX

MU

XM

UX

MU

XM

UX

T1T1 T2T2T1T1

T1T1

AfterDFT

A B CM

UX

MU

X

MU

X

MU

XT1 T2T1

T1


Partitioning using fewer MUXsPartitioning using fewer MUXs

�� Testing is more difficult but easier than original circuitTesting is more difficult but easier than original circuit

�� A more observableA more observable

��Less than full DFTLess than full DFT

�� C more controllableC more controllable


After

DFT

After

DFTAA BB CC

MU

XM

UX

MU

XM

UX

TestingTesting

AA BB CC

MU

XM

UX

MU

XM

UX

After

DFTA B C

MU

X

MU

X

Testing

A B C

MU

X

MU

X



�� B is completelyB is completely

��ControllableControllable

��ObservableObservable��Same as full DFTSame as full DFT

�� Half the area penaltyHalf the area penalty

Testing

Ckt B

Testing

Ckt BAA BB CC

MU

XM

UX

MU

XM

UX

Ckt ACkt AAA BB CC

MU

XM

UX

MU

XM

UX

Testing

Ckt C

Testing

Ckt CAA BB CC

MU

XM

UX

MU

XM

UX

Testing

Ckt BA B C

MU

X

MU

X

Ckt AA B C

MU

X

MU

X

Testing

Ckt CA B C

MU

X

MU

X

Ad Hoc Techniques: I/O PinsAd Hoc Techniques: I/O Pins

Extra I/O pins are often required (sometimes a lot of I/O)Extra I/O pins are often required (sometimes a lot of I/O)

�� Test data inputs may be able to share primary inputsTest data inputs may be able to share primary inputs

�� Test data outputs can share primary outputsTest data outputs can share primary outputs

�� Test data/mode for gate test point typically need I/O pinsTest data/mode for gate test point typically need I/O pins

�� Test mode control signals for MUX test points require:Test mode control signals for MUX test points require:�� Extra I/O pinsExtra I/O pins

��Devices with out processor interfaceDevices with out processor interface


��Devices with out processor interfaceDevices with out processor interface

��Decode test mode pins to obtain desired test modesDecode test mode pins to obtain desired test modes

��Assumes only a subset of possible combinations neededAssumes only a subset of possible combinations needed

�� Extra internal test register bitsExtra internal test register bits

��Devices with processor interface Devices with processor interface

After

DFT

After

DFTAA BB CC

MU

XM

UX

MU

XM

UX

After

DFTA B C

MU

X

MU

X

TestModeTestMode

DD QQ

QQ


NormalReset

NormalReset

TestMode

D Q

Q

asyncreset

NormalReset

AdAd--Hoc Techniques: SummaryHoc Techniques: Summary�� Advantages:Advantages:

��Relatively low area overhead and performance impactRelatively low area overhead and performance impact��1 MUX (or gate) per test point1 MUX (or gate) per test point

��Critical paths can often be avoided Critical paths can often be avoided

��Moderate to good improvements in testabilityModerate to good improvements in testability

��Does not constrain the designDoes not constrain the design

��Can be used with other DFT techniques like BISTCan be used with other DFT techniques like BIST


��Can be used with other DFT techniques like BISTCan be used with other DFT techniques like BIST

�� Disadvantages:Disadvantages:��Requires manual design & implementationRequires manual design & implementation

��Limited CAD support (if any) availableLimited CAD support (if any) available

��I/O pin overhead can be high in some casesI/O pin overhead can be high in some cases

��Fault simulation required to evaluate effectivenessFault simulation required to evaluate effectiveness

��Considerable test development effort requiredConsiderable test development effort required

Scan Design Techniques: Basic IdeaScan Design Techniques: Basic Idea

�� Transform FFs in sequential logic into shift registerTransform FFs in sequential logic into shift register

��All FFs controllable & observable via serial accessAll FFs controllable & observable via serial access�� Many different types of scan FF (too many!)Many different types of scan FF (too many!)

��Test problem simplified to testing combinational logicTest problem simplified to testing combinational logic�� The best overall DFT approach ever developedThe best overall DFT approach ever developed

DiDi QiQiDi QiPrimaryPrimary PrimaryPrimaryPrimary PrimaryPrimaryPrimary PrimaryPrimaryPrimary Primary


FFFFClkClk

FFClk

Scan FFScan FF

ClkClk

DiDi QiQi0

1

0

1Qi-1Qi-1

ScanModeScanMode

Scan FF

Clk

Di Qi0

1Qi-1

ScanMode

ScanFFsScanFFs

CombinationalLogic

CombinationalLogic

PrimaryInputsPrimaryInputs

PrimaryOutputsPrimaryOutputs

ScanModeScanMode

ScanDataOut

ScanDataOut

ScanData InScanData In

ScanFFs

CombinationalLogic

PrimaryInputs

PrimaryOutputs

ScanMode

ScanDataOut

ScanData In


PrimaryOutputsPrimaryOutputsCombinational

LogicCombinational

Logic

FFsFFs

PrimaryInputs

PrimaryOutputsCombinational

Logic

FFs

Level Sensitive Scan DesignLevel Sensitive Scan Design�� Originally developed by IBMOriginally developed by IBM

��Used level sensitive latchesUsed level sensitive latches��System vs. scan mode controlled by clocksSystem vs. scan mode controlled by clocks

��SCLK SCLK –– system clock to slave latchsystem clock to slave latch��MCLK MCLK –– system clock to master latchsystem clock to master latch

��1 MCLK pulse + 1 SCLK pulse = 1 system clock cycle1 MCLK pulse + 1 SCLK pulse = 1 system clock cycle��TCLK TCLK –– test clock to scan latchtest clock to scan latch

��1 TCLK pulse + 1 SCLK pulse = 1 scan clock cycle1 TCLK pulse + 1 SCLK pulse = 1 scan clock cycle


Di

MCLK

Di

MCLK

Qi-1

TCLK

Qi-1

TCLK

Qi

Qi

Qi

Qi

SCLKSCLK Slave LatchSlave LatchMaster LatchMaster Latch

Scan LatchScan Latch

Di

MCLK

Qi-1

TCLK

Qi

Qi

SCLK Slave LatchMaster Latch

Scan Latch

Scan Design Testing SequenceScan Design Testing Sequence

Step 1.Step 1.Shift some patterns through scan chainShift some patterns through scan chain

��FFs are now completely testedFFs are now completely tested

Step 2.Step 2.ScanScan--in test vector in test vector

��Scan Mode Scan Mode = 1= 1

Step 3.Step 3.Apply test vector at PIsApply test vector at PIs

Step 4.Step 4.Observe results at POsObserve results at POs

ScanFFsScanFFs

CombinationalLogic

CombinationalLogic


PrimaryOutputsPrimaryOutputs

ScanScan

ScanDataOut

ScanDataOut

ScanData InScanData In

ScanFFs

CombinationalLogic

PrimaryInputs

PrimaryOutputs

Scan

ScanDataOut

ScanData In


Step 4.Step 4.Observe results at POsObserve results at POs

Step 5.Step 5.Apply Apply Clock Clock to capture results in scan chainto capture results in scan chain


Step 6.Step 6.ScanScan--out results & scanout results & scan--in next test vector in next test vector


Step 7.Step 7.Go to Step 3 until all test vectors processedGo to Step 3 until all test vectors processed

ScanModeScanModeScanMode

Scan Design Techniques: AdvantagesScan Design Techniques: Advantages

�� Fully automated DFT processFully automated DFT process��WellWell--supported by CAD vendorssupported by CAD vendors��Sequential circuits become combinational in test modeSequential circuits become combinational in test mode

�� ATPG CAD tools for generating test vectorsATPG CAD tools for generating test vectors��Typically no fault simulation requiredTypically no fault simulation required

�� ATPG can identify redundant logicATPG can identify redundant logic��Helps minimize designHelps minimize design

��Reduced timeReduced time--toto--marketmarket


��Reduced timeReduced time--toto--marketmarket�� High fault coverageHigh fault coverage

��Near 100% for gate level stuckNear 100% for gate level stuck--at and bridging faultsat and bridging faults�� Can be applied hierarchicallyCan be applied hierarchically

��chips chips ⇒⇒ boards boards ⇒⇒ systemsystem�� Allows simplified & accurate fault/defect diagnosis & FMAAllows simplified & accurate fault/defect diagnosis & FMA�� Highly structured & provides good basis for BISTHighly structured & provides good basis for BIST

Scan Design Techniques: DisadvnatagesScan Design Techniques: Disadvnatages

�� Overhead:Overhead:

��Pins: 3 ( Pins: 3 ( Scan Data In, Scan Data Out, Scan ModeScan Data In, Scan Data Out, Scan Mode))�� Scan Data InScan Data In can be shared with primary inputcan be shared with primary input

�� Scan Data OutScan Data Out can be shared with primary outputcan be shared with primary output

��Area Overhead: 1 MUX per flipArea Overhead: 1 MUX per flip--flopflop��Typically 2Typically 2--10% total area overhead penalty10% total area overhead penalty

��Performance degradation: added delay through MUXPerformance degradation: added delay through MUX


��Performance degradation: added delay through MUXPerformance degradation: added delay through MUX

��Routing overhead: scan chain connections, Routing overhead: scan chain connections, Scan ModeScan Mode�� Long test application time:Long test application time:

��# clock cycles # clock cycles == #vectors #vectors ×× (#FFs + 1) + #FFs(#FFs + 1) + #FFs��Lots of vectors & output responses to storeLots of vectors & output responses to store

�� Logic must be synchronousLogic must be synchronous

�� Difficult to test at system clock speed Difficult to test at system clock speed

Variations on Scan Design TechniquesVariations on Scan Design Techniques

�� Multiple scan chainsMultiple scan chains

��Fewer clock cycles to scan vectors in/outFewer clock cycles to scan vectors in/out

��Reduces test time if scan chains are balancedReduces test time if scan chains are balanced�� MM times faster for times faster for MM equal length scan chainsequal length scan chains

��Good for multiple clock (or clockGood for multiple clock (or clock--edge) circuitsedge) circuits

��Additional pins for Scan Data In/Out for each chainAdditional pins for Scan Data In/Out for each chain


��Additional pins for Scan Data In/Out for each chainAdditional pins for Scan Data In/Out for each chain�� Scan Data In can come from PIsScan Data In can come from PIs

�� Scan Data Out can use POs if output FF is last in scan chainScan Data Out can use POs if output FF is last in scan chain

�� Partial Scan Design replaces only selected FFs in devicePartial Scan Design replaces only selected FFs in device��Full scan replaces all FFs in device with scan FFsFull scan replaces all FFs in device with scan FFs

��Lower area & performance penalty than full scanLower area & performance penalty than full scan��But usually lower fault coverage as wellBut usually lower fault coverage as well

Scan Design Techniques: Partial ScanScan Design Techniques: Partial Scan

Lower area & performance penalty comes with price:Lower area & performance penalty comes with price:

�� What FFs should be replace and how manyWhat FFs should be replace and how many

��TradeTrade--off between fault coverage and area overheadoff between fault coverage and area overhead

��FF replacement selection methodsFF replacement selection methods�� Structural:Structural: select FFs to cut loopsselect FFs to cut loops�� ATPGATPG--based:based: select FFs useful during ATPGselect FFs useful during ATPG


�� TestabilityTestability--based:based: select FFs to maximize testabilityselect FFs to maximize testability

�� CAD tool support more limited than for full scanCAD tool support more limited than for full scan

�� Fault simulation typically required for partial scanFault simulation typically required for partial scan

��Not required for full scan since done by ATPGNot required for full scan since done by ATPG

�� Significantly more complex diagnosisSignificantly more complex diagnosis

�� Still difficult test at system clock speedStill difficult test at system clock speed

Full Scan Full Scan -- Partial Scan Comparison ExamplePartial Scan Comparison Example

Comparison study data from Comparison study data from Jet Propulsion LaboratoryJet Propulsion Laboratory

�� Viterbi Butterfly Decoder used for comparisonViterbi Butterfly Decoder used for comparison

��Fewer FFs replaced with partial scanFewer FFs replaced with partial scan

��Lower area overhead with partial scanLower area overhead with partial scan

��More vectors but fewer clock cycles with partial scanMore vectors but fewer clock cycles with partial scan


Number of Scan FFsNumber of Scan FFsLogic OverheadLogic Overhead

Number of VectorsNumber of VectorsClock cycles/vectorClock cycles/vectorTotal clock cyclesTotal clock cycles



Full ScanFull Scan448448

24.6%24.6%3434449449

15,71415,714


24.6%24.6%3434449449

15,71415,714

Partial ScanPartial Scan256256

14.1%14.1%4141262262

10,99810,998


14.1%14.1%4141262262

10,99810,998




24.6%24.6%3434449449

15,71415,714


14.1%14.1%4141262262

10,99810,998

Boundary ScanBoundary Scan�� Developed to test interconnect between chips on PCBDeveloped to test interconnect between chips on PCB

��Originally referred to as JTAG (Joint Test Action Group)Originally referred to as JTAG (Joint Test Action Group)��Uses scan design based approach to test external interconnectUses scan design based approach to test external interconnect��NoNo--contact probe overcomes problems of “incontact probe overcomes problems of “in--circuit” testing:circuit” testing:

��Surface mount components with less than 100 mil pin spacingSurface mount components with less than 100 mil pin spacing��DoubleDouble--sided component mounting sided component mounting ��MicroMicro-- and floating and floating viasvias

�� Provides standardized test interfaceProvides standardized test interface


�� Provides standardized test interfaceProvides standardized test interface��IEEE standard 1149.1 IEEE standard 1149.1 ��Four wire interface Four wire interface

�� TMS TMS -- Test Mode SelectTest Mode Select�� TCK TCK -- Test ClockTest Clock�� TDI TDI -- Test Data InTest Data In�� TDO TDO -- Test Data OutTest Data Out

��TRST TRST -- reset (optional & rarely included)reset (optional & rarely included)

BS IntBS IntBS IntBS Int

CoreCoreApplicationApplication

LogicLogic


LogicLogic

TMS TCK TDI TDOTMS TCK TDI TDO

I/O buffer I/O buffer w/ BS cellw/ BS cellI/O buffer I/O buffer w/ BS cellw/ BS cell

BS chainBS chainBS chainBS chain BS IntBS Int


LogicLogic

TMS TCK TDI TDO

I/O buffer I/O buffer w/ BS cellw/ BS cell

BS chainBS chain

Boundary Scan (cont.)Boundary Scan (cont.)Additional logic required:Additional logic required:

�� 1 Boundary Scan cell per I/O pin1 Boundary Scan cell per I/O pin

�� Test Access Port (TAP)Test Access Port (TAP)

�� 44--wire interfacewire interface�� TMSTMS

�� TCKTCK

�� TDITDI

BS Chain (I/O buffers)BS Chain (I/O buffers)BS Chain (I/O buffers)BS Chain (I/O buffers)

MU

XM

UX

MU

XM

UX

FFFFFFFFTDOTDO

MU

XM

UX

MU

XM

UX

User Defined RegistersUser Defined RegistersUser Defined RegistersUser Defined Registers

Bypass RegisterBypass RegisterBypass RegisterBypass Register

TDITDI

BS Chain (I/O buffers)BS Chain (I/O buffers)

MU

XM

UX

FFFFTDO

MU

XM

UX

User Defined RegistersUser Defined Registers

Bypass RegisterBypass Register

TDI


�� TDITDI

�� TDOTDO

�� TAP controllerTAP controller��1616--state FSMstate FSM

��Controlled by TMS & TCKControlled by TMS & TCK

�� various registers forvarious registers for�� InstructionsInstructions

��OperationsOperations

Instruction RegisterInstruction RegisterInstruction RegisterInstruction Register

Instruction DecoderInstruction DecoderInstruction DecoderInstruction Decoder

MU

XM

UX

MU

XM

UX

TAPTAPControllerController


TMSTCKTMSTCK

Instruction RegisterInstruction Register

Instruction DecoderInstruction Decoder

MU

XM

UX


TMSTCK

Boundary Scan Cell ArchitectureBoundary Scan Cell Architecture

BS Cell OperationBS Cell OperationBS Cell Operation

MU

XM

UX

MU

XM

UX

Shift_DRShift_DR

ININ

SINSIN

SOUTSOUT

Capture_DRCapture_DR Update_DRUpdate_DR

OUTOUT

Mode_ControlMode_Control

D QD QCAPCAPCKCK

D QD QCAPCAPCKCK

D QD QUPDUPDCKCK

D QD QUPDUPDCKCK

MU

XM

UX

MU

XM

UX

MU

XM

UX

Shift_DR

IN

SIN

SOUT

Capture_DR Update_DR

OUT

Mode_Control

D QD QCAPCAPCKCK

D QD QUPDUPDCKCK

MU

XM

UX

BiBi--directional buffers directional buffers require multiple BS cellsrequire multiple BS cells

InputInputCellCellInputInputCellCell

Input datato IC coreInput datato IC core

BS test data in (SIN)BS test data in (SIN)

InputInputCellCell

Input datato IC core

BS test data in (SIN)

Basic BS CellBasic BS Cell


OperationalOperationalModeMode

NormalNormalScanScan

CaptureCaptureUpdateUpdate




DataDataTransferTransfer

IN IN →→ OUTOUTSSININ →→ CAPCAPIN IN →→ CAPCAP

CAP CAP →→ UPDUPD




BS Cell OperationBS Cell Operation







BS Cell Operation

Tri-state controlFrom IC core


OutputOutputCellCell


ControlControlCellCell


CellCellCellCell

PadPadPadPad

to IC coreto IC core

Output dataFrom IC coreOutput dataFrom IC core

BS test data out (SOUT)BS test data out (SOUT)




CellCell

PadPad

to IC core

Output dataFrom IC core

BS test data out (SOUT)

Boundary Scan TAP Controller OperationBoundary Scan TAP Controller Operation

1. Send test instruction serially via 1. Send test instruction serially via

TDI TDI into Instruction Register into Instruction Register

((shiftshift--IRIR))

2. Decode instruction and configure 2. Decode instruction and configure

Select DRSelect DRSelect DRSelect DR

Capture DRCapture DRCapture DRCapture DR

Shift DRShift DRShift DRShift DR

ExitExit--1 DR1 DRExitExit--1 DR1 DR

00

00

11

00

11

Select IRSelect IRSelect IRSelect IR

Capture IRCapture IRCapture IRCapture IR

Shift IRShift IRShift IRShift IR

ExitExit--1 IR1 IRExitExit--1 IR1 IR

00

00

11

00

11

11

Test Logic ResetTest Logic ResetTest Logic ResetTest Logic Reset

Run Test IdleRun Test IdleRun Test IdleRun Test Idle

00

11

11 1100

Note: transitionson rising edgeof TCK basedon TMS value

Note: transitionson rising edgeof TCK basedon TMS value Select DRSelect DR

Capture DRCapture DR

Shift DRShift DR

ExitExit--1 DR1 DR

0

0

1

0

1

Select IRSelect IR

Capture IRCapture IR

Shift IRShift IR

ExitExit--1 IR1 IR

0

0

1

0

1

1

Test Logic ResetTest Logic Reset

Run Test IdleRun Test Idle

0

1

1 10

Note: transitionson rising edgeof TCK basedon TMS value


2. Decode instruction and configure 2. Decode instruction and configure

test circuitry (test circuitry (updateupdate--IRIR))

3. Send test data serially into Data 3. Send test data serially into Data

Register (Register (shiftshift--DRDR) via ) via TDITDI

4. Execute instruction (4. Execute instruction (updateupdate--DRDR & &

capturecapture--DRDR))

5. Retrieve test results captured in 5. Retrieve test results captured in

Data Register (Data Register (shiftshift--DRDR) serially ) serially

via via TDOTDO


Pause DRPause DRPause DRPause DR


Update DRUpdate DRUpdate DRUpdate DR

00

11

11

11

00

00

00


Pause IRPause IRPause IRPause IR


Update IRUpdate IRUpdate IRUpdate IR

00

11

11

11

00

00

00

11 11ExitExit--1 DR1 DR

Pause DRPause DR

ExitExit--2 DR2 DR

Update DRUpdate DR

0

1

1

1

0

0

0

ExitExit--1 IR1 IR

Pause IRPause IR

ExitExit--2 IR2 IR

Update IRUpdate IR

0

1

1

1

0

0

0

1 1

Boundary Scan InstructionsBoundary Scan Instructions

Defined by IEEE 1149.1 standard:Defined by IEEE 1149.1 standard:�� Mandatory InstructionsMandatory Instructions

��ExtestExtest –– to test external interconnect between ICsto test external interconnect between ICs��Bypass Bypass –– to bypass BS chain in ICto bypass BS chain in IC��Sample/Preload Sample/Preload –– BS chain samples external I/OBS chain samples external I/O��IDCodeIDCode––3232--bit device IDbit device ID


��IDCodeIDCode––3232--bit device IDbit device ID�� Optional InstructionsOptional Instructions

��IntestIntest –– to test internal logic within the ICto test internal logic within the IC��RunBISTRunBIST –– to execute internal Builtto execute internal Built--In SelfIn Self--TestTest

�� If applicable (this is rare)If applicable (this is rare)

��UserCodeUserCode –– 3232--bit programming data codebit programming data code��For programmable logic circuitsFor programmable logic circuits

��User Defined InstructionsUser Defined Instructions

Boundary Scan: UserBoundary Scan: User--Defined InstructionsDefined Instructions

�� UserUser--defined instructions facilitate:defined instructions facilitate:

��Public instructions (available for customer use)Public instructions (available for customer use)

��Private instructions (for the manufacturer use only)Private instructions (for the manufacturer use only)

��Extending the standard to a universal interfaceExtending the standard to a universal interface��For any system operation feature or functionFor any system operation feature or function

��A communication protocol to access new IC test functionsA communication protocol to access new IC test functions


��A communication protocol to access new IC test functionsA communication protocol to access new IC test functions

�� ExampleExample: : Texas InstrumentsTexas Instruments 74BCT824474BCT8244

��Octal buffer with Boundary ScanOctal buffer with Boundary Scan

��Additional 2Additional 2--bit Control Register whose state can bit Control Register whose state can

reconfigure the BS Register for BIST functions reconfigure the BS Register for BIST functions

(pseudorandom pattern generator or signature analyzer)(pseudorandom pattern generator or signature analyzer)

��Additional instructions to initiate these functionsAdditional instructions to initiate these functions

Boundary Scan: AdvantagesBoundary Scan: Advantages

�� It’s a standard!!! (IEEE 1149.1)It’s a standard!!! (IEEE 1149.1)

��Allows mixing components from different vendorsAllows mixing components from different vendors

��Provides excellent interface to internal BIST circuitryProvides excellent interface to internal BIST circuitry

�� Well supported by CAD tool vendors, IC & ATE manufacturersWell supported by CAD tool vendors, IC & ATE manufacturers

�� Allows testing of board & system interconnectAllows testing of board & system interconnect

��BackBack--plane interconnect test without using PCB functionalityplane interconnect test without using PCB functionality


��Very high fault coverage for interconnectVery high fault coverage for interconnect

�� Useful in diagnosis & FMAUseful in diagnosis & FMA

��Provides componentProvides component--level fault isolation level fault isolation

��Allows realAllows real--time sampling of devices on boardtime sampling of devices on board

��Useful at wafer test Useful at wafer test (fewer probes needed)(fewer probes needed)�� BS path reconfigured to bypass ICs not under test for faster testBS path reconfigured to bypass ICs not under test for faster test

Boundary Scan: DisadvantagesBoundary Scan: Disadvantages

�� Overhead:Overhead:

��Logic: about 300 gates/chip for TAP + about 15 gates/pinLogic: about 300 gates/chip for TAP + about 15 gates/pin��Overall overhead typically small (1Overall overhead typically small (1--3%)3%)

��But significant for only testing external interconnectBut significant for only testing external interconnect

��Especially triEspecially tri--state (2 cells) & bistate (2 cells) & bi--directional buffers (3 cells)directional buffers (3 cells)

��I/O Pins: 4I/O Pins: 4


�� 5 if optional TRST (Test Reset) pin is included5 if optional TRST (Test Reset) pin is included

��I/O delay penalty I/O delay penalty �� 1 MUX delay on all input & output pins1 MUX delay on all input & output pins

��This can be reduced by designThis can be reduced by design

�� Internal scan design cannot have multiple chainsInternal scan design cannot have multiple chains

�� Cannot test at system clock speedCannot test at system clock speed

��But internal BIST can run at system clock speedBut internal BIST can run at system clock speed

BuiltBuilt--In SelfIn Self--Test (BIST)Test (BIST)�� Provides the capability of a circuit to test itselfProvides the capability of a circuit to test itself�� Can be applied hierarchically: module, chip, board, or systemCan be applied hierarchically: module, chip, board, or system�� Provides Provides vertical testabilityvertical testability = same test circuitry used all all = same test circuitry used all all

levels of testing: from chip to systemlevels of testing: from chip to system�� OnOn--line BIST:line BIST: testing occurs during normal system operationtesting occurs during normal system operation�� OffOff--line BIST:line BIST: testing occurs when circuit is outtesting occurs when circuit is out--ofof--serviceservice


TestTestPatternPattern

GeneratorGenerator(TPG)(TPG)



OutputOutputResponseResponseAnalyzerAnalyzer(ORA)(ORA)


CircuitCircuitUnder TestUnder Test

(CUT)(CUT)


(CUT)(CUT)

TestTestControllerController


BIST StartBIST Start BIST DoneBIST Done

System Data InSystem Data In System Data OutSystem Data Out

Pass/Failor

Signature

Pass/Failor

Signature





(CUT)(CUT)


BIST Start BIST Done

System Data In System Data Out

Pass/Failor

Signature

DFT Evaluation CriteriaDFT Evaluation Criteria

�� Area overhead Area overhead �� Performance penaltiesPerformance penalties�� IO pin countIO pin count�� CAD tool supportCAD tool support�� Fault simulationFault simulation�� ATE costATE cost

Power dissipationPower dissipation

Area Overhead Calculation MethodsArea Overhead Calculation Methods

chip areachip areaarea of chip w/DFTarea of chip w/DFT

area of chip w/o DFTarea of chip w/o DFT

number of gatesnumber of gatestotal gates w/DFTtotal gates w/DFT

total gates w/o DFTtotal gates w/o DFTfrequently used frequently used

methodmethodtotal gates for DFTtotal gates for DFTtotal gates w/o DFTtotal gates w/o DFT

most frequently most frequently used methodused method

total gates for DFTtotal gates for DFTtotal gates w/DFTtotal gates w/DFT

number of gate number of gate inputsinputs

total gate inputs for DFTtotal gate inputs for DFTtotal gate inputs w/DFTtotal gate inputs w/DFT


�� Power dissipationPower dissipation�� Risk to projectRisk to project

��Increase in design time vs. test time reductionIncrease in design time vs. test time reduction�� Economic impact on productEconomic impact on product

��Impact on product quality and product costImpact on product quality and product cost�� How well does the DFT circuitry get tested?How well does the DFT circuitry get tested?

��Does the BIST circuitry also test itself?Does the BIST circuitry also test itself?

inputsinputs total gate inputs w/DFTtotal gate inputs w/DFTNumber of gate Number of gate

I/OI/Ototal gate I/O for DFTtotal gate I/O for DFTtotal gate I/O w/DFTtotal gate I/O w/DFT

design for testability design for testability

Documents