TCAD Simulation forTCAD Simulation forSOI Pixel DetectorSOI Pixel Detector

October 31, 2007October 31, 2007IEEE-NSS, Honolulu, Hawaii, USAIEEE-NSS, Honolulu, Hawaii, USA

Hirokazu Hayashi, Hirotaka Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.),Komatsubara (Oki Elec. Ind. Co.),

Yasuo Arai, Yasuo Arai, Masashi HazumiMasashi Hazumi (KEK), (KEK),Yuji Saegusa (TIT)Yuji Saegusa (TIT)

for the SOIPIX groupfor the SOIPIX group

2006/10/31 M. Hazumi (KEK) 2

SOIPIX collaboratorsSOIPIX collaboratorsSOIPIX collaboratorsSOIPIX collaboratorsKEK Detector Technology Project : [SOIPIX Group]

Y. Arai*, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda,H. IkedaA,K. HaraB, H. MiyakeB, H. IshinoC, Y. SaegusaC, T. KawasakiD, E. MartinE, G. VarnerE, H. TajimaF, K. FukudaG, H. HayashiG, H. KomatsubaraG, J. IdaG , M. OhnoG

KEK 、 JAXAA, U. TsukubaB, TITC,Niigata U.D, U. HawaiiE, SLACF, OKI Elec. Ind. Co.G

(*)—contact person

Y. Arai*, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda,H. IkedaA,K. HaraB, H. MiyakeB, H. IshinoC, Y. SaegusaC, T. KawasakiD, E. MartinE, G. VarnerE, H. TajimaF, K. FukudaG, H. HayashiG, H. KomatsubaraG, J. IdaG , M. OhnoG

KEK 、 JAXAA, U. TsukubaB, TITC,Niigata U.D, U. HawaiiE, SLACF, OKI Elec. Ind. Co.G

(*)—contact person

2006/10/31 M. Hazumi (KEK) 3

OverviewOverview

LSI Manufacturing

LSI Manufacturing

Real

VirtualSpecificationsSpecifications

Function designFunction design

Logic designLogic design

Circuit designCircuit design

Layout designLayout design

Mask fabricationMask fabrication

Device productionDevice production PrototypingPrototyping

Process dataProcess data

CharacterizationCharacterization

Device dataDevice data

TCAD

Processsimulation

Processsimulation

Devicesimulation

Devicesimulation

~3mon.

Fast Deeper understanding

TCAD = Technology CAD

• ENEXSS (Environment for NExt Simulation System)

• Developed by Selete (Semiconductor Leading Edge Technologies)( http://www.selete.co.jp/?lang=EN )

• Full 3D process/device simulation !• Commercially available from TCAD-International (

http://www.tcad-international.com/ENEXSS_e.html )

• ENEXSS (Environment for NExt Simulation System)

• Developed by Selete (Semiconductor Leading Edge Technologies)( http://www.selete.co.jp/?lang=EN )

• Full 3D process/device simulation !• Commercially available from TCAD-International (

http://www.tcad-international.com/ENEXSS_e.html )

• Back gate effect• Circuit-sensor crosstalk• Implantation

parameters• Guard ring design• Pixel layout

• Back gate effect• Circuit-sensor crosstalk• Implantation

parameters• Guard ring design• Pixel layout

Topics covered in this talkTopics covered in this talk

2006/10/31 M. Hazumi (KEK) 4

Back gate effectBack gate effect

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

-20

-16

-12 -8 -4 0 4 8 12 16 20

Vts0(V)

VB (V)

Th

resh

old

vo

ltag

e (V

)

Back bias (V)-20 -10 0 +10 +20

ENEXSS TCAD

Back Gate

Substrate voltage acts as Back Gate,

and changes transistor threshold.

Measurement

TCAD

2006/10/31 M. Hazumi (KEK) 5

Back gate effect:Back gate effect:mitigation with p+ mitigation with p+

implants implants

Bulk: N- (~700ohm cm, 6 x 1012 cm-3)

BOX (200nm)

NMOS

(5 m wide P+, 1 x 1020 cm-3)

distance (D) (40 – 2 m)

350m

Threshold voltage

- 0.3

- 0.2

- 0.1

0

0.1

0.2

0.3

0.4

0.5

0 50 100

V_B (V)

Vth

(V

)

256710203040

D

Back bias

Measurement(10MHz clock)

p+ implant (0V) for I/O buffer

MPW06

Much improved !

In

Out

Back bias = 40V

2006/10/31 M. Hazumi (KEK) 6

Circuit-sensor crosstalkCircuit-sensor crosstalkSignals in the circuitry very close to the sensor may inject noise to the sensor.

OK for charge-integrated device.Need some care for other cases

Input

2006/10/31 M. Hazumi (KEK) 7

Implantation parametersImplantation parameters

• ““Deeper” implantation Deeper” implantation mitigates impact ionization mitigates impact ionization (II) and results in a higher (II) and results in a higher breakdown voltage.breakdown voltage.

• ~20% improvement ~20% improvement expected by doing both.expected by doing both.

2m

Ion #1 Ion #2

Vbreak = +88.5V = +102.4V

Find the best ion and beam energy to achieve thehighest breakdown voltage (vital important for full depletion)Find the best ion and beam energy to achieve thehighest breakdown voltage (vital important for full depletion)

Example 1)

Example 2)

2006/10/31 M. Hazumi (KEK) 8

Test structure (strip Test structure (strip sensor)sensor)

StandardNew

MPW06

~20% improvement observed

Measurement

2006/10/31 M. Hazumi (KEK) 9

Guard ring designGuard ring designBetter guard ring design also helpful to improve breakdown voltage.

E [V

/cm

]

1 guard ring (MPW06)2 guard rings (next submission)

40000

20000

d [um]40300 10 20

Bias Ring edge

Bias GuardGuard

60000

80000

100000

Pixels

I/O

VSS Ring

Bias RingGuard Ring

SOI pixel detector

.....

.

An additional guard ringis effective to reducethe electric field concentration.

MPW061 guard + 1bias

MPW062 guards + 1bias

20V at the back side

2006/10/31 M. Hazumi (KEK) 10

Pixel layoutPixel layout

For digital readout, charge sharing curve at the cell boundary should be as steep as possible.

BA

cell A cell B

Note that in our design there are4 p+ implants in one cell connectedin the readout.

1550①

2010

②

③

4

3 17

16

m]x

x2

+:①+:② 　　 +:③

Narrower gap b/wtwo cells ( ) ③slightly better.

MIP-like charge injection with TCADfor the 3 layouts shown below

2006/10/31 M. Hazumi (KEK) 11

SummarySummary

• Back gate effect largely mitigated with additional Back gate effect largely mitigated with additional p+ implants near the circuitry.p+ implants near the circuitry.

• Circuit-sensor crosstalk is not an issue for digital Circuit-sensor crosstalk is not an issue for digital pixel readout with charge integration.pixel readout with charge integration.

• Higher breakdown voltage with improved Higher breakdown voltage with improved implantation parameters (~20% achieved)implantation parameters (~20% achieved)

• Additional guard ring can reduce the electric field Additional guard ring can reduce the electric field by factor ~2.by factor ~2.

• Implantation gap b/w two cells should be Implantation gap b/w two cells should be minimized (present design seems close to the best)minimized (present design seems close to the best)

• Good prospects for thinned fully-depleted SOI pixel Good prospects for thinned fully-depleted SOI pixel !!