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CMOS I C Desig n Flow

The Study of Background Theory

Schematic Level Design

Schematic Level Simulation (Pre-Layout

Simulation) Circuit Layout

Layout Level Simulation (Post-LayoutSimulation)

IC Fabrication & Testing

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CMOS Lay ou t

Schematic Capture Real IC Structure

What will we do during the Layout Procedure?

Drawing the layout of your circuit

Design Rule CheckCircuit and Parasitic Extraction

Post-Layout Simulation

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Ho w t o st ar t w i t h l ay o u t ..

The Study of CMOS Structure A Copy of Layout Design Rules from IC

foundry

Familiar with the Design Tools

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Po ly - Si l icon CMOS Self-Alignment of Source, Drain and Gate

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Po ly - Si l icon CMOS p-substrate CMOS Structure (Cross Section)

Usually we study CMOS structure with its cross

section, How about the plan view?

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Po ly - Si l i con CMOS p-substrate CMOS Structure (Plan View)

Why we need to study the plan view of a CMOSProcess?

The Layout Process is done in plan view

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CMOS Lay ou t

Using Cadence Virtuoso Layout Editor

The Drawing Sequence of Layers is arbitrary

The Layout of PMOS and NMOS is nearly the

same, with a little difference The mask definition for different technology is

different

We use AMS Tech CUP 0.6um CMOSTechnology in this course

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CMOS Layo u t ( PMOS 6 / 0 .6 )

1. Choose the POLY1(dg) layer, with the helpof ruler tool, draw a rectangle with size 6 * 0.6um.

Defining the poly-gate of the PMOS

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 2. Choose the layer CONT(dg), check the minimum

distance between POLY1 and CONT and theminimum DIFF enclosure of CONT from the DesignRule, Draw some CONT on the layout editor

CONT create some holes on the oxide layer formetals contact with the active area

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CMOS Layo u t ( PMOS 6 / 0 .6 )

3. Choose the layer DIFF(dg), draw the active area

on the layout editor.

This step defines the active area of the PMOS

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 4. Check the minimum POLY1 extension of DIFF, use the

stretch tool, modify the size of the poly-gate to fit therequirement.

The minimum extension mainly overcomes the misalignment ofmasks to avoid failure of device.

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 5. Choose the MET1(dg) Layer. Check MET1 minimum

enclosure of CONT from the design rule, draw two metal stripon the layout editor.

This step tries to use the metal 1 layer to connect with theactive area of the PMOS.

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 6. Choose the PPLUS(dg) Layer. Check the minimum PPLUS

extension of DIFF, draw the PPLUS implantation mask.

The area with PPLUS layer will be implanted to p+ region toensure ohmic contact between the metal and the substrate.

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 7. Choose the layer NTUB(dg), check the minimum NTUB

enclosure of PDIFF from the design rule, draw a rectangle inNTUB layer.

PDIFF = the overlapping area of PPLUS and DIFF

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 8. Choose the Layer FIMP(dg), draw a rectangle exactly

overlapped with NTUB.

The two layers NTUB and FIMP together forms the NWELL forthe PMOS. These two layers must be exactly overlapped.

FIMP

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CMOS Layo u t ( PMOS 6 / 0 .6 )

(Note: Step 9 Step 10 trying to draw the bulk pin ofthe PMOS, with the assumption that the bulk is connectto the source of the PMOS. If the bulk is not connectedto source, you need to separate the DIFF of the contact

to the PMOS)

9. Check from the design rule for the minimumPDIFFCON spacing to NDIFF, use the ruler to mark thisposition.

PDIFFCON = CONT over PDIFF region

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CMOS Layo u t ( PMOS 6 / 0 .6 ) 10. At the position located by step 9, draw a substrate contact

formed by the four layers MET1, CONT, DIFF and NPLUS.You need to check the distance requirements from the designrule.

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CMOS Layo u t ( PMOS 6 / 0 .6 ) The last thing we need to connect the POLY gate with

MET1

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CMOS Layou t ( NMOS 6 / 0 .6 )

The Layout Procedure of a NMOS is similar toa PMOS, with the following difference:

No N-Well is needed for NMOS (i.e., no need to

draw the mask NTUB and FIMP)The PPLUS and NPLUS implant is exchanged

i.e. PPLUS region NPLUS region

NPLUS region PPLUS region

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CMOS Layou t ( NMOS 6 / 0 .6 )

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CMOS Lay ou t

The size of the transistor is defined by theoverlapping area between POLY1 and DIFF.

Difference between NMOS and PMOS in a p-

substrate n-well process:

1. PMOS requires a n-well, while NMOS not.

2. The bulk pin of all NMOS in the same die is thesame potential, while PMOS is not.

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Design Ex am p le : 2 t o 1 MUX Step 1: Schematic Level Design

F = A*S + B*NS

NS = S

Al l PMOS and NMOS s ize are 6 / 0 .6

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Ex am p le: 2 t o 1 MUX

Step 2: Layout Design

We have PMOS and NMOS ready in previousslides.

How to connect them?

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Ex am p le: 2 t o 1 MUX

Simply connect your nets use either POLY1 orMET1.

If the connection cannot be done, then youmay need MET2, MET3 or even more layers.

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Ex am p le: 2 t o 1 MUX

Complete Layout

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Run DRC

DRC (Design Rule Check) Choose Assura Run DRC a DRC

window will pop up.

Use default setting and press OK. It will pop up Progress Form, press OK.

The region which cannot passed DRC willbe displayed with shining crosses.

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Run LVS

LVS (Layout vs. Schematic) Before run RCX, you must run LVS to enable

extract the RC Parasitic Choose Assura Run LVS, use the

default setting in the pop window and press OK Press OK or Yes in the following pop windows You can get the LVS debug window. Or you can

browse the choose Assura

LVS debugENV or LVS Error report

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Run RCX (Parasitic extraction)

RCX (Resistor Capacitor eXtract) meansParasitic extraction

You can choose Assura Run RCX, usethe default setting in the pop window and press

OK (you can choose the Rule Set as Typical orWorst Case by your requirement) It will generate the new view named

av_extracted You can open the av_extracted view and press

F to show data in this view.

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Post layout Simulation

You will apply the symbol to simulate yourdesign.

Choose the Setup Environment in AnalogDesign Environment. And in Switch View Listadd the av_extracted that created by the RunRCX at the preview step.

Other sets are same as the pre-layout simulation

Then you can get the simulation result of thedesign.

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Example2: inverter (schematic)

Inverterschematic

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Example2: inverter (layout)

Inverter layoutYou must add the pins

of OUT, IN, VDD, GND

by the layer of PIN M1

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Example2: inverter (Run DRC)

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Example2: inverter (Run DRC)

In Error layer Window, you can see theerror list, and choose to the error place.

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Example2: inverter (Run LVS)

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Example2: inverter (Run LVS)

It will pop the somewindows

The LVS ENV can see theLVS errors

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Example2: inverter (Run RCX)

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Example2: inverter (Extracted view)

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Example2: inverter (Post layoutSimulation)

Test design example

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Example2: inverter (Post layoutSimulation)

Note: addav_extractedin Switch

View List

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Example2: inverter (Post layoutSimulation)