symbolic layout

7/22/2019 Symbolic Layout

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Symbolic Layout Compaction ReviewDavid G. BoyerBell Communications Research331 Newman Springs RoadRed Bank, NJ. 07701

Abstract: Symbolic layout and compaction is reacbin8 a mature status.l%is is demonstrated, n part. by the recent or imminent introductions of anumber of commercial symboIic layout and compaction systems. The twomost frequently used symbolic layout compaction approaches. constraintgraph compaction and virtual grid compaction, are reviewed in this paper.The cummt status of these two approaches s presented by looking at theresults of the ICCD87 compaction benchmark session.

1. IntroductionSymbolic layout compaction research has reached a relatively mature

state. This is demonstrated, in part, by the recent and imminentintroductions of a number of commercial symbolic layout and compactionsystems. This paper reviews the two main approaches to compaction,constraint graph compaction and virtual grid compaction. Constraint graphcompactors typically produce smaller area results than virtual gridcompactors, while virtual grid compactors typically run faster andinherently support abutted hierarchy. The first section in this paper reviewsleaf cell compaction. Hierarchical compaction and pitchmatching am nexttiewed. followed by a discussion of the ICCD87 compaction benchmarksession. The paper concludeswith a summary.2. Lfaf Cell Compaction

Symbolic layout systemswith compaction are used o create full customdesigns in a processndependent fashion. Symbolic contacts, wires, andtransistors are used to represent the different circuit elements of the targettechnology. A designer uses symbolic circuit elements rather thao maskgeometries to create his/her design. A compaction program is responsiblefor creating the mask level description of a circuit. It spaces the circuitelements according to the design rules of a target process which aretypically kept in a technology tie. The compactor can compact a symboliccell fo r a new fabrication process simply by using a new technology file.Consequently, a designer does not usually have to redesign his/&z cinxdt totake advantage of a new fabrication process. Tracking an evolutionaryprocess change can be done n as ittle as a day or two mY86].Symbolic layout and compaction have been active areas of researchover the past lifteon years [AKBIO] and although virtual grid and constraintgraph compaction are the main techniques used today, quite a few otherapproaches have been tried Some of these are - the SLIM system[DUN801 which combines a shear line algorithm LAKE703 with theconstraint graph approach, the two dimensional approach of Watanabe andKedem -841 which uses a mathematical optimization technique tosolve a two-dimensional constmint graph, and the local two-dimensionalapproach of Wo lf [wOL83] which minimizes the area iu a preferreddirection. A simulated annealing approach was recently reported byMosteller @iOS87] which is a 2-D compaction approach that produces acurvilinear (non-Manhattan) ayout.2.1 Constraint Graph Compaction

The CABBAGE @SU79] compactor of M.Y. Hsueh s the most widelyknown comtra int graph compaaor. I&. first repotted graph basedapproach was by Cho [CHO77]. III the constraint graph approach thedesigner typically places circuit element symbols on a fine grained physical

grid. The compactor brings circuit elements as close together as design rulespacing requirements will allow. Some constraint graph compactors canalso push apart circuit elements that are too close together. Locations aretypically given to each circuit element. Some constraint graph compactors,however, group together circuit elements whose center lines share he samephysical grid line, aad who are connected geometrically (electricallyconnected) aud give the groups locations. Constraint graph compactors areone-dimensional compactors and require at least one X compaction passand one Y compaction pass.2.1.1 Constraint Graph Generation The lint step necessary n constraintgraph compaction is to build a directed constraint graph for tbe circuit. Thenodes of the graph represent the circuit groups and the edges in the graphconuect groups that have potential design rule spacing requirements. No te,that if groups were not being used there would be a node in the graph foreach circuit element. The weights of the edges anz the minimum spacingnecessarybetween two nodes (circuit groups).The building of the constraint graph is the most time comuming part ofconstmint graph compaction and is, in the worst case, O(s). There is anedge between every pair o f nodes n a worst case ccmstmintgraph. Only asmall subset of the potential edges are actually needed for constraint graphcompaction. A circuit element group typically will only have spacingrequirements with its nearest neighbors. Many techniques for efficientlygenerating the constraint graph have been proposed Some of these will bementioned below.One of the beat known techniques for building a constraint graph is theshadow-propagation method [HsU79] used in CABBAGE. This appmacbtrims the sarcb space by only checking mask edges that e covered by ashadow that is caused by shining an imaginary light fium behind thegroup under consideration figure 11. An edge is created n the circuit gmphbetween a group of circuit elements and the given group if the shadow fallson the group of circuit elements. l%e shadow-propagation method has anaverage complexity o f O(N*.s) [HSU79]. Note that the shadow s one-half adesign rule bigger (for most graph based approaches) than the element inorder to account for diagonal constraints. This leads to mter &anminimal Euclidean spacings since an enlarged mctaugle is used to accountfor corner intemctions. ibis appears o be strictly an implementation detailand not a restriction o f the constraint graph approach.A number of techniques exist that matly improve the efficiency ofcoustraint generation and result in run times approaching O(NlogN), whereN is the number of edges. A bitmap technique is used by [I-IED 85] and istechnically still O( @) but the actual time taken is reported to approach

Agure 1. As x-shadow is blocked by B [REI87]. Ihere will be an edgebetweenAandBiotheconstraintgraphandtherewillnotbeanedgebetween A and C.25th ACM/IEEE Design Automation Conference@ Paper 26.1Ct-l2540-3/88/0000/0383$01 .OO0 1988 IEEE 383


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O(N). excluding time to sort the edges. The intervening group methodincrementaRy generates the constmint graph. This method effectivelyshadows vertices in the graph when a pair of vertices are coostrained toremain far enough apart F;IN84]. A combination of shadowing and Ibinningis used in [CR0871 which has worst case complexity of O(Nt.r). lbeperpendicular-plane-sweep method of Lengauer LEN831 was generakedby Burns IBUR87] resulting in coustmiut graph generation whichapproaches O(NlogN). AR the above techniques also attempt to minim&ethe number of edges in tire graph because a stmightf~ard implementationof the shadow-propagation method leads to the generation of marryuunecessary edges.

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Ihe approach used by Kingsley [KIN821 is similar to Schielesalgorithm [SCH83] which pulls back elements that are not on the criticalpath as far back as they can go. The different wiring layers of thetechnology are given different weight factors, so that the diffusion layers,for example, are m nimized preferen tially. This approach is iterative innattlte.The method employed by Varadarahan in [CROSI ] uses a non-iterative,event-driven algorithm to minimize the wire length. Groups of circuitelements wilt have preferential upward movement due to a wire connectingto it from above that needs its length to be minimized (wire widths areconsidered in this process as well as wire layers) [figure 51. The group ismoved up until it is stopped by another group. These groups are merged ifpossible and move up together. When the merged group is stopped thecomposite group will be broken up and if the top group is not con&mined itwilt continue upward if it has a preferential upward movement. A gtobatoptim um is nzported for this work and near linear run times are achieveddue to its non-iterative approach.

Figure 5a. A cell after compaction[CRO87].Rgwe 5b. Group B is moved upand it forms a new group withGroup A.

Figure 5c. Group C moved up. Figure Sd. New Group A formedby Shearing.2.1.6 Zone Refining Compaction The one dimensional constraint graphapproach is enhanced and generalized in the ZORRO Zone-Reliningapproach in [SHI86]. Lateral movements are permitted in ZORRO, leadingto locat twodimension24l compaction. The lateral movement of elementsserves to shake ind ividual components into more dense con6gurat ions[figure 61. ZORRO .%uts with the compacted results of a celt and proceedsto optimize these msults. ZORRO maintains dual X aud Y graphs tosupporl the vertical spacing as welt as the laterat movement of the groups.The Zone-Relining approach gives denser layouts than one-dimensionalcompactors because it has more freedom in moving individual components.2.2 Virtual Grid Compuction

Viial grid layout is a structured approach to symbolic designWSl] . The virtual grid is used to establish the relative placement ofcircuit elements and does not correspond to a physical grid [figure 71. Inthe virtual grid approach the compactor gives locations to the virtual gridlines, not to the circuit elements themselves. This imposes an arbitraryc&t on a virtual grid design: alt elements that fall on a virtual gr id mgiven the same location.

Figure 6. (a) Intermediate compaction results. (b) Corresponding conshaintgraph. (c) Box C is selected to be moved aud three candidate locationshave been identified. (d) Result of moving box C and in (e) the updatedconstmint graph [SHI86].Virtual grid compaction begins by 6rst examining spacings in onedirection only (we will use the X direction as the 6rat compact ion pass).Each X grid line is compared with parallel ne ighbotig X grid lines forspacing requirements. A spacing is required with a neighboring X grid ifelements on two neighboring X grids have the same Y coordinate value.The 6nal spacing of an X grid will be the greatest spacing it hasencountered with respect to its parallel neighbors. In onier to accommodatespacings that exert their influence over a number of symbolic grid lines,backtracking must be done. The grid tine to he placed is compared topreviously placed columns until the distance between the current columnad the prior column exceeds some worst-case process value.During Y compaction (the secoud compaction pass) comer spacings ateaccommodated. An element being placed during Y compaction is spacedagainst diagonal neighbors w ithin the worst-case process window as well asagainst its adjacent neighbors. Alt diagonal spacing requirements arehaudled duringthe second compaction pass.

14@p#-~~@+...-~- 7-------T--

Rgme 7. Virtual Grid Symbolic circuit.

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2.2.1 Fence Compoctiun Fence compaction POYSS] eliminates the needto do backtracking in a virtual grid compaction and is linear in nm time.The fence compaction technique is similar to the shadow-propagationmethod discussed above. lbe fence algorittau, in effect, combines thegraph building step with analysis of the critical path. The virtual grid limitsthe potential locations of the symbolic elements. Ibis permits the use of apicket fence da ta sttuctum for each grid tine.A picket fence data structure records the last placement of each layerfor the given process, ami thereby keeps tracJr of the necessary parallelneighbor information. There is a fence data structure for each Y grid line.Each fence, in turn, has one picket for each layer of the process that isbeing compacted for. Each picket comains a rectangle tha t represents thelast placement of a rectaugle of the cmmsponding layer along the fencestructures grid line. The contour of a given layer is captutud by the picketsfor that layer.

Dming the second compaction pass Y grid lines ate placed in much thesame way as grid lines were placed during X compaction. Jn figme 8 thecontour of the aluminum layer (the contems of the aluminum picketscontributed by aJl the fence data stmctmm) is depicted for the Ycompaction of the circuit found in figum 7. Diagonal constraints amhandled du ring this compaction pass and the actual Rucltdean distances forthe cornem being spaced ate used.

ygrid-4

Hgure 8. Y virtual grid 4 is being placed with respect to the alumhu rmfence. The fence. outline conesponds to the already placed abuuinumlayers.

2.2.2 Split Grid Compaction A split grid compactor starts with a virtualgrid layout. Ibe virtual grid is retained to organize the topology of thecircuit. The grid lines ate split apart into distinct circuit groups which areco&ctious of circuit elements that lie on the same grid line and areelectrically connected. The compactor gives locations to groups of circuitelements rather than virtual grid lines. Split grid compaction is a hybridapproach to compaction; it retains the simplicity and speed of virtual gridcompaction and produces area results that am similar to those produced bya graph based compactor. A number of approaches have been used for splitgrid compaction [NyL87] [KOL86] @OY87a].In the approach presented in cNyL87], groups sm identified and placedas close to the fence as possible. Upper bound constraints am handled forthe element rectangles in this approach by using layer decoupling. Layerdecoupling allows wires and contacts to slide with respect to a groupscenterline (contacts ami wires can be offset).

Virtual segments am used in the approach presented in [KOLJ?6], ratherthan virtual grids. Placed circuit groups ate sorted by location in a doublylinked list in increasing order. Ihe placement of a new group is determinedby spacing the sew group with respect to the groups in the doubly Linkedlist in demeasiug order. The group is spaced with ah groups until thedistance between the group and the fixed location of a previouslycompacted group is large enough to accommodate a worst case design rule.Near linear run times ate reported for this work [KoL86]. Automaticelement offsMing is ills0 done with this approach.A modified picket fence data structure is used in pOY87a]. Atopological data structure is used to facilitate nearest neighbor access. Fasgroup identification as welt as fast compaction is possible since nearesneighbor iuformation can be obtained in constant time. The X compactionpass is similar to the X compaction pass presented above for virtual gridcompaction except that gtoups are being placed instead of virtual grids (thefence structure is the same for both). During the Y compaction pass there ioue fence structure for each X group (not each X virtual grid). Y groupplacement is similar to Y grid placement. Run times as fast as thosreported for a virtual grid compactor and area results as small as thosproduced by a constraint graph compactor have been reported for this workPOY87al..3. Hierarchical Compaction/Pitchmatching

The majority of the hierarchical compactors presented in the literatuream hierarchical pitchmatchem [MN841 pNT85 ] m86]. In this paper thterm hierarchical compactor will refer to programs that can compact element/modtde with respect to other elements/modules aud wires. Theelements/modules ate fixed in size (they are not stretchable). Programs thastretch cell so they can be abutted to each other will be referred to apitchmatchers.3.1 Pitchmotching

Both cons&m graph compaction systems and virtual grid systemssuppm t pitchtnatohing. The common approach for both techniques today isto use a comurtdnt grr@ for the pitchmatching process. A number of otheapproaches have been tried with virtual grid pitchmatchers, including linearpmgmmm ing teclmiques, simulated amsealing , and a variety of heuristicapproach [ACK831.* virtual grid concept extends nalumlly to a pitchmatchingenv&nmm l. Abutmen t points are identified between two cells when theshare a common viatual grid (the edges of the two cells fall on the sam&tad grid line) and when one or both have symbolic etements on thcommon bcsmdary. Cells are permitted to have coincident edges, but theare not permitted to overlap. The virtual grid helps to identify thpit&matching points in a module aud identities the connection points ineighboring cells that need to be aligned.

lhem ate basicahy four steps that must be done in order to pitchmatch module. The 6rst step is to compact the leaf cells to be pitchmatched ttheir minimal size. After a ceil is compacted the abutment points aridentified and a parent constraint graph is ~0nstruUed. Once the parengraph is created it is then solved using the same longest path dgOfithm thawas used in the leaf ceg compactor. Ihe cells pitches are matched by thprocess. The pit&matched port locations are then fed back to the leaf 0ecompactor rand all the leaf cells are recompacted with the pitchmatched polo&ons as fixed constraints. After cells are pitchmatched they are tinallyplaced.

One of the most active areas of research in constmint grappit&matching has been with cetl abstraction. The celt abstraction inckrdetwo COIII~OIO~~~S,he constraint graph that represents the cell in the parenand the geometric model that is used to place the cell once it has beepitchmatched The most common constraint graph representation is develop a port abstraction graph @IN821 WC861 wOL86] [CRO87]Typically, the transitive closare of the constraints used for the leaf cecompaction is taken [wOL86] and the port abstraction graph results [figur91. Only the vertices that correspond to the ports are retained in the graphwhen a cell. is used hierarchicaRy its constraint graph can be replaced w itits port abstraction graph.

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m@lre 9a. cell collstlaint graph[REIW. Figme 9b. Ports identified

Pigure 9c. Port abstraction BraphThe geometric model typically used is that elements not on a cellboundary are forced to be a half design rule from the. cell boundary. Thisinmes that when two cell edges are abutted , the elements tha t do not fall onthe cell edge will always be design rule correct with respect to theneighboring ceil. This approach can be very expensive because elements

that contain diftkion must be kept far enough from the edge iu order topermit the opposite diffusion type iu a neighboring cell. The schemedescribed in [TAN871 does not require this half design rule spacing.Another approach is to include some of the elements around the edge of acell in the port abstraction (a donut [RE186]) so tbat an accurateplacement of cell edges can be made [figure lo]. The most generalapproach is the approach used by Bums PUP871 that creates protectionthmes for a cell. This is discussed in detail beiow.The ZORRO compactor uses a tkee step hierarchicalcompactioslpitchmatch ing process. The core of a cell is compacted whilemaintain ing a terminal frame that has the terminals located at apredetermiued pitch. The compacted cell is then assembled with itsneighbors (the terminal frames have been designed so that neighboring cellswill abut). Tbe final step in the process is a compaction at the next level ofthe hierarchy where the cell cores are treated as tixed clusters. The terminal@tunes and other wires are compacted at this stage [SHI87]. This approachis a hierarchical compaction approach with river routing to take care of tkinter cell f2Jmuecliolls.

3.2 Hierarchical CompactionA hierarchical compactor can space fixed sired modules/e/elements withrespect to other modules/elements lJ3UR87] pAU32]. In W approachUtOEA Contads, and modules axe treated in the same mmtner. Ihey areali treated as cells and receive one. vertex in tbe constraint graph regardtessof the number of layers and terminals that comprise them . Arbitraryrectiliuear polygons cau be accommodated in SPARCS [BUR86] and noveldevice shapes, as welt as analog parts, can be used with th is approach. Tofacilitate hierarchical compaction, a cell abstraction is generated thatconsists of protection frames t&El&I] and terminal frames [figure 111. The

protection frames for a cell hide the details of a cells layers and representthem by bounding Manhattan polygons. The gmunlarity of these polygonsis adjustable by the user. Terminal frames represent connection areas oneach layer. The terminal frames and the protection frames are sufficient todescribe tbe cell in the hierarchy ami serve as the cell abstraction. Ihepower in this approach is in the abitity to handle device shapes sod analogdevices not traditionally found in symbolic layouts, as welJ as being able toaccurately space adjacent modules [fignre 121. SPARCS csn also handleanalog devices requiring symmetry using active constraints @UR86] .

Figure 11. Cell dehnition and abstraction @UR87] .

Rgure. 12. Two modules spaced by SPARCS (BUR87J.l3gum 10. The constraint graph for a cell to be pit&matched showing thedonut abstractions W86].

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4. Compaction Ben&ma&Ibe author conducted a benchmark session at the ICCD87 conference

pOY87b]. IBe purpose of this session was to compare the performauce ofdifferent compact ion approaches. For the details of the benclnna tkingprocess see [BOY87b] and @3OY87c].4.1 Benchmark Results

Four compactors participated in the session. The MACS compactorwhich [CR0871 is a constraint graph compactor that does automatic jogirtsertion and wire minimixation, the ZORRO [SHI87] and SIARCS[BUR87] compactors which were discussed above, and the Spnbolicsvirtual grid compactor FAN871 which does automatic contact offsetting.The results produced by the compactors were checked for design ruleviolations as well as netlist inconsistencies lBOY87cl. Ibe strengths andweaknesses of the different approaches can be found horn these results.The most noticeable result of the compaction benchmark session wasthe benefit of introdu&g jogs in the compacted layout. The compactorsthat iatrodnced jogs ia wires consisteatly produced smaller areas than thosethat did not.The MACS compactor [CR0871 is a constraint graph compactor thatiatroduces jogs along the critical path in the constraint graph. The processis iterated on the critical path until there ate no wires on the current criticalpath, or there is not enough room to introduce any jog for wires on thecurrent critical path. MACS redetetmines the critical path after each jog isinserted in an incremental, event-driven approach. The h%ACS compactorproduces very good area results quickly with the use of event drivenalgorithms. It also effectively minimizea wire length. The MACScompactor, however, requites a large amount of memory. MACS also wasnot capable of pit&matching modules with arrayed instances at the time ofthe benchmark session.Ihe ZORRO compacto r [SHI87 ], overall, produced the smallest arearesults. Ibis was achieved by using the local twodimensiona l compactionwhich resulted ia the introductJon of many jogs in wires. The draw back tothis approach is the long ran time that is required.The Symbolics compactor is a virtual grid compactor that automaticallyoffsets contacts. The streng ths of this compacto r ate its speed and its abilityto handle large designs. It was the only compacto r that participated in thesession that could compact the 16x16 multiplier. The symbolics compactorwas also used in the design of the 390,000 transistor Symbolics ivory LISPProcessor [BAK87].The SPARCS compactor is a hierarchical compactor that is designed tocompac t modules that consist of f&d modules of varied shapes and wires.An example should have been included in the benchmark set that was ablock style layout to demonst rate th is. A block style layout is a cellcomposed of modules of 6xed and varied sizes connected with routingwires. The abutted cells in the benchmark set had to be pit&matched byhand for SPARCS to compact them. The results produced by the SPARCScompactor were good and the efficiency of its hierarchical approach is seenby its fast run times.

S. ConclusionThere is currently a resurgence of interest in symbolic layout audcompaction with the recent or imminent introduction of a number ofcommercial symbolic layout systems @CAD, SDA, SCS, etc.). Symboliclayout and compaction has reached a relative1y mature stage; compactedresults can be generated quickly and the compacted areas are quite good.The advantage of introducing jogs in wires can be seen from the results of

the ICCD87 compaction benchmark session. While compaction isrelatively mature , there ate still many areas that ate actively beingresearched. These areas include reduct ion of compaction run times,improved area efficiency, wire minimization. enhanced pit&matching audhierarchical compaction schemes, and compaction for circuit perfomuauce,6. Acknowledgements

Deborah Rappaport assisted in preparing tbis paper in her usual expertfashion. I also would like to thank Jeff Burns for his comments andcorrectioas, his insights were very helpful and timely.

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Example~-Compactor-= afaMACSSPARCSSymbolicszorro~- afavg~-MACSSPARCSSymboliaszotlu___-Cl32~-MACSSPARCSSymbol&zkro___-mul2x2~-MACSSPARCSSymbol&

mttl4x4~-SPARCSSymbol&lzurro~-mttRtxl?___-SPARCSSymbol&ZAXTO~-mttD6x16~-Symbolics~-

Area CPU Memory(microns) w-4-143 x 166=23738 9 145QK157 x 180=28260 11 356K160 x 189=30240 52 164K140.5 x 171=24025.5 430 647K142x145=20590157x151=23707154 x 154=23716128.5 x 151=19403.5627 x 354=221958685 x 339=232215675 x 330=222750660~3223212520309 x 252=7786a 16 205OK343 x 255-87465 47 215K370 x 270=99900 10 512K312x252=78624 838 614K649 x 601=390049 66 754K654 x 638A17252 54 840K577 x 577.51333217.5 1904 741K1285 x 1285=1651225 89 2066K1276 x 1352=1725152 245 32OOK1138 x 1207.5=1374135 11738 7754K2524x2780=7016720 1 1073 ) 14400K 1

Table 1. Compsctioa beacbmti results. The area is in microns square preceded bthe x and y dimension. Run times for the compactoru are reported for running onVAX 8650. The memory usage is the peak memory needed for a g&n comp+ztto compact an utampk. No two netlists for the Cl32 example wcpc the same.

7. References[ACK83] B. Ackland and N. Weste, An Automatic Assembly Tool foVittual Grid Symbolic Layout, Proc, VLSI 83 (Trondheim), pp 457-466Jan. 1983.[AKEI70] S.B. Akers, J.M. Geyer, and D.L. Roberts, IC hIask Layout witha Sit& Conductor Layer, Pmt. of the 7th Design AutomationConference, pp 7-16, June 1970.IBAI.821 M.W. Bales, Layout Rule Spacing of SymboIic IntegratedCircuit Artwork, BRL Memo No. UCB/ERL M82/72, Univemity o

CaIifomia, Berkeley, May 1982.lBAK87] C. Baker et al. The Symbolics Ivory Processor: a 40 Bit TaggeArchitecture Lisp Microprocessor, Proc. of the IEEE IntematiomdConfereace oa Computer Design, pp 512515, Sept. 1983.[BOY831 D.G. Boyer and N. Weste, Virtual Grid Compaction using thMost Recejmt Layers Algorithm, Proc. of the IEEE InternationalConference 1011omputer-Aided Design, pp 92-93, Sept. 1983.[BOY87a] D.G. Boyer, Split Grid Compaction for a Virtual Grid SymbolicDesign System, Proc. of the IEBE International Conference on Computer-Aided Design, pp 134-137, Nov. 1987.


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