CHIPS

Subu Iyer (s.s.iyer@ucla.edu)

Three questions

• What are we trying to do ?

• Why are we doing this ?

• How are we planning to do this ?

What are we trying to do ? Develop an “app-like” environment for Hardware that can • Cut the time to market by 5-10X

• Cut the NRE cost by 10-20X

• Allow extreme heterogeneity including

extensions to cyber-physical systems

• Develop a sophisticated manufacturing workforce

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Why now ?

• The application space is transforming • CMOS scaling is saturating

• Systems are getting more heterogeneous

and complex

• Holistic system Integration is the next frontier of Moore’s law

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Computing is transforming

Manycore

Mobile sensors + processors Cognitive

storage

Persistent slower

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“cognitive” computing – brawn Vs. brain

It is unlikely that we can just scale our selves out of the huge gap (103 to 104) in power and interconnect density

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1964 - Transistor SLT module 6 transistors, 4 resistors

2014 22nm CMOS Tech.The Power of System on a Chip (SoC)

2014 – POWER8 Processor 22nm SOI eDRAM technology, 650mm2 12 cores and 96MB of on-chip memory 4.2 billion transistors

Transistor scaling has made this possible

But as SoCs have gotten more complex • NRE costs have skyrocketed • Time to market has become huge • Manufacturing costs have grown • and yields have plummeted Courtesy IBM

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What would Yogi Say ?

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Do we need Packages ?

Epoxy /glass Board CTE = 16-20x10-6 /oC

Packages are supposed to: • Protect the chip – mechanically and thermally • Connect the chip electrically to other chips • Allows mission mode testing of the chip

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Do we need Packages ? – No!

Epoxy /glass Board CTE = 16-20x10-6 /oC

Packages are supposed to: • Protect the chip – mechanically and thermally (not really) • Connect the chip electrically to other chips (by progressive fan-out) • Allows mission mode testing of the chip (this is true)

We can scale the package by getting rid of it And mount the bare die directly on the board

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Shrinking the board

• Without question the smallest board is a single large die with all the system functions on it

• Hence the quest for the largest Yieldable Unit – the SoC (reticle size today will yield at 3-15%)

Gene Ahmdahl @Trilogy Systems

Amdahl eventually declared the idea would only work with a 99.99% yield, which wouldn't happen for 100 years.

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Evolution Of System IntegrationSy

stem

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orm

ance

Integration

Stacked Die

Module onInterposer

“Prehistoric”

Now

Future

Interposers/BoardsOrganic –> Si-> glass

Stacked memoryWafer stacking

Massively integrated Silicon-like Board

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Mega SoIFs by re-integration on an Interconnect Fabric

>100 �m pitch Mass reflow

100�m >pitch > 40 �m Mass re-flow+TCB

h > 40 0h > 40

The ”right” interconnect fabric • Mechanically robust (flat, stiff, tough…) • Capable of fine wiring, fine pitch

interconnects • Thermally conductive • Can have active and passive built-in

components Silicon Fits the Bill in many cases

Full contact – TCBProximate • Inductive • Capacitive

Challenges: • Warpage • Topography • Assembly /Thru’put • Thermal

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Wafer to Wafer integration at tight pitch

4-layer wafer stack w/ 2.5 �m Pitch

Handle Wafer

Strata 1

Strata 2

Strata 3

Strata 4

DRAM Scaling also slowing New Failure Modes

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Highly interconnected Microsystems 2.5 �m PPPPit

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DRN

CHIPS Framework

Integration A processing facility for Interconnect Fabric (IF) & assembly

•Silicon processing •Glass •Flexible substrates •Additive manufacturing •Thermal compression bonding •Wafer thinning •Wafer-wafer integration

Applications & Architecture

Heterogeneous Systems Approximate Computing

Cognitive Computing Fault Tolerance

Supply chain Integrity Security

Memory Subsystems Processing in Memory DFT

Network on Board

Materials Fine Pitch Interconnect Substrate Materials Warpage, Stress Flexible Materials Thermal solutions Materials for Additive Mfg. Reliability

Devices/Components Novel switches New memory MEMS Sensors Passives, antennae Medical devices

Design Infrastructure

Thermo-Mechanical Electrical

Tools Partitioning

DFT Active IF Design

Tier 1 Equipment Partners

New Tool Concepts Tool Development

Scale-Up

Tier 1 Foundry Partners

Si, Compound Semis, MEMS, and OSATs

gration

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Test Beds

“Mega SoIF*” (~ wafer dimensions)

Desktop Datacenter

autonomous origami �-Yodabot that thinks, walks, flies, swims and does stuff….. *System on Interconnect Fabric

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Fabric

Chip Assembly

Summary • We are in the midst of a significant hardware

transformation • Semiconductor Scaling is saturating • Computing models are changing • Systems are getting more heterogeneous • SoCs design costs and Times-to-Market huge

• CHIPS will drive a much more holistic Moore’s Law

• We can’t do it alone, we have to do it together

• Industry Partners • University Partners: GINTI (Tohuku U),

Binghamton U, Georgia Tech, • Government Agencies

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