smartspice & utmost models and features - silvaco · latest model improvements in smartspice...

SmartSpice & UTMOST Models and Features

2004 Development

Latest Model Improvements in SmartSpice and UTMOST

Agenda

New trends in model development Improvements in existing models RPI Vertical Cavity Surface Emitting Laser model TFT models Simulation issues Outlook on future models

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Agenda


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New Trends in Model Development

Surface potentials High-frequency modeling New modeled effects :

Shallow-Trench Isolation (STI) Source / Drain asymmetry Self-heating Noise improvements

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Surface Potentials

Old” models based on Threshold voltage Vt : Need transitions between operating regions ➩ Issue at moderate inversion

➩ Smoothing equations & parameters

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Surface Potentials

Recent models, based on surface potential Φs : One equation for whole operating range Iterative (HiSIM) or approximated (MOS11) solution

➩ Accurate transitions (weak to strong inversion), No empirical parameters

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S G D

φS0

φSL φS0+Vds

B


High Frequency Modeling

RF design generally uses table look-up models. It lacks :

Efficiency Scalability Predictive ability Simulation of a whole system (SOC)

Need for compact models aimed at RF simulation

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High Frequency Modeling

What compact models need to fulfill the RF designers requirements : Intrinsic input resistance (depends on channel length & bias) Extrinsic resistance (gate electrode and bulk) Accurate thermal noise description NQS model Continuity of high-order derivatives (for distortion)

➩ Various models add equations dedicated to RF : BSIM4, HiSIM 2.0 (not released yet), BSIM-SOI v3

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New Modeled Effects

New effects are now included in every recent model : Shallow Trench Isolation Source / Drain asymmetry Self-Heating Noise improvements

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New Modeled Effects: Shallow Trench Isolation

Replaces LOCOS to provide isolation between MOS devices :

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Critical corners

LOCOS

Poly

Channel stop

Bottom device

Top device

Substrate

Trench


New Modeled Effects: Shallow Trench Isolation

Two different approaches HiSIM : Electric field modification new surface potential

Uses 4 dedicated parameters BSIM4 : Consequences of mechanical stress on parameters

mobility velocity saturation threshold voltage body effect DIBL effect

Uses 23 parameters (including geometry and temperature scaling)

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New Modeled Effects: Source / Drain Asymmetry

Symmetry Source and Drain nodes can be swapped without any difference Attention is needed to get correct results near VDS=0

➩ Model has to perfectly account for Source / Drain inversion

Asymmetry Needed for specialized simulation (RF) Process has an influence on source / drain differences

➩ Different parameters for Source and Drain (BSIM4)

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New Modeled Effects: Self-Heating

Self-Heating is a key effect for different technologies : SOI, TFT (because heat cannot be dissipated through bulk) Power devices (because of high voltages & currents)

➩ Need to dynamically compute device’s temperature

Models are connected to a thermal sub network :

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CTH RTH PDISS

DT

PDISS = Dissipated power RTH = Thermal resistance CTH = Thermal capacitance


New Modeled Effects: Noise Improvements

Common flicker noise equation is several years old ➩ Need some accurate equations, depending on technology

Improvements : Charge-based / Holistic equation (BSIM4.3.0) Thermal noise partition between Source / Drain Drift / Diffusion model (HiSIM) BSIMSOI equations based on BSIM4

+ floating body noise

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Agenda: Improvements in existing models


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Improvements in Existing Models

MOS11 v1101 HiSIM 1.2.0 BSIMSOI v3 BSIM4 UFSOI

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Improvements in Existing Models: MOS11 – 1101.1 Improved charges description

New variable ξox : now accurate for large values of body factor k0 is now deduced from

New Gate Induced Drain Leakage (GIDL) effect

(Same for IGISL)

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Improvements in Existing Models: HiSIM 1.2.0

New GISL current, in addition to GIDL Sub-threshold characteristics improved for short-channel devices

PTHROU = correction for steep subthreshold swing

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Improvements in Existing Models: HiSIM 1.2.0

New flicker noise equation Conductances smoothing for high bias ranges:

COSMBI flag Gate leakage current now partitioned (GLPART1, GLPART2 parameters)

New parameter for high-k stacked gates KAPPA = Dielectric constant for gate oxide

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Improvements in Existing Models: BSIMSOI v3 - Level 33

Unified model for PD and FD SOI MOSFETs v3.0 May 2002 Official release

3 versions provided for year 2003 : v3.1 February Beta version v3.1.1 April Official release (default version) v3.2 August Beta version

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In VERSION=3.0 SOIMOD=0 BSIMSOI PD, identical to Level=29 v3.2.2 SOIMOD=1 Unified model for PD & FD

In VERSION=3.11 SOIMOD=2 Ideal BSIMSOI FD, based on BSIMSOI FD v2

No body node, no body leakage/charge calculation

In VERSION=3.2 SOIMOD=3 Automatic selection

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SOIMOD=1: Lower bound of Vbs set to Vbs0

SOIMOD=2: Vbs pinned at Vbs0

SOIMOD=3: Bias independent estimated value of Vbs0 2 parameters : VBS0FD, VBS0PD

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In all versions : Bugs reported to Berkeley and fixed

In VERSION = 3.0 Gate-Channel, Gate–S/D current model ➩ IGCMOD = 1

In VERSION = 3.11 Gate resistance model ➩ RGATEMOD = 0, 1, 2, 3

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In VERSION=3.2 : Noise Model FNOIMOD=0.1 Flicker noise model TNOIMOD=0.1 Thermal noise model Thermal noise associated to Rgate Shot noise associated to igb, igs, igd currents

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Improvements in Existing Models: BSIM4

Release History BSIM4.0.0 released on 03/24/2000 BSIM4.1.0 released on 10/11/2000 BSIM4.2.0 released on 04/06/2001 BSIM4.2.1 released on 10/05/2001 BSIM4.3.0 released on 05/09/2003

BSIM4.3.0 intermediate versions distributed for beta-testing for limited time on December 2001, December 2002, and April 2003

All versions available in the SmartLib : Berkeley compatible versions invoked by LEVEL=14 HSpice compatible versions invoked by LEVEL=54

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Summary of Changes New scalable stress effect model (STI effect) Unified current-saturation model New temperature model mappings for

Saturation velocity Mobility S/D Resistances (TEMPMOD=1)

Enhanced holistic noise model (TNOIMOD=1) Forward body bias limitation function Extension of gate direct tunneling model to multiple-layer gate dielectrics Nine bugs fixed

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Stress Effect Model

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L

W SB SA

LOD

SD

Trench Isolation

Edge

POLY

OD

Contact

node1 node2

node3

node4 node5

node6

node7

A1,P1 A2,P2

A3,P3

A4,P4 W1

W1’

W1”

W2

W2’

W2”

W2’’’

W3

L1

L2

L3 S3”

S5

S6

S1

S3’

S2’ S2”

S4’ S4”

STIMOD=0 : Disabled STIMOD=2 : TSMC model, irregular devices

STIMOD=1 : Berkeley model, β-version STIMOD=3 : Berkeley model, multi fingers



Unified Current Saturation New Ids expression based on approximation of Price’s equation accounts for

Velocity Overshoot Model Source-end Velocity Limit Quasi-Ballistic Transport

Only 4 new model parameters : LAMBDA, VTL, LC, XN

Temperature Model Enhancement New format for Vsat, Prt, Ua, Ub, and Uc temperature scaling rule

Invoked by setting new selector TEMPMOD=1 TEMPMOD=0 invokes BSIM4.2.1 temperature model (default)

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Holistic Thermal Noise TNOIMOD=1 equations : constants replaced by new model parameters

Direct Tunneling through Multiple-Layer Gate Stacks BSIM4 capability of modeling multi-layer gate tunneling demonstrated,

attenuation coefficient already accounted for in BSIM4.2.1 no changes needed in gate tunneling current equations

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Default values of RNOIA / RNOIB ensure backward compatibility with BSIM4.2.1



Forward Body Bias New smoothing function to set an upper bound for the forward body bias

BSIM4.2.1 already has the smooth function for the low bound

Avoid unreasonable values during simulation enhanced convergence properties

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Improvements in Existing Models: BSIM4 - Bug Fix

Bug fix : CAPMOD=1 Cgg

➩ Also affects drain, source, and bulk charges and capacitances

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Improvements in Existing Models: BSIM4 - Bug Fix

Bug fix : Gate Current partition Gate tunneling current saturation with

Vds experimentally verified but not reflected by simulated results

Fix : Igcs / Igcd now expressed as functions of Vdseff instead of Vds

Saturation effect with Vds now correctly simulated with IGCMOD=1 equations

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Improvements in Existing Models: BSIM4 - Other Bug Fixes 7 bugs in BSIM4.2.1 have been also fixed in BSIM4.3.0

Parameters CKAPPAS/CKAPPAD limitation (negative values) Thermal noise error DIOMOD=2 Bulk-Drain diode current equation corrected RDSMOD=0 Rds scaled with NF Gate shot noise calculation swapping Convergence check issue (not relevant in SmartSpice) Qdef in bypass criterion removed (not relevant in SmartSpice)

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Improvements in Existing Models: BSIM4 - Features

Silvaco - specific features Experimental features introduced in beta version of December 2001:

Dynamic Reference Method (DRM) Invoked by DRMOD=1 (default 0) or by specifying DRDELTA

New quantum effect charge-based capacitance model Invoked by CAPMOD=3 (default 2)

Experimental features introduced in beta version of December 2002: Simple stress effect model (STI effects on mobility and carrier velocity)

Invoked by setting SK0 to non-zero value (default 0.0) Reduced set of model parameters: SK0, SK1, SL, SW, K

➩ DRM and old STI model also supported in previous versions of BSIM4

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Improvements in Existing Models: UFSOI 7.5/UFPDB 2.5

University of Florida SOI model (Pr. J. G. Fossum) : FD, PD, and Bulk-Si UFSOI 7.0 : strained Si/SiGe channel option in PD and Bulk-Si models UFSOI 7.5

Released in July 2003 Strained Si / SiGe channel option expanded SOI model applicable to CMOS scaled to the bulk-Si limit

(Lgate ~ 50nm with Leff ~ 40nm)

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0.2 Ge content x in the underlying Si1-xGex buffer layer (DEG no more used)

0.0 - GEX 7.5

0.1 0.0 eV Bandgap narrowing in strained Si channel DEG 7.0

Typical value

Default value

Unit Description Parameter Version


Agenda: RPI Vertical Cavity Surface Emitting Laser model


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RPI VCSEL Model

RPI Vertical Cavity Surface Emitting Laser (VCSEL) model is a single-mode laser diode model

Rensselaer Polytechnic Institute VCSEL model by Pr. Michael Shur et al

Mixed Electronic/Photonic (MEP) simulation: photonic part described in terms of equivalent electrical signal

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Vin I V(I)

Emitter diode

RPI VCSEL model

Optical signal

Optical interconnect

Det

ecto

r

Vout

VCSEL model can be connected to transmission line and optical receiver devices

- full MEP simulation


RPI VCSEL Model

Electrical Diode model level = 1

including : recombination current leakage current self-heating

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Rs

Idiode Ileak Il Cj

Ig

Isp Rp Cp

n+

n-

o

Optical 1st order rate equations of

semiconductor laser


RPI VCSEL Model P-I characteristics :

Node “o” voltage = optical output power (mW)

Implementation in SmartSpice:

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3 terminals

Dxxx n+ n- o …

Diode model : cathode and anode

Optical power output


Agenda: TFT models


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TFT Models SmartSpice provides 4 models :

Leroux model (Amorphous Si, level 15) RPI model (Amorphous Si, level 35)

Berkeley TFT model (Polysilicon, level 16) RPI model (Polysilicon, level 36)

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Source Drain

Glass substrate

Gate Gate insulator

Passivation Intrinsic a-Si

Conducting channel

N+ a-Si N+ a-Si

Gate Drain

Source gate oxyde

quartz or glass substrate

poly-Si n+ n+

SiO2 coating


TFT Models: RPI Polysilicon (Level 36) update

Reference for scaling equations and bug fixes: Pr. B. Iñíguez paper

B. Iñíguez , Z. Xu, T.A. Fjeldly, and M.S. Shur, "Unified Model for Short-Channel Poly-Si TFTs," Solid-State Electronics, Vol. 43, No. 11, pp. 1821-1831 (1999).

Effective parameters now scaled according to Leff ASAT, LAMBDA, MS, MU0, MU1 are replaced with their scaled counterpart:

Select VERSION=2 and set SCALERPI flag

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TFT Models: RPI Polysilicon (Level 36) update

Bug fixes : Systematic use of Eta (including floating-body effects) instead of ETA in

calculations of Vgte and Ns

Corrected Vteff to fit exactly the paper equation

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with


Agenda: Simulation Issues


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Simulation Issues

Improvements made regarding : Voltage Monitoring Compatibility with 3rd party tools

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Simulation Issues: Voltage Monitoring - .BIASCHK statement Syntax (HSpice-compatible) :

.BIASCHK type terminal1=termname1 terminal2=termname2 + limit=val <noise=val> + <name=devname1> <name=devname2>... + <mname=modelname1> <mname=modelname2>...

Silvaco-specific features : Available for all devices (passive and active) New “terminal” names added to offer voltage monitoring of internal nodes .option biaschkmode=0 (default) reports “local maxima” .option biaschkmode=1 reports all points for which |bias|>|limit+noise| .option biaschkmode=2 reports the periods during which |bias|>|limit|

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Simulation Issues: Voltage Monitoring - Example

SmartSpice input deck : .option biaschkmode=2 .biaschk PMOS terminal1=ngp terminal2=nbp limit=0.5

SmartSpice output after running a transient analysis : type terminals time duration model-name element-name ... pmos ngp - nbp 8.3280e-10 2.8300e-09 p m.xnandf.x4.mp1 pmos ngp - nbp 1.2528e-09 2.8300e-09 p m.xnandf.x6.mp1 pmos ngp - nbp 1.6628e-09 2.8300e-09 p m.xnandf.x8.mp1 pmos ngp - nbp 2.0728e-09 2.8300e-09 p m.xnandf.x10.mp1 ... Element that have biaschk out of limit during transient simulation: type terminals Number Count model-name element-name pmos ngp - nbp 2 p m.xnandf.x1.mp1 pmos ngp - nbp 2 p m.xnandf.x10.mp1 pmos ngp - nbp 1 p m.xnandf.x11.mp1 ...

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Simulation Issues: Compatibility with 3rd Party Tools

RSC / RDC device parameters now default to model parameters values MOS level 2,3 : New compatible subthreshold computation (WIC selector) Element template parameters (LVnn and LXnn) are now accounted for in

most models

ex : LV1 returns channel length LV36 returns Gate-Source overlap capacitance LX14 returns gate charge ➩ Improves HSpice compatibility

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Agenda: Outlook on future models


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Outlook on Future Models

New models to come : Double-gate MOSFET Nanocristalline TFT

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Outlook on Future Models: Double Gate MOSFET

Bulk scaling reaches its limit ➩ DG MOS is the most scalable structure to suppress short channel effects

BSIM-DG features : Based on next generation Surface Potential Plus (SPP)

BSIM core Modular (shares equations with bulk BSIM model) Threshold voltage model including :

short channel effect drain-induced barrier lowering (DIBL) quantum mechanical effect back-gate channel coupling effect

Universal mobility model and velocity saturation Symmetric / Asymmetric operation

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Outlook on Future Models: Nanocristalline TFT

Nanocristalline TFT emergence is due to its Cheap process Stability under illumination and bias stress

➩ Need for a suitable compact model

Today only a DC model is available ➩ Waiting for a complete model (DC+charges model) to be released

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References Berkeley models (BSIM, BSIMSOI): http://www-device.eecs.berkeley.edu Philips models (Mextram, MOS11): http://www.semiconductors.philips.com/Philips_Models Mextram Users Group : http://retina.et.tudelft.nl/homepages/mug HiSIM : http://www.starc.or.jp/kaihatu/pdgr/hisim Double-Gate MOSFET : http://www-device.eecs.berkeley.edu/~bsimdg University of Florida (UFSOI) http://www.soi.tec.ufl.edu RPI Polysilicon TFT :

B. Iñíguez , Z. Xu, T.A. Fjeldly, and M.S. Shur, "Unified Model for Short-Channel Poly-Si TFTs," Solid-State Electronics, Vol. 43, No. 11, pp. 1821-1831 (1999).

Nanocristalline TFT : D.Dosev, T.Ytterdal, J.Pallares, L.F.Marsal and B.Iñíguez, “DC SPICE Model for Nanocristalline and

Microcrystalline Silicon TFTs”, IEEE Trans. Electron Devices, vol 49, pp 1979-1984, Nov. 2002.

VCSEL model : J. Deng, M. S. Shur, T. A. Fjeldly, S. Baier, “CAD Tools and Optical Device Models for Mixed Electronic/

Photonic VLSI”, International Journal of High Speed Electronics and Systems, Invited, Volume 10, No 1, pp. 299-308, March 2000.

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