SONy;, CXA 108280/85 I

Servo Signal Processor for CD Player

Description CXA 1 082BO/BS is a bipolar IC designed for the

servo control of the compact disc player. The only difference from CXA 1 082AO/AS is the FZC threshold.

Features • Single power supply, 5 V • Dual power supply, ± 5 V • Low power consumption (165 mW Typ.:

±5 V, 100 mW, 5 V) • Servo functions same as the CX201 08 (focus,

tracking, and sled servo) • Built-in auto sequencer • Built-in LPF for spindle servo • Built-in loop filter and VCO for EFM clock

reproduction PLL • Fewer external parts • Built-in circuit for preventing sled runaway • Built-in circuit for disc defects • Built-in anti-shock circuit • High-speed access using a linear motor • Sharing of the serial data bus of the micro co m­

puter witli the CX23035 or CXD 11350 • Compatible in the upward with the CX201 08

for microcomputer software • The peaks of focus search, track jump, and

sled kick pulse can be set with external resistors.

Functions • Focus servo control • Tracking servo control • Sled servo control • Spindle servo

LPF, drive amplifier • EFM clock reproduction PLL

Loop filter, 8.64 MHz VCO • Auto sequencer

Built-in RAM

Structure Bipolar silicon monolithic IC

CXA1082BO 48 pin OFP (Plastic)

CXA1082BS 48 pin SDIP (Plastic)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

-1-

'E90777B78

SONY

. Absolute Maximum Ratings (Ta = 25°C) • Supply voltage Vee - VEE 12 • Operating temperature Topr - 20 to + 75 • Storage temperature Tstg - 55 to + 150 • Allowable power dissipation PD CXA 1 082BO 833

Recommended Operating Conditions • Supply voltage Vee

Vee

Block Diagram

CXA 1 082BS 1330

VEE DGND

4 to 11 4 to 5.5

12 L DATA REGISTER INPUT SHIFT REGISTER ADDRESS-DECODER

V °C °C

mW mW

V V

1 1

SEQUENCER [ 2 L

OUTPUT DECODER

FS 1 to 4 TG 1 to 2 TM 1 to 7 PS 1 to 3

TGI TRACKING PHASE COMPENSATION

r-----, , , ,

-2-

~ TM7

t TTL

eXA 108280/85

SONY

Pin Configuration CXA 1082BQ

SPDl8

WDCK

TE

TZC

FE

:;: z 0 en

~ :;;

u " > " ~

Pin Description

No. Symbol

2 (8) FGO

3 (9) FS3

a. " " " U <D > 0 '" "' :;; ~ u '"

~~

2

~t'"

. "

3

~

~

0 ~ :;: u Ci > '" a. '"

0 z " ~ ~

" u

o CD f" " ....

Equivalent Circuit

Vee

180 48K

130K ~20PA VEE

Vee

180 46K

r -3-

CXA1082BS

SRCH

TGU

TG2

AVec

TAO

TA8

Sl ffi

SlO

sl8

SSTOP

FSET

SENS

CXA 1 08280/8S

MIRR

WDCK

SPlDO

SPDl8

DGND

ClK

DATA

AVEE

Numbers in ( ) show CXA 1 082BS

Description

Connect a capacitor between this pin and pin 3 (9) to reduce the high-frequency gain.

The high-frequency gain of the focus servo can be changed by switching FS3 ON or OFF.

SONY CXA 1 OB2BQ/BS

No. Symbol Equivalent Circuit Description

Vee

· ~ 40K 4 (10) FLB 4 Time constant external pin for rising low band-

width of the focus servo. · ~

VEE

Vee

5 (11) FED ® ~ " ~>- Focus drive output ~

11 (1 9) TAO 11 ~ .. .. Tracking drive output

@J 14 (20) SLO j 0{' o::.'-l

Sled drive output

39 (45) SPDLO @J 250~ I>'00~A Spindle drive output v,,

Vee

~ ... ~ 180 90K

®-6 (12) FE - Inverse input pin for the focus amplifier.

" ... 40K~; j 2.5~A

VEE

~ee · ~ 180

l-7 (13) SRCH 7 Pin for providing a time constant to generate r-..,

· " 50K ~3.5~At t"~A the focus search waveform.

VE'

Vee

~ " 110K 20K

8 (14) TGU 8 Pin for providing a time constant to switch the tracking gain of high-frequency. -" ,~ 82K

VEE

Vee

· r- >-I" 180 I-' Pin for providing a time constant to change the 9 (15) TG2 9

?- ~2~A · r- 470K high-frequency tracking gain. ,.

VEE

-4-

SONY CXA 1 0828Q/8S

No. Symbol Equivalent Circuit Description

~" -,.. ,~ 180 ~90K L

12 (18) TA - 12 .1-.., Inverse input pin for the tracking amplifier.

-~ (!)3~~q} l~A ,

v ••

Vee

-I-,~

10K 13 (19) SL + 13 Non-inverse input pin for the sled amplifier.

-I-

v ••

~" .~ 180 L

15 (21) SL - 15

I"'" Inverse input pin for the sled amplifier.

.~ ct)3PA 0 22PA

v ••

Vee

. i- ~'" 180 16 (22) SSTOP 16 Pin for detecting a signal for the ON/OFF limit

. i- switch of th~ innermost part of the disc .

v ••

Vee

17 (23) FSET 17 ~ Pin for setting the peak frequency of the fo-o. ...

; 180 CUS, tracking phase compensation and fO of

the CLV LPF. 15K 15K

v ••

, 20K S- Veo

18 (24) SENS Pin to output FZC, AS, TZC, SSTOP and BUSY 180 by command from CPU.

18

20 (26) C. OUT @ ,I- r lOOK Track number count signal output

-t VEE

-5-

SONY CXA 1 0828Q/85

No. Symbol . Equivalent Circuit Description

21 (271 DIRC @ Y Vee

Pin for one~track jump

@~ j j 15~A Contains a 47 kO pull-up resistor.

22 (281 XRST ::47K Reset input pin, reset at "L"

23 (29) DATA @ r Serial data input from CPU

24 (30) XlT @l 180 ...... latch input from CPU

25 (31) ClK ®~ ~ Serial data transfer clock input from CPU

@ VEE Pin for the operation of the sled runaway

33 (39) lOCK prevention circuit at "L" Contains a 47 kO pull-up resistor.

Vee

27 (33) BW =- ~:, K Pin for providing a time constant for the loop =

~ filter.

4.7K ,

VEE

Vee

~~ 4.7K

28 (34) POI ""'" Input pin for the .CX23035/CXD1135 phase = ~r :;: lOOP

comparator output POD.

VEE

Vee

~r ,~ 180

I 10K

29 (35) ISET 29 Curre"nt is input, determining the peaks of focus

,~ 01 search, track jump, and sled kick.

VEE

30 (36) VCOF C>. 10K

cp The free-running frequency of veo is almost

'=

~ ( proportional to the resistance value between , this pin and pin 31 (37).

DVcc

180 , 32 (38) C864 3 Output pin of 8.64 MHz VCO.

.~ I

-6-

SONY CXA 108280/85

No. Symbol Equivalent Circuit Qescription

Vee

,~ 15K

180 34 (40) MDP = " Pin for connec'ting the CX23035/CXD1135

"-" 20K MDP pin. ;~ .

14.5K

VEE ,,..

Vee

;~ 100K 180

35 (41) MON 35 Pin for connecting the CX23035/CXD 1135

.~ 20.5K MON pin.

15K

VEE

Vee

20K 180

C. 36 (42) FSW '= ." Pin for providing an external LPF time constant of the CLV servo error signal.

220K

VEE

Vee

, 180

"'" ... 38 (44) SPDL - '=

~ Inverse input pin for the spindle drive amplifier.

•• VEE

Vee

40 (46) WDCK @ .~ Clock input for auto sequence, usually 88.2

180 kHz is input

41 (47) FOK 41 FOK signal input pin

42 (48) MIRR @ .~ ~ Mirror signal input pin

44 (2) DFCT Defect signal input pin for the operation of the

8 VEE defect countermeasure circuit at "H"

Vee 6aOK

,~ IsaoK t 45 (3) TE 45 Input pin for tracking error signals.

,<- t VEE

-7-

SONY CXA 1 0828Q/8S

No. Symbol Equivalent Circuit Description

Vee

~~ J7~A ,.",

180 46 (4) TZC " "

Input pin for the zero-cross tracking com-= ~

parator. 75K

VEE

.

Vee

j 470K

47 (5) ATSC 4 Input pin of the window comparator for ATSC

t47P detection.

330K

VEE

Vee

180 48 (6) FE 48 ~"

~20~ Input pin for focus error signals.

VEE

-8-

<0

I

Electrical Characteristics

TeSt No, TeSI items Symbol

51

1 Supply current 1 II.[('C'

2 Supply current 2 Dice

3 Supply current 3 A, DII,I'

4 Supply current 4 ItKiND

5 DC voltage gain (il'l:O

1-6 FeeJthrougn VI'I,(W 0

f---- r.1o!1l. output 1 ." voltage I

VFEO[

I-- g

8 ~ Max. output VFE02

I-- ~ voltage 2

< Max. output 9 0 voltage) VFEOJ

I-- Max. output 10 voltage 4 VFE04

r-- Search output 11 voltage 1 YSRCJII

f---- Search output 12 voltage 2 V$RCm

13 DC voltage gain OTEO

f----14 Feedthrough VTEOF

I-- Max. output 15 voltage 1 YTEI'I

16 ~ Max. output VTEI>] g: voltage 2

I- ~ Ma:lO. output

11 • VTI~I'.l

I--, voltage 3 0

Max. output 18 voltage <I VTEI>~

I-- Jump output 19 voltage I VJlJM I' 1

I- Jump output 20 voltage 2 VJlIMI'2

21 DC voluge gain CiSl.O

I-- Max. output 22 ~ voltage I VSlI'l

l- ii: Max. output

23 • YSl.I'2

I--, voltage 2 0

Max, output 24 voltage)

YSI.I'J

SW conditions

52 S3 54 55 56 51 58 S9 SJO 511

0

0

0

0 0

0 0

0

0

0

0

0 0

0 0

0

. SD

00

08

08

08

08

08

02

03

25

13

25

25

25

25

2C

28

25

25

25

25

Ta-2S"C AVec DV cc -2SV AV - - EE. DV EE- - 2 SV DGND- - 2 SV -

Bias conditions Description of output Input Test point point

wavefonn Min. Typ, Max. Unit

E1 E2 E3 E4 and lest method

0 0 0 0 JO Measure after resetting 2,8 5,5 8,2 rnA

31 10,8 15.0 19.2 rnA

19 9,8

43 13, a 16.2 rnA

26 4,8 1,5 10,2 rnA

48 5 SCi = JOllz,2()[)mVp-p 18,0 2\. 0 24.0 dB

SG"" 10kHz, 4OmVp-p, Gain differ--35 dB

=ncc bcLwccn 08 and 00 of Sll

SG = 0.5VDC 1,98 Y

sa = -1J.5VDC -1. 98 Y

SG = O.5Vl)c 1.18 y

SCi = - O.SYnc -1.18 y

-0.64 -0.55 -0.35 Y

0.35 0.55 0.64 Y

45 11 SO = Illllz,5{}flmVIl-p 11.6 14.6 17.6 dB

SG .. I01tHz,IOOmVp·p,Gain differ· enee b.:tl.llcen 25 and 20 of SD

-39 dB

SCi = -1.5VI)(, 1.98 y

SCi = 1.5Vnc -I. 98 V

SG = -I.5Vnc 1.18 y

S(i = I.5Vnc -I. 18 Y

-0.64 -0,55 -0.36 Y

0.36 0.55 0.64 I'

13 14 S(j I!J I lz 50 56 62 dB Opcnloopgain

SCi = fl.4VIK 1.98 Y

SCi = -(lAYnC" -1.98 y

SO = Oo4VI)(" 1.18 y

'Serial data (hex)

CJ)

o z ~

o I

Test No,

25 I--

26 I--

27 I--

28

29 f-----

30

f--31

f--32

f--33

34 I--

35 f-----

36

f--37

38

39

40

4J

.2

43

44

Test items

Max. output vohage 4

~

[ Feed through

" Kick output ~ voltage 1

Kick OUtput voh.age 2

Spindle servo gain Max. output

.g> voltage' I [ Mall. output

" vult;]gc 2

S Max. output 0

vullage J MaJ(.oulput vollllge ~

PLL Reg. OUlp11l

VOltage

Self-running ~ frequency r r Frequency

deviation I

Frequency deviation 2

SENS low level

COUT low level

FZC threshold value

ATSC threshold value

A TSC threshold value

TZC threshold value

SSTOP threshold value

SW conditions • Symbol SO

51 52 53 54 55 56 57 58 5, 510 511

VSI.I'~ 0 25

VSI.OF

V"-IC'K I 22

YKJCK2 23

Ci.'iI'O 0

V~iI'l>1 0

YSI'I'2 0

VS['I'.l 0 0

VSI'I'~ 0 0

Vreg

Fvco

~FI

~F~

VSENS

VCOUT

VTI.C 00

VATSCI JO

V,\TSC] JO

Vnc 20

VSSTOI' 30

Bias conditions Description of output Inpu t Test waveform point point

EI E2 E3 E' and lest method

0 0 0 0 13 I, SO = -(l.4Yne

sa", IOkHz,200mVp-p,Gain differ cm-c bclwc.c:n 25 ard 20 of SO

34 39 SO = 1001z, 20()mVp-p

SG = 1.{)VI)C

S(i = - I.{)VI)C'

SO = LOVD('

SCi = -I.nvnc

3J DC voltage

0 32 VI =OmV

Frequency deviation from FVCO, V1= 148mV

V1""'-148mV

J8

20

. 48 J8

0 • 47 * Value of E when SENS becomes High ('" 1.1 V) by . 47 El 10 E4 varying

• 0 46 SO =/lV

• 0 J6

Min. Typ.

-0,75 -0,6

0.45 0.6

I. 16,5

1. 78

1.[3

3.3 3.5

7 .• 8,,6

7 Jl

-J5 -Jl

3' 50

-,5 -26

7 26

-20 0

-65 -50

Malt.

-1.18

-34

-0,45

0.75

I'

-1.78

-I. 13

3,85

9.7

J5

-7

~l. 98

-1.98

6J

-7

45

20

-35

Unit

V

dB

V

V

dB

V

V

V

\'

V

MHz

%

%

V

V

mV

mV

ml'

mV

ml'

rJJ o z ~

Electrical Characteristics Test Circuit

(See the Pin Configuration for CXA 1 082BS)

13K

140 'l---IW--o S7

4.23K 240K

CXA1082BQ

S3

13K 1'40 13K

eLK

24 XLT

23 DATA

\-.::ft,-t, E 1

5K

59 60K ~

140

13K

r.n 0 z ~

---j> A Vee - A VEE

---0 o Vee

p - com ------. o VEE

~ D GND

~ A GND

SONY

Description of Functions

Focus servo system

(See the Pin Configuration for CXA 108285)

FE

10K FE

22ooP;;1;

1.2K

FZC

Focus phase compen­sation lOOK

O.!}J 40K ~ ......... ~-----(E }---,\N-----l

F52

10K

40K

120K

~ ________________ v~}-B-{rrFr5_E_T ______________ ~7~S~RC~H~ __ ~

001).1 14.7)J

I 22}l

The above is a block diagram of the focus servo system.

CXA 1 OB2BQ/BS

When FS3 is switched on, the high frequency gain can be reduced by forming a low frequency time constant through a capacitor connected across pins 2 and 3 and the internal resistor.

The capacitor across the pin 4 and GND has a time constant to raise the low frequency usually playback condition. The peak frequency of the focus phase compensation is inversely proportional to the resistor con­nected to pin 17 (about 1.2 kHz when the resistor is 510 kQ).

The focus search peak becomes about ± 1.1 Vp-p with the above constant. The peak is inversely proportional to the resistor connected across the pins 29 and 30. However, when this resistor is varied, the peaks of track jump and sled kick also vary.

The FZC comparator invert input is set to 2 % of the difference between the reference voltage Vee and VC (pin 1): 2 % x (Vee - VC).

Note) A resistor of 510 kfl is recommended for pin 17.

- 12-

SONY

Tracking sled servo system

O.022jJ

lOOK

45 TE

6aOK TG1 TE

22K

5PI TMI

Cl------O"'C

20K

TG2

0--0 N

'" 470K >-

120K

SSTOP---<~~~=-----~

ATSC

lOOK

IK

~ +-----<1""C

TM5

TG1 680K

~ -66P

10K I 110K

Tracking phase 10K compensation

yM7 82K

17 FSET

S10K

O.01jJ

The above is a block diagram of the tracking sled servo system.

CXA 1 0828Q/8S

lOOK

The capacitor across pins 8 and 9 has a time constant to lower the high frequency when TG 2 is switched off. The tracking phase compensation peak frequency is inversely proportional to the resistor con­nected to pin 17 (about 1.2 kHz when the resistor is 510 kfl).

For a tracking jump in the FWD or REV direction, TM3 or TM4 are set to ON. At this time, the peak voltage fed to the tracking coil is determined by the TM3 and TM4 current values and the feedback resistor from pin 12. That is:

Track jump peak voltage = TM3 (TM4) current value x feedback resistor value The FWD or REV sled kick is done by setting TM5 or TM6 to ON. At this time, the peak voltage added to the sled motor is determined by the TM5 or TM6 current value and the feedback resistor from pin 15.

Sled jump peak voltage = TM5 (TM6) current value x feedback resistor value Each SW current value is determined by the resistor connected to pins 29 and 31. When the resistor is at about 120 kG,

TM3 or TM4 is ± 11 /LA and TM5 or TM6 is ± 22 /LA. This current value is almost inversely proportional to the resistor, variable within a range of about

5 to 40/LA for TM3. . S STOP is the ON/OFF detection signal for the limit SW of the sled motor's innermost circumference.

-13 -

SONY CXA 108280/85

Spindle servo and LPF

CXQ1l30/1135

MaN

15K

MOP

15K

L-__________ -{36~FS~W~----------~17~F~S~ET~--------J

O.Q1.u SIOK 20K MDS>---~WL----------1

1 M 0.47 FSWT+

50V 1.0.033

The 200 Hz LPF is formed with 0.033 p.F and 20 kO connected to pin 36 and the secondary LPF is formed with the built-in LPF (fc up to 200 Hz with 510 kO for pin 17), and the carrier component of the eLV servo error signals MDS and MDP is eliminated. .

In the eLV-S mode, FSW becomes L and the pin 36 LPF fc lowers, strengthening the filter further. With the pin 17 resistor connected to Vee, fc does not vary with power supply voltage fluctuations. Note) Use the phase compensation instead of MDS when the eX23035 is used.

veo loop filter and 8.64 MHz veo I.SP

32K

66K

CX01130/1135 32K

10K POI PDQ 281r-::-'--------,~w----.--iy

100Pr 2.7K 15K

C864 f--------C32

'-____________ --(z27Y.B:.:W~----------_<30 VCOF 31}:3"'.5"'V ________ J

+ 4.7)J 6.3V

TO.0047"

100

l

3.3K

2K

CXD11301113S loaop

:eveOI

lOOK

veDa

The phase compensation output PDO input from pin 28 has its PWM carrier component removed in the loop filter. Then, the V-I conversion is made and the free-running frequency setting current from pin 30 is added to control the veo frequency. The veo self-running frequency is almost in­versely proportional to the resistor across pins 30 and 31. This resistor is set so that the PLL capture range center matches the 4.3218 MHz at pin 70 of the eXD1135/1130.

-14 -

SONY CXA 1 0828Q/8S

Commands

The input data to activate this IC consists of 8-bits. It shall be represented as $XX in two hex­adecimal digits. (X denotes 0 to F). Instructions for the CXA 1 082BQ are classified into 8 types -$OX to 7X.

1. $OX [SENSE Pin 18 is "FZC"] This instruction is related to the focus servo control. The bit configuration is as follows:

07 06 05 04 03 02 01 00 o 0 0 0 FS4 FS3 FS2 FS1

The four switches FS 1 to FS4 are related to focusing, and correspond to 00 to 03. $00 At FS1 = 0, Pin 7 is charged to (22p.A - 11p.A) x 50 kfl = 0.55 V).

If FS2 = 0, this voltage is not output and the output of Pin 5 remains 0 V. $02 From the above state, FS2 only becomes 1 and a negative output is output to Pin 5.

This voltage level is stipulated as follows:

(22 A _ 11 A) x 50 kfl x Resistance value between Pin 5 and Pin 6 ..... (1) p. p. 50 kfl

$03 From the above state, FS1 becomes 1 and the current supply of + 22 p.A is separated. Then, the CR charge/discharge circuit is formed and Pin 7 voltage decreases as time passes, as shown in Fig. 1.

Fig. 1 Voltage of pin 7 as FS1 changes from 0 to 1

The time constant is formed by 50 kfl and an external capacitor.

By giving instructions $02 and $03 alternately, the focus search voltage is produced (Fig. 2).

$ 00 02 03 02 03 02 00

Fig. 2 Production of search voltage by $02 and $03 (Voltage of Pin 5)

- 15-

SONY CXA 1 0828Q/8S

1) Description of FS4 This switch is placed between the focus error input 48 and the focus phase compensation, serving to switch on and off the focus servo.

$00 -> $08 Focus off Focus on

2) Focusing procedure

Assume the polarity as follows: a) The lens moves away onoward the disc in searching. b) At this time, the output voltage of Pin 5 varies from negative to positive. c) Further, the focus S-curve changes as follows:

Fig. 3 S-curve

The focus servo is activated at the operating point of @ as shown in Fig. 3. Generally, a logical product (AND) with the Focus-OK signal is used to switch on the focus servo in focus searching and to prevent a malfunction while passing the @ point in Fig. 3. This IC is designed so FZC (Focus Zero Cross) is output from the Sense Pin 18 as the @ point passing signal. The Focus-OK indicates a signal is in focus (focus is enabled in this case). In summary, the following time chart shows how to obtain the focus.

Drive voltage

Focus error

Sense pin (FZC)

Focus OK ICXA 1081)

(20 ms){ 200ms J

$02 I I '-, I

1$001 1,1 $03 I' I

I

I I

$08 ---

-----------~--~------1\ ,," I "---I I I

l The moment it is in focus

I I I L ____________ _

Fig. 4 Timing Chart of In-Focu.s

-16 -

* With the dotted line a focus cannot be obtained.

SONY CXA 1 08280/BS

Care should be taken here that $08 is instructed in the shortest time after FZC changes from H to L. For this purpose, the (b) sequence required for software is better than (a).

(a) (b)

Fig. 5 Bad Sequence and Good Sequence

3) On the Sense Pin 18

What is output to the Sense Pin depends on input data as follows: FZC is output with $OX. AS is output with $1 X. TZC is output with $2X. SSTOP is output with $3X. BUSY is output with $4X. HIGH-Z is output with $5X to 7X.

Higher instructions than $7X are codes for the CX01135 and several outputs are ob­tained by connecting to the CX01135 "SENS" pin.

2. $1X (SENS Pin 18 is "AS") This instruction refers to ON/OFF of TG1, TG2 and the break circuit. The bit configuration is as follows:

07 06 05 04 03 02 01 0 0 0 1 ANTI Break TG2

SHOCK Circuit ON/OFF ON/OFF

TG1, TG2

DO TG1

The purpose of these switches is to switch on or off Up/Normal of the tracking servo gain. The break circuit refers to a mechanism which prevents a volatile actuator servo circuit. After jumps of 100 tracks or 10 tracks, the servo circuit is out of the linear range and the actuator often sets tracks wrong. Using a feature that the RF envelope and the tracking error are out of phase by 180 0 when the actuator crosses the tracks outwardly and vice versa, unwanted track­ing errors are cut to break this undesirable jumping.

-17 -

SONY CXA 1 OB2BQ/SS

RF

r­Tracking error,

Envelope detection

Waveform rectification

( MIRR)j

Waveform rectification

-----'

Edge detection

CXA 1082

02

® ®

CK SRK

Fig. 6 TM7 Movement (Break Circuit)

Center -+ Outward Outward --> Center

0 ~ ~ ®

CD @

®

CD

®

,-1/TM7

J. Open at L Make at H

COOMIRR OO )

COOTZCOO)

...... Break is applied with this.

@ov

3.

Fig. 7 External Waveform

$2X (SENS Pin 18 is "TZC")

This instruction refers to ON/OFF of the tracking servo and thread servo as well as generation of the jump pulse and speed feeding pulse in accessing.

07 06 05 04 03 02 01 00 I I I I

0 0 1 0 T racking control Sled control 00 off 00 off 01 Servo ON 01 Servo ON 10 F-JUMP 10 F-speed feed 11 R-JUMP 11 R-speed feed

U U TM1,TM3,TM4 TM2,TM5,TM6

-18 -

SONY CXA 1 OS2SQ/SS

DIRC Pin 21 and 1 Track Jump

Generally, for a 1-track jump, an acceleration pulse is added and a deceleration pulse is given for a specified time from the moment a tracking error passes the 0 point; then the tracking servo is switched on again. For the 1 OO-track jump to be explained in the next item, as long as the number of tracks is about 100 there is no problem, but the 1-track'jump must be exactly, requir­ing the above complicated procedure. For a 1-track jump of a CD player, both the acceleration and deceleration take about 300 to 400 p.s. When software is used to execute this operation, it will be as in the flow chart of Fig. 9, but practically it takes time to transfer data.

Pulse waveform

Tracking error

Acceleration ,------,

Deceleration '------'

Fig. 8 Pulse Waveform and Tracking Error of 1-Track Jump

'---~~

ITH:flEV 1 SL : ()FF Execute

ITR:FWll

\SL:()FF

Execute

I Til : HEV

\ SL : <WF Execute

The following develops:

ITI{:FIVIJ \SI.: <IFF

The following develops:

ITR:()N

\ SL : ON Execute

Fig. 9 1-Track Jump without DIRC 21

I TH : < IN \SL:()N

Fig. 10 1-Track Jump with DIRC 21

For this IC, the "DIRC" (Direct Control) Pin is provided for simple 1-track jumping. For 1-track jump using DIRC, the following is undertaken (DIRC = normal H). (a) Acceleration pulse is output. ($2C for REV or $28 for FWD). (b) With TZC t (or TZC t), set DIRC to l. (SENS Pin 18 is "TZC"). As the jump pulse

polarity is inverted, deceleration is applied. (c) Set DIRC to H for a specific time.

Both the tracking servo and sled servo are switched on automatically. As a result, the track jump will be as shown in the flow chart of Fig. 10 and two serial data trans­fers are saved.

-19 -

SONY CXA 1 0828Q/8S

4. $3X This command is for switching the Focus search and Sled kick peak value.

DO, D1 ..... Sled, NORMAL feed, high-speed feed D2, D3 ..... Focus search peak switching

Focus search peak Sled kick peak

ll7 06 ·05 04 D3 D2 Dl DO Relative value

(PS3) (PS2) (PS]) (PSO)

0 0 0 0 .± 1

0 1 0 1 ± 2 0 0 1 1

1 0 1 0 ± 3 1 1 1 1 ± 4

5. $4Xto$7X $4X to $7X are for the auto sequencer commands. Refer to the table and timing chart for the auto sequencer.

The auto sequencer automates the troublesome routines of focus pull-in and track jump, eliminating any timing control of the microcomputer that is less than 10 ms and combin­ing with the Q register of the CXD1135, CXD1125, CXD1130 and CX23035 .

• Auto focus When a focus is pull-in during the BUSY shifts H -+ L -+ H, the $08 is automatically set in the register. Even when it is out of focus, no auto pul1-in is done requiring FOK to be monitored .

• Track jump When the BUSY shifts H -+ L -+ H and the track jump is completed, the $25 is automatically set in the register. Sequencer malfunctions can be relieved with the $40 anytime.

Others

1. Connection of the power supply pin

Vee VEE VC ± 5 _~. dual power SUPPlY +5V -5V OV 5 V sinl!le power +5V OV VC* supply

• CXA1081

2. FSET pin The FSET pin determines the characteristic of the high frequency phase compensation of Focus, Tracking servo, and cut-off frequency (fc) of CLV LPF.

3. ISET pin ISET current = 1.27 V /R

= Focus search current ($30) = Tracking kick current = 1/2 sled kick current ($30)

4. In the tracking amplifier, input is clamped at 1 VSE to prevent over input.

5. How to change the FE and TE gains (1) To increase: Pins ® and ® , pins ® and @ to more than 100 kD. (2) To decrease: Divide the FE and TE resistor of input.

6. Tracking servo phase From TE to TAO the phase is negative. (CXA20108 has a positive phase.)

- 20-

8 __ FE TE

SONY

Auto Sequencer Timing Chart

1. 1 track jump

$48 latch (549)

;} , XLT u TE

C.Qur

BLIND A

FWD/IREV) JUMP

REV!{FWD) JUMP

, TRACKING SERVO

ON OFFI

, , FWD/(REV) MOVE , ,

OFF1

SLED SERvO ON 1

BUSY

Internal mode $25 $28 FWD(REV)

($2CI

2. 10 track jump

$4A latch ($48)

:} , XLT U , c.OUr

BLIND A

FWD/(REV) JUMP

REV!1FWD! JUMP ,

TRACK ING SERvO ON OFFI

, FWD/(REV] MOVE

OFF' SLED SERVO ON I

BUSY

Internal mode $25 $2A FWO\REV)

1$2FJ

C.OUT 1 count

$28 ($2Cl

C.OUT 5 counts

$2A 1$2F)

- 21 -

8

$2C 1$28)

$2E 1$281

CXA10B2BQ/BS

OL

.25

Inversion with counter overflow

:;

[FWO] REV

$25

SONY

3. 2N track jump

$4C latch ($4D) ,,-' , ,-, I

----.;' , U XLT

c.our

BLIND

FWD/IREV)JUMP

REV/CFWQ1JUMP

TRACKING SERvO ON

FWD/fREV) MOVE

SLED SERVO ON

BUSY

Internal mode FWD{REVj

4. M track movement

XLT

C.DUT

BLIND

FWD/IREV) JUMP

REV/(FWDIJUMP

TRACKING SERVO

FWD/{REVIMOVE

SLED SERVO

BUSY

Internal mode FWO(AEV)

,

OFF! ,

, OFFI

, I I

.25 $2A C$2Fl

C.OUT N count

, 1111111111'

$2A ($28)

"III

$2E 1$28)

$ 4E latch ($4F)

:; ,

U ,

~IIIIII' A

ON OFFi

C.OUT M count

ON OFFj

$25 '22 $22 ($23) ($231

- 22-

Inversion with counter overflow

:; , ,

nJJc f-.-,.< c ,

, I , '26 ~). ($271

"-

( FWD) REv

$25

Reading the Q data is possible.

, , , IIII11111 ! I FWD

REV

$25

CXA 1 0828Q/65

SONY CXA 1 0828Q/8S

5. Auto focus

$47 latch

:}

U I

1 I

1 I I

FOK I I I I I I

FZC I f f + I I

, I I BLIND I I' 'I I

I E I I ,

SEARCH UP I I I

SEARCH DOWN I I

FOCUS ON

BUSY

Internal mode $02 $03 $03 $03 $08

6. Notes on use of the auto sequence 1) The horizontal axis of the timing chart is not always proportional to the actual time. 2) Use the auto focus only while the search is down.

Use the track jump while the focus, tracking, and sled servo are switched on. 3) The auto sequencer does not cover tracking gain up, brake, anti-shock, and focus gain down.

Separate commands are required. 4) BUSY does not tell the full status of the player. Monitor FOK and GFS, etc. using the

microcomputer. 5) When the sequencer hangs up, detect BUSY's max. excess time using the microcomputer

and send $40 (CANCEL) to reset to the preceding status. 6) In all modes the auto sequence starts from the first WDCK falling edge right after

XLT falls.

- 23-

SONY

Parallel Direct Interface

1 . DIRC $28 latch

V , XLT

$2C latch , I I

:.; I

I I I I

CXA 1 0828Q/85

U , DIRe

I ( I I ,

ON I I t=t =::jr-I I

f I

\)

u ,

FWD JUMP OFF , , 55

REV JUMP ON I OFF I , , ON

OFF I TRACKING SERVO , ON

OFFI SLED SERVO

))

2. LOCK (Sled runaway prevention circuit)

LOCK l f , , ON

OFFI I SLED SERVO , ,

TRACKING GAIN DOWN

OFF It:===::::jl UP I I

ON TG1,TG2

I , I , , I I I I I I I

3. DEFECT (Disc defect countermeasure circuit)

DEFECT

FOCUS SERVO

TRACKI NG SERVO

, I I ,

______ ~n~======== ------------------~' ~ ON OFF U ----------------~' 'r-------------------------OFFU , , ON

, I I I I ,

- 24-

SONY CXA 1 0828Q/8S

CPU Serial Interface Timing Chart

DATA DO 02 X 03 ~ 05 X 06 X 07

t '"1 I..-.!.e..-eLK

11 fCk I

XLT

DYcc ~ DGND = 4 5 to 5 5Y

Item Symbol Min. Typ. Max. Unit

Clock frequency [ok 1 MHz Clock pulse width fwck 500 ns Hold time t," 500 ns Setup time th 500 ns Delay time tD 500 ns Latch pulse width tWL 1000 ns

System Control

AOORESS OATA SENS Item

07060S04 03 02 01 00 Output

FS4 FS3 FS2 FSI

Focus Control o 0 0 0 Focus Gain Search Search FZC

ON Down ON Up

Tracking Control 0 0 0 I Anti

Shock

Brake TG2 TGI A.S

ON Gain Set *1

Tracking Mode 0 0 I 0 Tracking Mode • 2 Sled Mode *3 TZC

PS4 PS3 PS2 PSI

Select 0 0 I I Focus Focus Sled Sled SSTOP

Search + 2 Search + I Kick+ 2 Kick + 1 Auto Sequence *4 0 I 0 0 AS3 AS2 ASI ASO BUSY

Blind CA, E)/Overflow CC) 0.18ms 0.09ms 0.04Sms 0.022ms *S Brake (B)

0 I 0 I 0.36ms 0.18ms 0.09ms 0.045ms

RAM Kick CD) 0 I I 0 11.6ms S.8ms 2.9ms 1.4Sms Hi-Z

SET Track Jump C N)

0 64 32 16 8

Track Move C M) I I I

128 64 32 16

Note)* 1. GAIN SET It is possible to set TG1 and TG2 independently. When the anti-shock is 1 (00011 xxx!. invert both TG 1 and TG2 when the internal anti-shock is H.

-25-

SONY

" 2 TRACKING MODE

1J3 [)2

()FF 0 0 ()\ 0 I

[.'\\·IJ J U~lP I 0

[n;v JU~lP I I

• 4 AUTO SEQUENCE

AS3

CANCU .. 0

FOCUS ON 0

I TRACK JU~lP I

10 TRACK JUMP I

2N TRACK JUMP I

M TRACK MOvr; I

"3 SLED MODE

OFF

ON

FWD MOVr;

RI':V MOVr;

AS2 ASI ASO

0 0 0

I I I

0 0 X

0 I X

I 0 X

I I X

III

0

0

I

I

x = 0 X=l

DO

0

I

0

I

FORWARD REVERSE

CXA 1 0828Q/8S

• When CANCEL $40 is sent, the status immediately preceding the auto sequence mode (just before $4X is sent) is reset.

• The auto sequence mode starts with the first falling of the pin 40 input pulse (WDCK) after the $4X transfer and the falling of latch pulse.

"5 RAM·SET • Values $ 1 to $ E (not $ 0, $ F) can be set. • The above set values are ones when WDCK (88.2 kHz) is input to pin 40. • The RAM is preset when the power is switched on and the internal initial set values are as follows:

ADDRI':SS DATA o I 0 I o I 0 I

o I I 0 o I I I

o I I I I I I 0

• The actual count values are slightly'different from the set values.

A B, D, E C N, M

set value + 4 to 5 set value + 3 set value + 5 set value + 3

WDCK WDCK WDCK Count out

- 26-

SONY CXA 1 0828Q/85

Serial Data Truth Table

Serial data Hexa. Function

FOCUS CONTROL FS~ 4321

o 0 0 0 0 000 $00 o 0 0 0

00000001 $01 o 0 0 1

o 0 0 0 0 0 1 0 $02 o 0 1 0

o 0 0 0 0 0 1 1 $03 o 0 1 1

o 0 0 0 0 100 $04 o 1 0 0

00 0 0 0 1 0 1 $05 o 1 0 1

o 0 0 0 0 1 1 0 $06 o 1 1 0

00000111 $07 o 1 1 1

o 0 001 000 $08 1 0 0 0

o 0 0 0 1 001 S09 100 1

o 0 001 010 SOA 1 0 1 0

00001011 SOB 1 0 1 1

o 0 0 0 1 100 SOC 1 1 0 0

o 0 001 101 SOD 1 1 0 1

00001110 $OE 1 1 1 0

00001111 $OF 1 1 1 1

AS- 0 AS~ 1 TRACKING CONTROL

TG~ 2 1 TG~ 2 1

00010000 $10 0 0 0 0

000 1 000 1 $11 0 1 0 1

00010010 $12 1 0 1 0

00010011 $13 1 1 1 1

00010100 $14 0 0 0 0

000 1 0 1 0 1 $15 0 1 0 1

00010110 $16 1 0 1 0

00010 1 1 1 $17 1 1 1 i

00011000 $18 0 0 1 1

000 1 100 1 $19 0 1 1 0

o 0 0 1 101 0 $IA 1 0 0 1

000 1 101 1 $IB 1 1 0 0

o 0 0 1 1 100 $IC 0 0 1 1

00011101 $ID 0 1 1 0

00011110 $IE 1 0 0 1

000 1 1 1 1 1 $IF 1 1 0 0

- 27-

SONY CXA 1 DS2SQ/SS

Serial data Hexa. Function

TIli\CK1NG MOllE DIRC=I DIRC=O DIRC=I

TM~ 654321 654321 654321

00100000 $20 000000 001000 000011

o 0 100 001 $21 000010 001010 000011

o 0 I 000 I 0 $22 010000 011000 100001

o 0 1 000 1 1 $23 100000 101000 100001

00100100 $24 000001 000100 OOOOll 00100101 $25 OOOOll 000110 OOOOll

00100110 $26 010001 010100 100001

00100111 $27 100001 100100 100001

00101000 $28 000100 001000 OOOOll 00101001 $29 000110 001010 000011

o 0 1 0 1 010 $2A 010100 011000 100001

00101011 $28 100100 101000 100001

o 0 1 0 1 100 $2C 001000 000100 OOOOll 00101101 $20 001010 000110 OOOOll 00101110 $2E 011000 010100 100001

00101111 $2F 101000 100100 100001

- 28-

N (0

Application Circuit

1. ± 5 V dual power supply for CXA 108280 (48 pin OFP)

(See the Pin Configuration for CXA 1 0828S)

From CXD 1130/CXD 1135 "------------------------------------;,

Spindle motor

From CXD 1135

From CXA 1081

TE

FE

1M t.47)J ~50V

+

+--tc-----f43 DVEE

f 22" +6.:W10K

2K

3.3

From microcomputer

4-- +UNREG

<!---- +5

__ -5

SEN 5 lB~-"'-"'" To microcomputer

Limit SW

~~7---~~

+----UNREG

Sled motor

VR >---~----------~ 82K

Focus coil Tracking coil

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of Ihese circuits or for any infringement of third party patent and other right due to same.

00 o z ~

OJ o I

2. + 5 V single power supply for CXA 108280 (See the Pin Configuration for CXA 108285)

From CXDl130/CXDl135 Ir-~---~---~--~'5~~~<8~~--~~~~~~--------~\

U) a 0000

~~6~Z ~ ~~! ~ooo p + ~ ~~~:K +-I p+-+-+--t.;,( ''1

0.033 20K

lOOK

From CXDl135 >----f40 woeK

FO K >--------{41 FOK

a 3

R » TE o OJ

MIRR >-___ ~42 MIRR

VR>--~~~----l

To spindle drive

CXA1082

0.1

To focus drive

0.1

To tracking drive

From microcomputer

a.lv

lK

To microcomputer 510K

Limit SW 0.01.~

toOK 0.015

120K 3.3p

')--r--li---<' +~ 22.

82K

To sled drive

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

O----VR

<J---+SV

Internal Phase Compensation Standard Circuit Design Data

sw conditions Mode Item Symbol 5D

SI S2 S3 S. S5 S6 S7 SB S9

1. 2 kHz gain 0 0 OB

'n 1. 2 kHz phase 0 0 OB 0 n c 00 1. 2 kHz gain 0 0 oc

1. 2 kHz phase 0 0 0('

1.2 kHz gain 0 25

-\ @ n

1. 2 kHz phase 0 25

" 3' 2. 7 kHz gain '"

0 15

2. 7 kHz phase 0 15

1 00 Hz phase Cf) "0 3' 0.

2 kHz gain

w CD

Bias conditions "0- "0-\ Output waveform o~ o ro and description _."0 -'00 ~c ,,~ of test methods ~~

.B 5

45 II

34 39

Min. Typ. Max.

21.5

63

16

63

13

-12~i

26.5

~130

-30

-3,5

Unit

dB

i.l{'g

dB

dt·g

dB

!It'll

dB

d"

d('11

dB

rn o z ~

SONY

,

'0

,

--"

,

"

-, , "

,

,

r--

,

,

~ , ' " -

,

,

.,

"

"

,

,

-, ,

0

,

Tracking frequency characteristics ,

, -- , , , , , G ,

, ,

'L 0 , ~ \

/ \

00

V V K , ,

-- --:..7 , 1\ \

:::-:,... --- , \ , '-. ,-- ./ 1\ ' '" \

, , , , ., \ ,

- - NORMAL 1\' 1\ .,

-- - GAIN UP \ ,

1'<" ,\:' CTGU 0.033" I I I

'00

" ,

f-Frequency (Hz)

FOCUS frequency characteristics

-- -, L CFLB=O.l" / )\ - ,

"~ CFDG =0.1" \t;"'" .... G

r- , ,

'\ / / ,

/ ,

I/-' , II ~ !\\ ,

/ , ,

~ " V " \' / , , ,

~;'-..... V , NORMAL "\ "

, r-, , "-

-/ , , - - -

GrJOT ' ----" "

f-Frequency (Hz)

CL V frequency characteristics

"

i--l"-

G r-

,,, f-Frequency (Hz)

- 32-

t--

f'-..

f'.

"

"

.,

" .,

'\ , " ,

" .,

i' " ., "

,

-90·

10.- ,60·

Ol Ol ~

Cl Ol e '$­Ol

'" '" .c a..

Ol Ol ~

Cl Ol

0

... Ol

'" '" .c a..

Ol Ol ~

Cl Ol e

"S­

Ol

'" '" .c a..

CXA 1 OB2BQ/BS

SONY CXA10B2BQ/BS

Package Outline Unit: mm

CXA 1 082BQ 4 Bpi n Q F P (P las tic) 0.7 9

36

o 15.3 :l:Q.4

'0.4 012.0 -0.1

25

12

24

13

+0,15 0.3 -0.1

±O.12 @ +0.3 22-0.1

SONY NANE QFP-48P-L04 EIAJ NAME -OFP048-P-1212-B JEDEC CODE

+0.1 0.15 -0.05

lb

"" 0.1-0,1

NOTE: PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

CXA1082BS 48pin SDIP (Plastic) 600mil 5.19

TOA 43.2-0.1

4,~ n n n n n n n n n n n n nn n nnn n n ~,5

) 0 [ 1

1 0

'u,'

1.778114

0.5:1:0.1

0.9:1:0.15

~~

ci6 " +, N q .n '" ~ ~

SONY NANEI SDIP-4BP-02

EIAJ NANEI SDIPD48-P-0600-A

JEDEC CODEI --

NOTE: PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

-33 -