serial interfaces.pdf

Serial Interfaces

Introduction to I2C, SPI & UART

- SUSHMA RAWAL

Serial Communication

� The concept of serial communication is the process of

sending data one bit at a time, sequentially, over a

communication channel.

� This is in contrast to parallel communication, where several

bits are sent as a whole, on a link with several parallel

channels.

� Advantages of Serial Communication

– Integrated circuits are more expensive when they have more

pins. To reduce the number of pins in a package, many ICs use

a serial bus to transfer data.

– Serial communication is used for all long-haul communication to

reduce the cost of the cable.

Reference : Serial communication. (2010, July 12). In Wikipedia, The Free Encyclopedia. Retrieved 06:30, July 29, 2010, from

http://en.wikipedia.org/w/index.php?title=Serial_communication&oldid=373069241

Various Serial Communication Examples

� High Speed Serial Communication Examples

– SATA Rev 1.0 with a data rate of 1.5 Gbps.



– SAS Gen 1 with a data rate of 3.0 Gbps.

– SAS Gen 2 with a data rate of 6.0 Gbps.

– PCI Express 1.0 with a data rate of 2.5 Gbps.

– PCI Express 2.0 with a data rate of 5 Gbps.

– PCI Express 1.0 with a data rate of 8 Gbps.

SAS- Serial Attached SCSI

SCSI - small computer system interface

SATA - Serial Advanced Technology Attachment

PCI - Peripheral Component Interconnect

Various Serial Communication Examples

� Low Speed Serial Communication Examples

– I2C Bus with a data speed spanning from 100 Kbit/s to 3.4

Mbit/s.

– SPI Bus. Standard does not specify maximum data rate.

Peripherals available operating with a maximum of 104

MHz.

– RS-232. Speeds range from 9600 bits/sec to 115200

bits/sec.

Inter Integrated Circuit (I2C) Bus – Introduction

� I2C is used to attach low-speed peripherals to a motherboard,

embedded system, or cellphone . For e.g.

– Some intelligent controller, say a microprocessor or microcontroller.

– General purpose LCD / LED drivers, Real time clocks, A-D Converters & D-A

Converters etc.

– Sensors like Temperature Sensors.

� Some form of communication needs to exist for the coherent operation of the

system.

� Philips Semiconductors (now NXP Semiconductors) developed a simple

bidirectional 2-wire bus for efficient inter-IC control. This bus is called the

Inter IC or I2C-bus.

� All I2C-bus compatible devices incorporate an on-chip interface which allows

them to communicate directly with each other via the I2C-bus.

Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors

I2C Bus – Features

� Only two bus lines are required; a serial data line (SDA) and a serial

clock line (SCL).

� Each device connected to the bus is software addressable by a

unique address and simple master/slave relationships exist at all

times; masters can operate as master-transmitters or as master-

receivers.

� It is a true multi-master bus including collision detection and

arbitration to prevent data corruption if two or more masters

simultaneously initiate data transfer.

� More than one IC capable of initiating a data transfer can be

connected to it. The I2C protocol specification states that the IC that

initiates a data transfer on the bus is considered the Bus Master.

Consequently, at that time, all the other ICs are regarded to be Bus

Slaves.


I2C Bus – Features

� Serial, 8-bit oriented, bidirectional data transfers

can be made at

– Up to 100 kbit/s in the Standard-mode.

– Up to 400 kbit/s in the Fast-mode.

– Up to 1 Mbit/s in Fast-mode Plus.

– Up to 3.4 Mbit/s in the High-speed mode.

Protocol

� Transfers are byte oriented, MSB first

� Start: SDA goes low while SCL is high

� Master sends address of slave (7-bits) on next 7 clocks

� Master sends read/write request bit

– 0-write to slave

– 1-read from slave

� Slave ACKs by pulling SDA low on next clock

� Data transfers now commence

I2C Bus – Terminology


I2C Bus – Signal Lines

� The two signal lines SDA and SCL are bidirectional lines, connected

to a positive supply voltage via a pull-up resistor.

� When the bus is free, both lines are HIGH. The output stages of

devices connected to the bus must have an open-drain or open-

collector to perform the wired-AND function.


� The levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are set as 30%

and 70% of VDD; VIL is 0.3VDD and VIH is 0.7VDD.

I2C Bus – Data Validity

� The data on the SDA line must be stable during the HIGH

period of the clock.

� The HIGH or LOW state of the data line can only change

when the clock signal on the SCL line is LOW.

� One clock pulse is generated for each data bit transferred.


I2C Bus – START & STOP Condition

� All transactions begin with a START (S) and can be terminated by a

STOP (P).

� A HIGH to LOW transition on the SDA line while SCL is HIGH

defines a START condition.

� A LOW to HIGH transition on the SDA line while SCL is HIGH

defines a STOP condition.

� START and STOP conditions are always generated by the master.


I2C Bus – Byte Format

� Every byte put on the SDA line must be 8 bits long.

� The number of bytes that can be transmitted per transfer is

unrestricted.

� Each byte has to be followed by an Acknowledge bit.

� Data is transferred with the Most Significant Bit (MSB) first.


I2C Bus – Byte Format

� 9-th pulse:

– transmitter releases SDA

– receiver must hold SDA low in order to ack. received data

– slave must release SDA after ack. bit

I2C Bus – Arbitration

� Arbitration refers to a portion of the protocol required only if more

than one master will be used in the system.

� A master may start a transfer only if the bus is free. Two masters

may generate a valid START condition on the bus.

� Arbitration is then required to determine which master will complete

its transmission.


I2C Bus – Data Transfer

� After the START condition (S), a slave address is sent.

� This address is 7 bits long followed by an eighth bit which is a data direction

bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a

request for data (READ).

� A data transfer is always terminated by a STOP condition (P) generated by

the master.


I2C Bus – Possible Data Transfer Formats


Message protocols

� I²C defines three basic types of message, each of which begins with a START and ends with a STOP:

� Single message where a master writes data to a slave;

� Single message where a master reads data from a

slave;

� Combined messages, where a master issues at

least two reads and/or writes to one or more slaves.

Message protocols

� In a combined message, each read or write begins with a START and the slave address.

� After the first START, these are also called repeated START bits; repeated START bits are not

preceded by STOP bits, which is how slaves know

the next transfer is part of the same message.

I2C Bus

� The number of I2C devices that can be connected to a single I2C bus segment is limited only by a

maximum bus capacitance (400pF) and address

space.

I2C Bus – Other evolved variants

� SMBus – System Management Bus.

� PMBus – Power Management Bus.

� IPMI – Intelligent Platform Management Interface.


SPI Bus – Introduction

� A Serial Peripheral Interface (SPI) system is a Master-Slave

protocol.

� SPI consists of one master device and one or more slave

devices.

� The master is defined as a microcontroller providing the SPI

clock and the slave as any integrated circuit receiving the SPI

clock from the master.

� SPI is also called “four wire” serial bus and operates in full-

duplex mode.

� Standard has been defined by Motorola.

Reference : TN15_SPI_Interface_Specification from VTI Technologies

Reference : Getting started in SPI from Microchip

SPI Bus – Features

� In SPI, data are always transferred in both directions.

� It is up to the master and slave devices to know whether a

received byte is meaningful or not.

� A device must discard the received byte in a “transmit only”

frame or generate a dummy byte for a “receive only” frame.

� SPI does not have an acknowledgement mechanism to

confirm receipt of data.

� SPI is better suited to applications in which devices transfer

data streams such as the communication between a “codec”

(coder-decoder) and a digital signal processor.

Reference : Introduction to Serial Peripheral Interface from Embedded Systems Design

SPI Bus – Signal Lines

The four typical SPI signals include:

Serial clock (SCLK)

- This signal is generated by the Master.

- Other signals in the transmission change based on the

timing of edges from this clock.

– Data is typically output from the transmitter during the

falling edge of SCLK.

– Data is typically latched by the receiver during the rising

edge of SCLK.

master data output, slave data input (MOSI)

- This line is the output from the Master to the slave.

- Transmits bit-by-bit synchronized with Master clock edges.

SPI Bus – Signal Lines

• master data input, slave data output (MISO)

-This line is the output from all the slaves connected.

- Transmits bit-by-bit from the slave synchronized with Master clock

edges.

• chip select (CS) or slave select (SS)

- This is a bank of signals where each line goes to individual

slaves in the system.

- One line is asserted at a time to enable communicate with

the corresponding slave.

– When this signal goes low, the slave will listen for SPI clock and

data signals.

SPI Bus

• The serial data transmission through SPI Bus is fully configurable.

• SPI devices contain certain set of registers for holding these configurations.

• The Serial Peripheral Control Register holds the various configuration parameters like master/slave selection for the device, baud rate selection for communication, clock signal control etc.

• The status register holds the status of various conditions for transmission and reception.

Master connected to one slave

SPI Bus – Typical SPI Connection

Reference : AT25512 SPI Serial EEPROM from Atmel

Data Transmission

� A typical hardware setup using two shift registers to form an inter-chip circular buffer

� the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports.

� Such frequencies are commonly in the range of 1-70 MHz.

� The master then pulls the slave select low for the desired chip

� With the SPI interface you can communicate with a device transmitting and receiving 8 bits of data at the same time and it is suited to high speed streaming data transfers.

Data Transmission

During each SPI clock cycle, a full duplex data transmission occurs:

� the master sends a bit on the MOSI line; the slave reads it from that same line

� the slave sends a bit on the MISO line; the master reads it from that same line

� Not all transmissions require all four of these operations to bemeaningful but they do happen.

Data Transmission

Basic Transmission Step-by-Step

� The Master drives a particular SS line low to initiate communication with the corresponding slave.

� Once the selected SS is low, one edge (rising or falling) of the SCLK signals the devices (Master and Slave) to toggle the MOSI and MISO to the correct bit of data being transmitted.

� The other edge of the SCLK line (rising or falling) signals the devices to register the bits on the MOSI and MISO, effectively reading the bit into the device.

Basic Transmission Step-by-Step

� The transmission continues in this fashion until the devices have exchanged the specified number of bits (usually 8,16, or 32)

� After the transmission is complete the Master pulls the SS line for the slave back high and either goes to another slave on the network or reinitiates the transmission with the same slave by pulling the corresponding SS line back to low.

Flowchart of the basic SPI transmission

Daisy chain SPI configuration

Daisy chain SPI configuration

� The first slave output being connected to the second slave input, etc.

� The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of what it received during the first group of clock pulses.

� The whole chain acts as an SPI communication shift register;

� Daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI .

� Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave

� Applications that require a daisy chain configuration include SGPIO

(Serial General Purpose Input/Output ) and JTAG

Strengths of SPI

� Widespread support and IP available � Full duplex communication � Higher throughput than I²C � Complete protocol flexibility for the bits transferred (i.e. Not

limited to 8-bit words) � Simple Protocol to implement and understand � Typically no external circuitry required (like pullup resistors for

I²C) � System clocked by a master meaning that precision

oscillators and PLL not needed � Addressing not needed (decreases complexity and helps

throughput by not sending an address for each communication)

� Mostly shared lines for multiple devices (except the separate SS lines for each device)

Weaknesses of SPI

� No standards body governs SPI as an official protocol

� The more devices you have the more pins and connections necessary

� No hardware slave acknowledgment (the master could be "talking" to nothing and not know it)

� Does not support a multi-master architecture

� Only handles relatively short distances (meant for on-PCB communication mostly)

Applications

SPI is used to talk to a variety of peripherals, such as:

� Sensors: temperature, pressure, ADC, touchscreens

� Audio codecs, DAC

� Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11

� Memory: flash and EEPROM� Real-time clocks

� LCD displays, sometimes even for managing image data

� Any MMC or SD card (including SDIO variant)

I2C & SPI – A Comparison

Reference : Application Note AN4024 from Maxim

UART – Introduction

� A Universal Asynchronous Receiver/Transmitter (UART) is a

type of "asynchronous receiver/transmitter", a piece of

computer hardware that translates data between parallel and

serial forms.

� An example of UART communication is RS-232.

� UARTs are commonly included in microcontrollers.

� An UART is usually used for serial communications over a

computer or peripheral device serial port.

� Serial ports are used as a control console for diagnostics &

configuration.

� Many modern personal computers do not have a serial port

since this legacy port has been superseded by USB now.

Reference : Universal asynchronous receiver/transmitter. (2010, July 28). In Wikipedia, The Free Encyclopedia. Retrieved 15:14,

August 1, 2010, from http://en.wikipedia.org/w/index.php?title=Universal_asynchronous_receiver/transmitter&oldid=375909355

UART

� The Universal Asynchronous Receiver/Transmitter (UART)

controller is the key component of the serial communications

subsystem of a computer.

� The UART takes bytes of data and transmits the individual

bits in a sequential fashion. At the destination, a second

UART re-assembles the bits into complete bytes.

� The serial communication settings (Baudrate, No. of bits per

byte, parity, No. of start bits and stop bit and flow control) for

both transmitter and receiver should be set as identical

� The start and stop of communication is indicated through

inserting special bits in the data stream

Reference : Universal asynchronous receiver/transmitter. (2010, July 28). In Wikipedia, The Free Encyclopedia. Retrieved 15:14,

August 1, 2010, from http://en.wikipedia.org/w/index.php?title=Universal_asynchronous_receiver/transmitter&oldid=375909355

UART

� While sending a byte of data, a start bit is added first and a

stop bit is added at the end of the bit stream. The least

significant bit of the data byte follows the start bit.

� The ‘Start’ bit informs the receiver that a data byte is about to

arrive. The receiver device starts polling its ‘receive line’ as

per the baud rate settings

� If parity is enabled for communication, the UART of the

transmitting device adds a parity bit

UART

� The UART of the receiving device calculates the parity of the

bits received and compares it with the received parity bit for

error checking

� The UART of the receiving device discards the ‘Start’, ‘Stop’

and ‘Parity’ bit from the received bit stream and converts the

received serial bit data to a word

UART – Features

� Serial transmission of digital information (bits) through a

single wire or other medium is much more cost effective than

parallel transmission through multiple wires.

� The UART usually does not directly generate or receive the

external signals used between different items of equipment.

Typically, separate interface devices are used to convert the

logic level signals of the UART to and from the external

signaling levels.

RS-232 – Example Connection

RS-232 – Signal Lines

Pin Name

Pin No:

(For DB-9

Connecto

r)

Description

TXD 3 Transmit Pin. Used for Transmitting Serial

Data

RXD 2 Receive Pin. Used for Receiving serial Data

RTS 7 Request to send.

CTS 8 Clear To Send

DSR 6 Data Set ready

GND 5 Signal Ground

DCD 1 Data Carrier Detect

DTR 4 Data Terminal Ready

RI 9 Ring Indicator


� RS-232 is a point-to-point communication interface and the devices involved in RS-232 communication are called ‘Data Terminal Equipment (DTE)’ and ‘Data Communication Equipment (DCE)’

� If no data flow control is required, only TXD and RXD signal lines and ground line (GND) are required for data transmission and reception. The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper data transmission.

� If hardware data flow control is required for serial transmission, various control signal lines of the RS-232 connection are used appropriately. The control signals are implemented mainly for modem communication and some of them may be irrelevant for other type of devices


� The Request To Send (RTS) and Clear To Send (CTS) signals co-ordinate the communication between DTE and DCE. Whenever the DTE has a data to send, it activates the RTS line and if the DCE is ready to accept the data, it activates the CTS line

� The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data. The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication link. DTR should be in the activated state before the activation of DSR

� The Data Carrier Detect (DCD) is used by the DCE to indicate the DTE that a signal is being received

� Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the telephone line

RS-232 – Bus Speeds & Signal Levels

� The typical operational speeds of the RS-232 bus are:– 9600 bits/sec– 19200 bits/sec– 38400 bits/sec– 57600 bits/sec– 115200 bits/sec

RS-232 – Bus Speeds & Signal Levels

RS-232 – Null Modem

� Null modem is a communication method to connect

two DTEs directly using an RS-232 serial cable.

� The RS-232 standard is asymmetrical as to the

definitions of the two ends of the communications

link so it assumes that one end is a DTE and the

other is a DCE e.g. a modem.

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