Senior Capstone ProjectSenior Capstone Project

GPS Signal SimulatorGPS Signal SimulatorMay 2, 2006May 2, 2006

Benjamin HerreidBenjamin Herreid

Anthony HoehneAnthony Hoehne

Advisor: Dr. In Soo AhnAdvisor: Dr. In Soo Ahn

Sponsored By:Sponsored By:Tracking & Im aging System s Inc.

G PS Services and Technologies

OutlineOutline

Project DescriptionProject Description Block DiagramBlock Diagram SoftwareSoftware

• System InputsSystem Inputs• GUI ApplicationGUI Application• Software/Hardware InterfaceSoftware/Hardware Interface

HardwareHardware• FPGAFPGA• RF sideRF side

Results and Future WorkResults and Future Work

Project SummaryProject Summary

Global Positioning System (GPS)Global Positioning System (GPS)• Satellite based navigation systemSatellite based navigation system• Guaranteed worldwide coverageGuaranteed worldwide coverage

Solve problem backwardsSolve problem backwards Generate the simulated GPS signals Generate the simulated GPS signals

for up to 4 visible satellites (channels)for up to 4 visible satellites (channels) Use generated signals to drive a Use generated signals to drive a

commercial receivercommercial receiver

Project ApplicationProject Application

Model a scenario that uses GPS Model a scenario that uses GPS signalssignals

Useful in developing a GPS receiverUseful in developing a GPS receiver Much cheaper than physical testingMuch cheaper than physical testing

• AirplanesAirplanes• SpacecraftSpacecraft

Tests that are impossible in real lifeTests that are impossible in real life• RepeatabilityRepeatability• High-dynamicsHigh-dynamics

EquipmentEquipment PC – Windows XP, Parallel PortPC – Windows XP, Parallel Port FPGA – Altera CycloneFPGA – Altera Cyclone

• Altera UP3 Development BoardAltera UP3 Development Board D/A Converter, OpAmpD/A Converter, OpAmp

• MAX5184, 10 bitsMAX5184, 10 bits• LM311LM311

Mixer and OscillatorMixer and Oscillator• RF Signal GeneratorRF Signal Generator

Commercial ReceiverCommercial Receiver• Ashtech G8Ashtech G8

Block DiagramBlock Diagram

Input data: GUI, FilesInput data: GUI, Files Data from PC to FPGAData from PC to FPGA

• 2kHz, Digital2kHz, Digital GPS Signal to MixerGPS Signal to Mixer

• Analog, IF = 2.046 MHzAnalog, IF = 2.046 MHz• Sampling Rate = 8.184 MHzSampling Rate = 8.184 MHz

GPS Signal to ReceiverGPS Signal to Receiver• Analog, L1 = 1.57542 GHzAnalog, L1 = 1.57542 GHz

PC FPGAGPS

Receiver

TrajectoryCode Phase

Amplitude

GPS Signal (L1 Freq)

GPS Signal(IF)

Oscillator(L1 – IF)

MixerStarting Location

Date/TimeAlmanac

Antenna Pattern

SV Number

PC Data PathPC Data Path

Traj

MV_Trajgen

Strapdown

Phasetru

EnRAP v9.0b

Pos File

ΔV/Δθ File

ECEF File

Bin File

Frame File

Vis File

Phase File

Almanac File

Antenna File

Tracking & Im aging System s Inc.

G PS Services and Technologies

Trajectory FileTrajectory File

ProprietaryProprietary Duration of JerkDuration of Jerk 4 axes: Roll, Pitch (Elevation), Yaw 4 axes: Roll, Pitch (Elevation), Yaw

(Heading), Thrust(Heading), Thrust

Roll Pitch Yaw

Initial ConditionsInitial Conditions

33rdrd Derivative Derivative Requires initial conditions for lower Requires initial conditions for lower

order parametersorder parameters• Acceleration: 0Acceleration: 0• Velocity: 0Velocity: 0• Attitude: 0 (level, due North)Attitude: 0 (level, due North)• Position: Specified by UserPosition: Specified by User

Almanac and Antenna FilesAlmanac and Antenna Files

Almanac FileAlmanac File• Standard - Rinex 2Standard - Rinex 2• Ephemeris DataEphemeris Data

Antenna FileAntenna File• ProprietaryProprietary• Antenna GainAntenna Gain• Azimuth, ElevationAzimuth, Elevation

Phase and Visibility FilesPhase and Visibility Files

Phase FilePhase File• Phase (distance) to each satellite in Phase (distance) to each satellite in

radiansradians• At fixed frequency, wavelength is At fixed frequency, wavelength is

constant so phase and distance are constant so phase and distance are interchangeable (finterchangeable (fλλ=c)=c)

Visibility FileVisibility File• Azimuth and Elevation of each satelliteAzimuth and Elevation of each satellite• Signal Power from each satelliteSignal Power from each satellite

Application ScreenshotApplication Screenshot

Application ScreenshotApplication Screenshot

PC to FPGA CommunicationPC to FPGA Communication

SVN: 5 bitsAmplitude: 7 bitsRoll Flags: 2 bitsPhase: 18 bits

Total: 32 bits4 bytes

4 Channels

Minimum Communication Rate:4 bytes/channel x 4 channels x 2kHz Update Rate = 32kHz

7 6 5 4 3 2 1 02 1 0Byte 1

7 6 5 4 3 2 1 03 2 1 01 0Byte 2

7 6 5 4 3 2 1 0Byte 3

7 6 5 4 3 2 1 0Byte 4

OutlineOutline

Project DescriptionProject Description Block DiagramBlock Diagram SoftwareSoftware

• System InputsSystem Inputs• GUI ApplicationGUI Application• Software/Hardware InterfaceSoftware/Hardware Interface

HardwareHardware• FPGAFPGA• RF sideRF side

Results and Future WorkResults and Future Work

FPGA CalculationsFPGA Calculations

Interpolate Code Phase

due to distance(18-bit)

Next Code PhasePrevious Code Phase

Sample Clock

Select Current Code Chip

from Lookup Table

Convert to Carrier lookup

table index

SV #Code Chip

Carrier (7-bit)

Interpolate Amplitudes

(7-bit)Sample Clock

Next Amplitude

Previous Amplitude Current Amplitude

Multiply Sum All 4 Channels

10-bit D/A Fs = 8.184

MHz

3 other channels

(One instance only)

Integer

Fractional

Wrap Flags

(From Communication Section)

Adder (Θd + Θt)

Calculate code phase due to time

Interpolation WrappingInterpolation Wrapping

Signal SpectrumSignal Spectrum

BT = 2.046 MHz

f(MHz)Fs =8.184IF=2.046

Spectrum at IF with Sampling Effects

2.046 MHzL1=1575.42

Receiver Filter

f(MHz)

LO=1573.374

Spectrum at L1

BW=1.023f(MHz)

RF SubsystemRF Subsystem

D/A converterD/A converter• MAX5184 – 10 bitMAX5184 – 10 bit

40MHz, Differential voltage output40MHz, Differential voltage output LM311 OpAmpLM311 OpAmp

• Conversion to single-ended signalConversion to single-ended signal Mixer and signal generatorMixer and signal generator AttenuationAttenuation

• -130dBm required for receiver-130dBm required for receiver• 90dB attenuation needed (-40dBm at D/A)90dB attenuation needed (-40dBm at D/A)

ResultsResults

PCPC• GUI finishedGUI finished• Individual programs runIndividual programs run• Data ready for packingData ready for packing

FPGAFPGA• Single channel nearly completedSingle channel nearly completed• Problems with Quartus IIProblems with Quartus II

RFRF• D/A – Not completedD/A – Not completed• Mixer – Experimented, not implementedMixer – Experimented, not implemented

SimulationsSimulations

Interpolation and lookup table indexing

SimulationsSimulations

C/A code generation for SV #1 / Ch 1

Future WorkFuture Work

Establish CommunicationEstablish Communication Add navigation dataAdd navigation data Additional featuresAdditional features

• Ionosphere and troposphere effectsIonosphere and troposphere effects• MultipathMultipath• Additional channels (multiple FPGA’s)Additional channels (multiple FPGA’s)• Instrument panel in GUIInstrument panel in GUI

Questions?Questions?

RF ExperimentingRF Experimenting