seminar_ppt (2) [compatibility mode]

7/28/2019 Seminar_ppt (2) [Compatibility Mode]

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SIDDAGANGA INSTITUTE OF TECHNOLOGY, TUMKUR(ANAUTONOMOUS INSTITUTION UNDERVISVESVARAYATECHNOLOGICAL UNIVERSITY, BELGAUM)

Under the guidance

Analysis of Ultra Low Power Fully Programmable

Frequency Divider

Project Seminar on

By:

Ajay Kumar 1SI09EC005

Ananda T Anaji 1SI09EC011

Apoorva prakash 1SI09EC118

Navaneeth B H 1SI09EC024

Mr. B. Sudarshan, M.E.,

Associate professor

Department of E&C

SIT, Tumkur

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

2012-13


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OUTLINE

Introduction

Pulse swallow frequency divider

Different Prescaler architectures

Delay and power consumption

Fully programmable divider

Conclusion

References

2


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OBJECTIVE

Focuses on reducing the power consumption andincreasing the operating frequency

To choose suitable Prescaler architecture for

specific application

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MOTIVATION

The Prescaler is one of the most critical blocks in

synthesizer since, it operates at highestfrequency and consumes large amount of power.

e power re uc on n e rs s age o e

Prescaler is important in realizing a low power

frequency synthesizer.

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DIFFERENT PRESCALERS

TSPC

E-TSPC

Conventional TSPC 2/3 prescaler

Design-I 2/3 prescaler

Design-II 2/3 prescaler

TSPC 32/33 and 47/48 prescaler

Fully programmable Divider: 32/33 prescaler Fully Programmable Divider: 47/48 prescaler

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PULSE SWALLOW FREQUENCY DIVIDER

6

Figure : courtesy : [1]


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PULSE SWALLOW FREQUENCY DIVIDER

(CONTD..)

Prescaler is an electronic counting machine used

to reduce a high frequency electrical signal tolower frequency by integer division

pera es a g es requenc es an consumes

more power

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THEORY OF OPERATION

Prescaler divides the input frequency by N+1 or N

based on the modulus control

Program counter and Swallow counter divides the

output by a fixed value of P and S respectively

Start from the reset, prescaler divides by N+1 until

swallow counter is full

After (N+1)S pulses at the input, the modulus control

changes to N and continues to count until P counter is

full.

Total pulses = (N+1)S + N(P-S) = NP+S

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HOW TO REDUCE THE POWER

CONSUMPTION

By decreasing the size of the transistors

By reducing the number of switching gates

By blocking the power supply to one of the D flip

flop during divide-by-2 operation

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CURRENT-MODE LOGIC DIVIDERS

Very sensitive to input amplitude

Requires buffers or level shifters at the output

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DYNAMIC LOGIC DIVIDERS

The CMOS latches eliminates the static current

consumption and use fewer transistors than theCML latches.

e sw c ng spee o e s a c c rcu s epen s

on two factors namely;

Current conduction level through a MOS

transistor

Parasitic capacitances

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SYNCHRONOUS 2/3 PRESCALER

12

Figure : courtesy : [1


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TSPC

Hold Mode:

Clk=0, M2=ON S1 charges

M4=ON S2 Charges to VDD

M7=OFF & M8=OFF Floating O/P

Evaluation Mode:

Clk=1, M2=OFFM5 =ON & M6=ON S2 discharges

through M5 & M6

13

RESULTS >>RESULTS >>RESULTS >>RESULTS >>Figure : courtesy : [1


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EXTENDEDTSPC (E-TSPC)

14

RESULTS >>RESULTS >>RESULTS >>RESULTS >>Figure : courtesy : [1]


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SHORT CIRCUIT POWER IN E-TSPC

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POWER CONSUMPTION OF TSPCAND

E-TSPC

1.175

1

1.2

1.4

Power consumption of TSPC and E-TSPC flip-flop (mW)

16

0.0647

0

0.2

0.4

0.6

0.8

TSPC E-TSPC


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PROPAGATION SPEED COMPARISON

The output load capacitance of E-TSPC is lower than

that of TSPC.

The charging time constant of E-TSPC is smaller

than TSPC.

The ropagation delay of TSPC stage is higher thanthat of the E-TSPC stage.

This implies that TSPC flip-flop has a lower operating

frequency compared to that of the E-TSPC flip-flop.

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POWER CONSUMPTION ANALYSIS

Total power consumption of a digital circuit is given

by

(3)

Switching ower depends on fclk and CL

Short circuit power is due to conduction of current

directly from the supply to ground.

Leakage power due to leakage current which is

technology dependent.18


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POWER CONSUMPTION ANALYSIS(CONTD..)

TSPC circuits cause more switching power than E-TSPC

circuits.

Switching power can be reduced by optimization

techniques such as reducing the number of switching

sta es and the width of the transistors.

19

In TSPC circuits, one of the transistors in each stage is

always off, there exists NO short-circuit power.

Large short-circuit power and considerable amount of

switching power makes the E-TSPC logic less suitable of

low power applications compared to TSPC.


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CONVENTIONAL TSPC 2/3 PRESCALER

20

Due to the large load on DFF2 and difficulty to embed theOR, AND gates into the DFF which introduces additional

delay and the speed of conventional 2/3 prescaler.

Also causes more power dissipation.



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CONVENTIONAL TSPC 2/3

PRESCALER(CONTD..) The maximum operating frequency of the conventional

2/3 prescaler is limited due to the logic OR and logic

AND gates.

The conventional TSPC 2/3 prescaler has 12 stages

21

and each stage has a switching output node.

The switching power is given by

(4)

RESULTS >>RESULTS >>RESULTS >>RESULTS >>


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TSPC 2/3 PRESCALER: DESIGN-I

22Figure : courtesy : [1]


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DIVIDE-BY-2 OPERATION

When MC= 1, transistor M10 turns-on and node S3 switches to

logic 0 irrespective of the data at node S2.

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DIVIDE-BY-3 OPERATION

When MC= 0 , transistor M10 turns-off and the inverted data at

node S2 is passed to the node S3.

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PROPAGATION DELAY OF THE 2/3

PRESCALER

The total propagation delay in divide-by-2 mode of operation is

equal to the propagation delay of DFF2.

In v e- y- mo e o operat on, s nce ot DFF an DFF

are active, the propagation delay is equal to the sum of

propagation delay of embedded NOR gate DFF1 and DFF2

respectively

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SWITCHING POWER OF DESIGN-I

The switching power saved by Design-I prescaler is

almost 42% and its speed is improved by 1.3 times

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SHORT-CIRCUIT POWER OF THE

DESIGN-I 2/3 PRESCALER During the divide-by-2 mode when control logic signal

MC = 1, the transistor M10 turns-on, allowing a direct path

from supply to ground when transistor M7 turns-on.

The power consumption of the prescaler is given by the sum of

switching power in DFF1 and DFF2, short circuit power in 3rd

stage of DFF1 and short circuit power in DFF2.

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TSPC 2/3 PRESCALER: DESIGN-II

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DESIGN II(CONTD..)

An extra PMOS transistor M1a is connected between the

power supply and DFF1 whose input is the controlled by

the logic signal MC.

continuous switching at the nodes S1 and S2

respectively.

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DESIGN II-DIVIDE-BY-2 OPERATION

30



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DESIGN-IITSPC 2/3PRESCALER:DIVIDE-BY-

2OPERATION

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POWER SAVINGANALYSIS IN DIVIDE-BY-2

OPERATION

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POWER ANALYSIS(CONTD..)

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POWERANALYSIS(CONTD..)



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POWER CONSUMPTION COMPARISON

2.655

Power consumption (mW)

35Conv. E-TSPC Conv. TSPC Design-I Design-II Divide by 32 Divide by 47

1.421

1.213

0.6310.7331

1.141


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2.541



1.138

0.8951 0.893

1.0461.141


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DESIGN ANDANALYSIS OF TSPC 32/33

(N/N+1) PRESCALER

To verify the advantages of the proposed ultra-

low power prescaler of Design-II, a divide 32/33

dual modulus unit is implemented with the 2/3

prescaler of Design-II

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TSPC 32/33 PRESCALER USING DESIGN-II

2/3 PRESCALER

In this 32/33 prescaler, the proposed 2/3 prescaler

unit is followed by four stages of the toggled

TSPC divide-by-2 units

38

RESULTS >>RESULTS >>RESULTS >>RESULTS >>Figure : courtesy : [1]


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TSPC 47/48 PRESCALER USING DESIGN-II

39



F P F D I


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FULLYPROGRAMMABLE FREQUENCYDIVIDER-I

40

Fig.1 Programmable frequency divider


7 BIT PROGRAMMABLE P COUNTER


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7-BIT PROGRAMMABLE P-COUNTER

41


END OF COUNT (EOC)


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END OF COUNT (EOC)

42

The EOC logic circuit is used to detect when the P-counter reaches

the state Q1Q2Q3Q4Q5Q6Q7=0000000

The output of EOC logic circuit goes low P-counter is loaded with the

preset value.

Fig.3 EOC of p-count Figure : courtesy : [4]


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RELOADABLE TSPC DFF FOR P-COUNTER

43

The signals LD and LDB are used to reload the programmable

state of the FF.

When (PI) of the each FF is loaded with a value and LD signal goes

low, the P-counter begins to count down.

FF remains in the divide-by-2 mode until the counter reaches the

state 0000010.

Fig.2 Reloadable DFF


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RELOADABLE TSPC DFF FOR S-COUNTER

44

When SP goes high, the S-counter remains idle for a period of

N*(P-S) clock cycles.

5-BIT PROGRAMMABLE S-COUNTER


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45



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END OF COUNT (EOC)

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FULLYPROGRAMMABLE FREQUENCYDIVIDER-II

47



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48


6 BIT PROGRAMMABLE P COUNTER


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6-BIT PROGRAMMABLE P-COUNTER

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CONCLUSION

Design II 2/3 prescaler is capable of operating

upto 4.5GHz and the amount of power saved is

60% and 45% in divide-by-2 and divide-by-3respectively, compared to conventional 2/3

rescaler.

Fully programmable divider consumes a power of

0.934mW at 1.8v and the duty cycle of the output

is 1MHz signal is close to 47%.

50

R


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REFERENCES

[1] M.Vamshi Krishna et.al, Design and Analysis of Ultra-Low

Power True-Single-Phase Clock CMOS 2/3 Prescaler, IEEE Trans.

On Circuits and Systems-I: Reg. Papers, Vol.57, no.1, pp. 72-

82, Jan. 2010.

[2] John P. Uyemura, CMOS Logic Circuit Design, Springer edition

2001.

[3] X. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma, Design

and optimization of the extended true single-phase clock-based

prescaler, IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, Nov.

2006.

S. Pellerano, M.Vamshi Krishna, C. Samori, and A. L. Lacaita, A

Low Power Fully Programmable 1MHz Resolution 2.4GHz CMOS

PLL Frequency Synthesizer IEEE J. Solid-State Circuits, vol.

39, no. 2, pp. 378383, Feb. 2004.

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THANK YOU


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TSPC SCHEMATIC

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WAVEFORM OF TSPC

54

DELAY AND POWER CONSUMPTION OF


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TSPC FLIP-FLOP

Parameters With parasitics Without parasitics

Operating voltage (V) 1.8 1.8

Max. operatingfreq.(MHz)

2.5 2.5

Output frequency (MHz) 1.25 1.25

55

tpHL(ps) 37 27

tpLH (ps) 88 73

tp (ps) 62.5 50

Power consumption

(uW)

64.71 45.93


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LAYOUT OF TSPC

56


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CIRCUIT INVENTORY OF TSPC FLIP-FLOP

LIBRARY CELL VIEW TOTAL

analogLib Pcapacitor Symbol 142

57

analogLib Presistor symbol 47

gpdk180 nmos ivpcell 5

gpdk180 pmos ivpcell 4


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WAVEFORM OF E-TSPC FLIP-FLOP

58

DELAY AND POWER CONSUMPTION OF E-


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DELAY AND POWER CONSUMPTION OF E-

TSPC FLIP-FLOP

Parameters With parasitics Without parasitics

Operating voltage (V) 1.8 1.8

Max. operating

freq.(MHz)

2.5 2.5

59

(MHz)

. .

tpHL(ps) 50 40

tpLH (ps) 20 15

tp (ps) 35 27.5

Power consumption

(mW)

1.175 1.173


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LAYOUT OF E-TSPC

60


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CIRCUIT INVENTORY OF E-TSPC

LIBRARY CELL VIEW TOTAL

analogLib Pcapacitor symbol 121

61

gpdk180 nmos ivpcell 3

gpdk180 pmos ivpcell 3

CONVENTIONAL TSPC 2/3


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PRESCALER SCHEMATIC

62

WAVEFORMS OF CONVENTIONAL TSPC 2/3


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PRESCALER IN DIVIDE BY-2 MODE

63

LAYOUT OF CONVENTIONAL TSPC 2/3



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PRESCALER IN DIVIDE BY2 MODE

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65

LAYOUT OF CONVENTIONAL TSPC 2/3


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66


CONVENTIONAL TSPC


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Parameters Divide By

2 mode

With

parasitics

Divide by

2 mode

Without

parasitics

Divide by

3 mode

With

parasitics

Divide by

3 mode

Without

parasitics

Operatingvoltage (V)

1.8 1.8 1.8 1.8

Max.

operating2.5 2.5 2.5 2.5

freq.(GHz)

Outputfrequency

(GHz)

1.25 1.25 0.833 0.833

tpHL(ps) 41 30 45 30

tpLH

(ps)58 34 66 35

tp (ps) 49.5 32 55.5 32.5

Power

consumption

(mW)

1.421 0.978 1.433 1.13867

CIRCUIT INVENTORY OF CONVENTIONAL


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TSPC

LIBRARY CELL VIEW

Divide by

2 mode

TOTAL

Divide by

3 mode

TOTAL

analogLib Pcapacitor symbol 626 615

216 218

gpdk180 nmos ivpcell 18 18gpdk180 pmos ivpcell 16 16

68

DESIGN-I 2/3 PRESCALER SCHEMATIC


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DESIGN I 2/3 PRESCALER SCHEMATIC

69

WAVEFORM OF DESIGN-I PRESCALER IN


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DIVIDE-BY-2 MODE

70

LAYOUT OF DESIGN-I PRESCALER IN DIVIDE-

BY-2 MODE


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71

WAVEFORMS OF DESIGN-I PRESCALER IN


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DIVIDE-BY-3 MODE

72

LAYOUT OF DIVIDE-BY-3 OPERATION OF


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DESIGN-I 2/3 PRESCALER

73


DESIGN-I PRESCALER


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Parameters Divide By2 mode

With

parasitics

Divide by2 mode

Without

parasitics

Divide by3 mode

With

parasitics

Divide by3 mode

Without

parasitics

Operating

voltage (V) 1.8 1.8 1.8 1.8

Max.

operating4.5 4.5 4.5 4.5

74

req. z

Outputfrequency

(GHz)

2.25 2.25 1.5 1.5

tpHL(ps) 49 48 34 28

tpLH (ps)

69 69 45 32tp (ps) 59 58.5 39.5 30

Power

consumption

(mW)

1.412 1.213 1.341 0.8951

DESIGN-II 2/3 PRESCALER SCHEMATIC


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75

WAVEFORMS OF DESIGN-II 2/3 PRESCALER


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IN DIVIDE-BY-2 MODE

76

LAYOUT OF DESIGN-II 2/3 PRESCALER IN


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DIVIDE-BY-2 MODE

77

WAVEFORMS OF DESIGN-II 2/3 PRESCALER


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IN DIVIDE-BY-3 MODE

78

LAYOUT OF DESIGN-II 2/3 PRESCALER IN


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DIVIDE-BY-3 MODE

79

C


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Parameters Divide By2 mode

With

parasitics

Divide by2 mode

Without

parasitics

Divide by3 mode

With

parasitics

Divide by3 mode

Without

parasitics

Operating

voltage (V) 1.8 1.8 1.8 1.8

Max.

operating4.5 4.5 4.5 4.5

80

req. z

Outputfrequency

(GHz)

2.25 2.25 1.5 1.5

tpHL(ps) 49 48 34 28

tpLH (ps) 69 69 45 32

tp (ps) 59 58.5 39.5 30

Power

consumption

(mW)

1.412 1.213 1.341 0.8951

DIVIDE-BY-32 SCHEMATIC


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81

WAVEFORMS OF TSPC 32/33 PRESCALER


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IN DIVIDE-BY-32 MODE

82

LAYOUT OF TSPC 32/33 PRESCALER IN


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DIVIDE-BY-32 MODE

83

DIVIDE-BY-33 SCHEMATIC


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84

WAVEFORMS OF TSPC 32/33 PRESCALER IN

DIVIDE-BY-33 MODE


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85

LAYOUT OF TSPC 32/33 PRESCALER IN DIVIDE-

BY-33 MODE


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86

WAVEFORMS OF TSPC 47/48 PRESCALER IN

DIVIDE-BY-47 MODE


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87

LAYOUT OF TSPC 47/48 PRESCALER IN DIVIDE-

BY-47 MODE


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88

WAVEFORMS OF TSPC 47/48 PRESCALER

IN DIVIDE-BY-48 MODE


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89

LAYOUT OF TSPC 47/48 PRESCALER IN

DIVIDE BY 48 MODE


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DIVIDE-BY-48 MODE

90

DELAY AND POWER CONSUMPTION


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Parameters Divide By

32 mode

Divide by 33

mode

Divide by 47

mode

Divide by 48

mode

Operating

voltage (V)

1.8 1.8 1.8 1.8

Max.

operating2.5 2.5 2.5 2.5

91

.

Output

frequency(GHz)

0.078 0.075 0.053 0.052

tpHL(ps) 160 150 240 230

tpLH (ps) 110 130 140 130

tp (ps) 135 140 190 180

Power

consumption

(mW)

733.1 1.046 1.141 1.141



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2.655



1.421

1.213

0.6310.7331

1.141



93/93

2.541



1.138

0.8951 0.893

1.0461.141

seminar_ppt (2) [compatibility mode]

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