r&d of interconnections for belle ii and slhc

H.-G. MoserMax-Planck-Institut

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VERTEX 2010 Loch Lomond June 10, 2010

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R&D of interconnections for Belle II and sLHC

R&D projects at the MPI semiconductor laboratory

• Requirements for ATLAS and Belle II pixel detectors

• Hybrid pixel detectors versus monolithic sensors

• DEPFETs for Belle II

• 3D integration for sLHC


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ATLAS: Hybrid Pixel Detectors

+ Large signal, good S/N+ High processing power in each pixel

fast, high rate capability+ Can be made very radiation hard

- Material (Sensor & ASIC, connectivity, tiling)- Large power dissipation (need active

cooling -> mass)- Cost driver: interconnection (non-standard high density bump bonding

50µm pitch)


Radiaton hardness (bulk damage)Fast readout with good timing (25 ns)

High momentum tracks: material less an issue (but still important)

Hybrid pixel detector (2 tier) & 3D interconnection


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Belle II: Monolithic Detectors

+ low mass+ (almost) no interconnection (but need few ASICs with large pitch > 150µm)- Slow (frame readout, rolling shutter)

nn+

p p

p

n nn

+ ‘standard CMOS’ process+ complex CMOS circuit

(but limited to NMOS)- small signal, slow collection- Area limited by chip size

CMOS Sensors (MAPS)DSM CMOS with epil layer as sensor

DEPFETFET on fully depleted bulk

- non standard double-sided process

- simple, one stage amplifier+ large signal, fast collection+ wafer size sensors VERTEX 2010

Loch Lomond June 10, 2010

Radiation hardness (ionizing)Moderate fast readout (20 µs)

Soft tracks: O(1 GeV) < 0.2% X0 requiredMonolithic active pixel sensor (DEPFET)

Integrate readout electronics (amplification) into sensor


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DEPFETEach pixel is a p-channel FET on a completely depleted bulk

A deep n-implant creates a potential minimum for electrons under the gate (“internal gate”)

Signal electrons accumulate in the internal gate and modulate the transistor current (gq ~ 400 pA/e-)

Accumulated charge can be removed by a clear contact (“reset”)

Fully depleted: Þ large signal, fast signal collection

Low capacitance, internal amplification: => low noise

High S/N even for thin sensors (50µm)

Rolling shutter mode (column parallel) for matrix operationÞ 20 µs frame readout time=> Low power (only few lines powered)

n x mpixel

IDRAIN

DEPFET- matrix

VGATE, OFF

off

off

on

off

VGATE, ON

gate

drain VCLEAR, OFF

off

off

reset

off

VCLEAR, ON

reset

output

0 suppressionVCLEAR-Control

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DEPFET Performance

Low noise: x-ray spectroscopy and imaging

High speed -> noise ~ t-1/2

At 50MHz: ENC < 40e (for 50ns readout )

For tracking: even thinned (but fully depleted) detectors have excellent S/N

S/N > 200 measured for d=450 mmS/N ~ 40 achievable for d=50 mmPosition resolution < 2 mm in beam tests

Fe55: 1.6 e- rms noise, Room temperature !10 ms shaping time



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Pixels: 50 x 50(75) µm 75µm thick 0.18% X02 layers: @1.4(2.2) cm

Thickness:75 µm

total of 8 Mpx

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DEPFET for Belle II

Power consumption in sensitive area: 0.1W/cm² => air-cooling sufficient

Barcelona (Uni, CNM, Ramon Lull), Bonn, Heidelberg,Giessen, Göttingen,Karlsruhe, Krakow, Munich (MPI, TU, LMU), Prague, Santander, Santiago de CompostellaValencia, KEK



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Sensor Thinning

?

Process backsidee.g. structured implant

sensor wafer

handle wafer

1. implant backsideon sensor wafer

2. bond sensor waferto handle wafer

3. thin sensor sideto desired thickness

4. process DEPFETson top side

5. structure resist,etch backside upto oxide/implant

Industry: TraciT, GrenobleHLL HLL main lab HLL special lab

sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







sensor wafer

handle wafer







Wafer bondingSOI process

Thinning of top wafer (CMP)

Processing etching of handle wafer (structured)

diodes and large mechanical samples Belle II module

Need thin (50µm-75µm) self supporting all silicon module



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ASICs for control and readoutSwitcher (Heidelberg)

DCD (Heidelberg)

DHP (Bonn)• Common mode correction• Pedestal subtraction• (16 events average)• DCD offset compensation

(2bit)• Switcher control• Test chip (1/2)• 32 channels• C4 bump bonding• Submitted IBM 90nm

• Produced in UMC 180nm

In order to get a very compact module layout bump bonding is needed for the interconnection to the DEPFET sensor

Moderate pitch 150 to 200 µm

Use standard processes whenever available

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Interconnection: Bump BondingDCD (UMC 180nm) :MPW delivered with bumps (SnAgCu, pitch 180µm)

DHP (IBM 90nm) MPW delivered with C4 bumps(SnAg, pitch 200µm)

Switcher: no bumping offered by AMS for MPW => in house (Heidelberg)



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Cu UBM compatible with DEPFET technology?

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Sensor test structes prepared at HLL

CNM, Barcelona

sputter barier and seed layerCu electroplating

Sputter and Cu plating is presently being implemented asbackend process at the HLL(also for other projects: XFEL, sLHC…)

Correlation of leakage currents before and after UBM



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Future: 3D integrationPerformance of DEPFET sensors ultimatelylimited by slow frame readoutBX identification not possible, long integration time

Hybrid pixel detectors offer high processing power per pixel

Need to reduce material, cost (fine pitch bump bonding) and power

3D integration: Evolution of hybrid pixels

high density, low mass interconnection of several (thin) layers (tiers)‘quasi-monolithic detectors’

Si pixel sensor


Optimized Module Design: Less material:

• thin sensors and ASICs• higher fill factor• Reduced cantilever• backside connectivity• slim edges

Radiation hardness:thin sensors improve CCE (rtapping)


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MPI 3D R&D Program Build demonstrator using ATLAS pixel chip (FE-I2/3) and thin pixel sensors made by MPI

(complete wafers with FEI2, FEI3 chips available!)

Use interconnection technology allowing postprocessing

Interconnection with SLID and ICV technology by Fraunhofer IZM

Demonstration of postprocessing of standard ASICs with via last

R&D Issues:

• Technology: compatible with sensors, ASICs?

• Interconnection quality: e.g. capacitance

• Yield & Costs.

• Production in industry. • Material (copper layer).



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Sensors

In house production onFZ-SOI material (2 kWcm)

Detector wafer thickness75 µm and 150 µm

p- and n-type materialp-spray insulation

Udep 20V and 80V(before irradiation)

~ 100% CCE at 1016 n/cm²

75 µmVERTEX 2010 Loch Lomond June 10, 2010


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IZM SLID Process

• Alternative to bump bonding (less process steps “low cost” (IZM)).• Small pitch possible (<< 20 mm, depending on pick & place precision).• Stacking possible (next bonding process does not affect previous bond).• Wafer to wafer and chip to wafer possible.

• However: no rework!



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Inter Chip Vias

• Hole etching and chip thinning• Via formation with W-plugs.• Face to face or die up connections.• 2.5 Ohm/per via (including SLID).• No significant impact on chip performance (MOS transistors).

ICV = Inter Chip Vias

Etching (Bosch process)

Insulation, filling with tungsten

Electroplating, metallisation

Back thinning

Electroplating, metallisation



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Test of SLID interconnection with metal dummies.

Aim: determine the feasibility of the SLID inter-connection within the parameters we need for the ATLAS pixels.

Test of the mechanical strength as a function of different area coverage by the SLID pads

Test the SLID efficiency varying the dimensions of the SLID pads

Study the SLID efficiency when degrading the planarity of the structure underneath the pads

Determine the alignment precision between single “chip” and “detector” wafer

Investigate the BCB isolation capability between the detector and chip surfaces

Tests of metal dummies

SLID Pad

27x58 mm2

10% SLID coverage

SLID Pad 27x360 mm2

50% SLID coverage

20 um

30 um

15 um

25 um

SiO2

Al

Cu3Sn

Al

BCBVERTEX 2010 Loch Lomond June 10, 2010


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Test interconnections (SLID)

Number ofPad width Pitch Aplanarity measured SLID SLID Resistance per

[μm2] [μm] pads Inefficiencyconnection [Ω]30 x 30 60 0 8288 <4.4x10-4 0.73±0.4780 x 80 115 0 1120 <3.3x10-3 0.29±0.2680 x 80 100 0 1288 <2.9x10-3 0.25±0.1240x40 70 0 2016 <1.5x10-3 0.37±0.2630 x 30 60 100 nm 5400 (10±4)x10-4 0.58±0.4630 x 30 60 1 μm 5400 (4±3)x10-4 0.58±0.40

Special test wafers for SLID testsChains of SLID connections



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Problems

Pad size 80x80 µm²Pitch 100 µm

Shorts:

No problems with small pads(30 x 30 µm² and 50 x 50 µm²)

However, many shorts for larger pads(80 x 80 µm²)

Amount of tin needs to be adjusted according to pad size and coverage (pressure)

Bad connection:

Some chips fell offDifferences in height: some chips not in proper contact!

Þ Chips came from different wafers (some 20 µm tolerances!)

Þ Different chip sizes lead to variations of local pressure

Use chips from same wafers (or make sure that they have equal thickness

Look even at radial position of chip on wafer (wafer thickness spherical)

Use only chips of same size



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Project Status

Cu electroplating of FEI3 chips for SLID UBM done

Dummy pads needed for extra mechanical strength

Pixel pads

Dummy pads (Type A)

1

2

3 Identification of Target area for ICV etching: Investigation with a FIB analysis to identify

possible areas for TSV etching:

1) Central region between pads: filling structures with superimposed tungsten plugs and metal layers

2) Covered by top metal layer in some pads3) ICV directly over the pad area after having

etched away the top aluminum layer



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Next Steps

Sensor/ASIC interconnection using SLID- ASIC thinned to 200 µm- No vias, integrated fanout on sensor for service connection

Sensor/ASIC interconnection using SLID-ASIC thinned to 50 µm-vias for service connections (fanouts for redundancy)

Future: SLID interconnection of sensors/ 3D FEI4

Sensor/ASIC interconnection using SLID- ASIC thinned to 200 µm- No vias, integrated fan-out on sensor for service connection

Sensor/ASIC interconnection using SLID-ASIC thinned to 50 µm-vias for service connections (fan-outs for redundancy)

Future: SLID interconnection of sensors/ 3D FEI4



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Summary

DEPFETs for Belle II:

precision vertex detector optimized for low momentum tracksemphasis on low mass and low powerradiation hard up to 10 Mradfast frame readout for low occupancy despite high backgroundthin, self supporting all-silicon detectorslow number of large pitch interconnectsuse industry standard bump bonding

3D integration of sensor and ASIC for sLHC

SLID interconnection as alternative to fine pitch bump bondingvias for backside connectivity (4-side buttable)3D integration using via last postprocessing

thin sensors for radiation hardness (1016 n/cm²)


r&d of interconnections for belle ii and slhc

Documents

loch lomond

depleted detectors

low noise high sn

ns readout

low power

time vertex

large pitch

d interconnection