slhc meeting cern, 21 may 2008

SLHC MeetingCERN, 21 May 2008

Presented by

C.-E. WulzC.-E. Wulz

Global Triggers,Global Triggers,TCA TechnologyTCA Technology

M. StettlerM. Stettler, M. Hansen (CERN) , M. Hansen (CERN) C. Foudas, G. Iles (Imperial College)C. Foudas, G. Iles (Imperial College)

J. Jones (Princeton)J. Jones (Princeton)A. TaurokA. Taurok, H. Bergauer, C.-E. Wulz (Vienna), H. Bergauer, C.-E. Wulz (Vienna)

C. - E. Wulz 2 SLHC Trigger Meeting, May 2008

Global Trigger Concepts for LHC and SLHC

FDL

GTL

GTL

128 Algo

GMT

PSBGCT

Syncdelay

Syncdelay

REC

COND ALGO

PSBSyncdelay

Technical Triggers

FDL chip

GTL

COND chip

GMTOptical links

GCT

Syncdelay

Syncdelay

SYNCSyncdelay

‘Conditions’

COND chip

nn Algo

(and,or,

not)

FPGA:Standard Conditions

- FPGA: DSPs (XC5V100T)

- FPOA: DSP array

TrackerTrigger

Syncdelay

Prescalers&

Trigger Counters

FinalOR

FinalOR

COND ALGO

LHC

SLHC

Tracker ‘Conditions’ Prescalers&

Trigger Counters

Totem, Castor, ZDC, BTPX, BSC, …

Totem, Castor, ZDC, BTPX, BSC, …


Global Trigger Concepts for LHC and SLHC

• Synchronize all Trigger Objects to arrive at the same time at the logic chip– 2008 Version: Muons: done by GMT; Calo_objects: done by PSB; Technical Triggers: done by PSB– SLHC Version: Muons: done by GMT; Calo_objects: done by GCT; TechTrig: done by SYNC chip

Tracker: done by Tracker_Trigger

• Send all Trigger Objects into one chip to be able to make any correlations between them• Use an FPGA to change trigger conditions as required by physics

– New trigger setup: -> configure FPGA with new trigger conditions– New parameter values for same setup:– 2008 Version: Load new ET and pT thresholds by software

– SLHC Version: Load all values by software ( Upgrade Version)

• Calculate physics trigger algorithms in parallel (FPGA branch)– 2008 Version: 128 Algorithms, limited by board layout, connectors and chip size

– SLHC Version: Extend to ‘nn’ Algorithms <- ‘Algo’ signals inside chip (chip size will be the only restriction)

• Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm– SLHC: maybe more requirements

• SLHC Version: – Array of DSPs for complex physics triggers

• C++ code -> trigger program with constant latency(!)– Each trigger object is received twice, on 2 optical links


Input to Global Trigger

• Global Calorimeter Trigger (GCT): redefinition (reduction?) of trigger data• 4 e/, 4 isolatetd e/ 4 e/ with ISOLATION bit• 4 central jets, 4 forward jets n jets• 4 tau jets• total_ET, HT apply set of thresholds in GCT

and send resulting bits to FDL chip

• missing_ET

• “jet counts” (now towers above thr., ring ’s)• More than 4 objects per type: 5 or 6 (?) Simulation for SLHC

• Global Muon Trigger (GMT):• 4 muons pmip, iso, charge, quality

• Tracker Trigger:• Tracks/jets with and COND chips• ‘Conditions’ calculated in Tracker Trigger FDL chip


CMS GT Standard Algorithm in FPGA: Example

Correlation TEMPLATE

Missing Energy TEMPLATE

Predefined VHDL code

Single particle TEMPLATE

ParametersET thresholds 1,2

window 1,2

Missing Energy threshold

Correlation

ieg1

ieg2

ieg3

ieg4

Find 2 out of 4 particles fulfilling all conditions

IEG condition: ieg2wsc

Combinatorial logic: Algorithm = ieg2wsc and MET

Missing ET condition: MET

ALGO bit (i) Final_OR

Single particle thr2,

window2Single particle thr2,



window2

Single particle thr1,




window1

ieg1

ieg4

ieg2ieg3

ieg1

ieg4

ieg2ieg3

Mask, Veto_mask

prescalers

Standard CONDITION chip

FDL chip


Condition chip with DSP array or RISCs

DSPCondition program

Trigger objects(GCT, GMT, TrackerTr…) Parameters

Condition bit

Parallel or tree structures

DSP DSP DSP

DSP

DSPDSPDSP

Trigger objects Trigger objects

Latency Latency

Algorithm logic in FDL chip Algorithm logic in FDL chip

Constraints:• # of Conditions # of DSPs• # of instructions latency limit• Keep pipeline structure

Latency = # of instructions

Hardwired logic*

*) if DSPs are implemented in FPGA

XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC,3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s)680 IO (1.25Gb/s LVDS)

Condition bitCondition bit

OR


Global Trigger board for SLHC

2 sets of opt. rcvers

RX:Serial parallel

COND_logicor

DSP array

Ethernet IPL1A_daq + Serial TX

LVDS

FDL chip

nn Algo

(and,or,

not)

FinalOR

COND chip

SYNC Chip

DAQ chip

L1A_daq + Serial TX

GCT: 5 ...GMT: 2Tracker: ~2 ..

Parallel data

LVDS

Ethernet IP

ControlCPU

ControlCPU

Ethernet IP

Ethernet IP

Trigger Counters

Pre

scal

ers

Spy_mem‘s &Ringbuffers

Spy_mem‘s &Ringbuffers

Event builder CMS - DAQ

LVDS LVDS Condition bits

Ethernet IO

Synccircuits

Condition bits

CLK, BCRES, ...

LVDSTIMINGcircuits

LVDS

CLK, BCRES, ..

Preliminary!


Trigger system design based on Telcom developments


ATCA standard


ATCA connectivity


TCA


TCA for GCT Quiet/ MIP Bits

• Data processing TCA module + custom active switching backplane

• Data processor card schematics have been designed (M. Stettler) and parts have been bought. The card is under layout at Los Alamos. Advanced PCB manufacturing techniques (e.g. micro-vias that penetrate several layers) are needed. Board stackup has been completed and verified with vendor.

• The Backplane has been designed (J. Jones + M. Stettler) but will be tested after the processor card.

• A TCA crate and a commercial backplane have been bought and are already at CERN.

• The first prototypes are expected to arrive at CERN in Summer 2008.


Main QM Data Processing Module

• Receives and transmits data via front panel optical links. • On board 72x72 Cross-Point Switch allows for dynamical routing of the data either to a V5 FPGA or directly to the uTCA backplane. • The module can exchange data with other modules either via the backplane or via the front panel optical links.


Custom TCA Backplane

• Instrumented with 144x144 cross-point switch for extra algorithm flexibility.• Allows dynamical or static routing of the data to different Data Processing Modules.


Routing detail


BACKUP


Global Trigger Crate 2008

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I/O, Hardware

DSP48E Slices :add/subtract o = Z ± (X + Y +CIN)Accumulate o = o + A&B + C //concatenateAccumulate & shiftMultiply Accumulate(MACC)MUX, BarrelShifter, Counter, multiply, divide, square_root, square_root of sum of squares,Parallel FIR Filters,…

I/O requirements:

4 calo objects(jet, ieg,..) 64 bits/40MHz 2.56 Gbps4 calo objects(jet, ieg,..) 64 bits/80MHz 5.12 Gbps1.25 Gbps LVDS IO for each pin pair: 31 bits/40MHz // 15 bits/80MHz

Virtex5XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC,3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s)680 =340 pairs IO (1.25Gb/s LVDS)

Altera Stratix III EP3SE110 : for DSP+Memory applicationsDSP: 448 18x18 Multipliers for 550 MHz clock

896 18x18 sum_of_multipliers56(88) LVDS 1.25Gb/s with serializer/deserializer (SERDES)

programmable pre-emphasis, (RapidIO, … )64(96) LVDS low speed

DSP block :300 MHz;

8 mult18x18, regs, adders, subtractors, accumulators, multiplexer, …

FPOA (..object arrays)1GHz clock256 ALU Arithmetic Logic Units 16 bit 64 MAC multiply&accumulate units 80 RF register set( 64 regs 16 bit) 2 fast serial IO links

slhc meeting cern, 21 may 2008

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