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A Technical Seminar Report on

SECURED AND EFFICIENT

DATA TRANSFER USING SPI PROTOCOL

A Technical Report submitted in partial fulfillment of the requirements to

Jawaharlal Nehru Technology University Kakinada for the award of the degree

of

Bachelor of Technology

In

ELECTRONICS AND COMMUNICATION ENGINEEIRING

Department of Electronics &Communications Engineering

Vasireddy Venkatadri Institute of Technology,

(Affiliated to JNTUK)

Nambur,

GUNTUR-5225089,Andhra Pradesh,INDIA[2009-2013]

Project Members Guided By:

R.Naveen Kumar

V.Yaswanth Kumar Prof.M.Yaswanth Bhanumurthy

K.H.C.V.Prasad

S.Akash



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CONTENTS

1. SD CARD INITIALIZATION

2. MULTIPLE BLOCK READ

3. MULTIPLE BLOCK WRITE

4. SPI INITIALIZATION

5. SSPSTAT REGISTER CONFIGURATION

6. SSPCON1 REGISTER CONFIGURATION

7. PORTC CONFIGURATION

8. USART REGISTER CONFIGURATION

9. PROGRAM TESTING AND VERIFICATION

10. CONCLUSION



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1. SD CARD INITIALIZATION

When an SD card is powered ON, we need to initialize the SD card and bring it to SPI mode.

This requires a series of commands and need to check the response whether it is correct or

not for the particular command.

Whenever the active low signal is given to chip select pin of SD card after few clock Cycles

the command (CMD0) is passed to CMD pin of SD card and wait for response. Here we have

three types of response format are available in that R1 response is Acknowledged by SD card

by receiving the initializing command and the response is Passed to the DATA OUT pin of

SD card

Every command was send in the form of packet and even if data also send to the SD card In

the packet format given below as we are using SPI protocol by default CRC is Disabled and

data received by SD card will be checked by the valid response given by Memory card as it is

known as data response .After sending the data we continuously Check at the DATA OUT

pin of SD card for the response. As if data is reached Successfully to SD card then it returns

the value zero so that we can send the next packet Of data else we have to retransmitted the

data to SD card .the value one indicates the Error While writing the data and at that condition

we have to send the data again to SD Card .To Check the data as it reached without any error

CRC check is used as it is little Bit Complicated to generate the polynomial and check sum

because of hardware Limitations we followed another approach which is level converter

which enhances the Voltage of Transmitting bit which is sending to destination memory card

.this solves the problem of loss of data while Transmitting



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2. MULTIPLE BLOCK READ

The Multiple Block Read command reads multiple blocks in sequence from the specified

Address. When number of transfer blocks has not been specified before this command, The

Transaction will be initiated as an open-ended multiple blocks read, the read Operation will

continue until stopped with a CMD12.

The received byte immediately Following CMD12 is a stuff byte; it should be discarded

before receiving the response of The CMD12. Before every data packet, a data token (FEh) is

sent by the card. If the data Token is not received, then it waits for the token.

For Single block Read The argument specifies the location to start to read in unit of byte or

block. The sector address specified by upper layer must be scaled properly. When a CMD17

is accepted, a read operation is initiated and the read data block will be sent to the host.

After a valid data token (FEh) is detected, the host controller receives following data field

and two byte CRC. The CRC bytes must be flushed even if it is not needed. If any error

occurred during the read operation, an error token will be returned instead of data packet

Every SD Memory Card token transferred on the bus is protected by CRC bits. In SPI Mode,

the SD Memory Card offers a non-protected mode which enables systems built with reliable

data links to exclude the hardware or firmware required for implementing The CRC

generation and verification functions in the non-protected mode the CRC bits of the

command, response and data tokens are still required in the tokens. However, they are

defined as ‘don’t care’ for the transmitter and ignored by the receiver. The SPI interface is

initialized in the non-protected mode. The host can turn this option on and off using

CRC_ON_OFF command (CMD5).



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3.MULTIPLE BLOCK WRITE

The Multiple Block Read command writes multiple blocks in sequence from the specifiedAddress. When number of transfer blocks has not been specified prior to this command The

transaction will be initiated as an open-ended multiple block write, the write Operation will

continue until it is terminated with a Stop Tran token (FDh). The busy flag will appear on the

DO line a byte after the Stop Tran token. As for SDC, the multiple Block write transaction

must be terminated with a Stop Tran token independent of the Transfer type, pre-defined or

open-ended.

When a write command is accepted, the host controller sends a data packet to the card after a

byte space. The packet format is same as Block Read command. The CRC field can have any

invalid value unless the CRC function is enabled. When a data packet has been sent, the card

responds a Data Response immediately following the data packet the data response trails a

busy flag to process the write operation.

Most cards cannot Change write block size and it is fixed to 512 bytes. Before every data

packets a data Token is written so that the MMC/SD could confirm that the next 512 bytes

received after the write token (FEh) is the data block to be stored in the SD/MMC.

In principle of the SPI mode, the CS signal must be asserted during a transaction however

there is an exception to this rule. When the card is busy, the host controller can be asserts CS

to release SPI bus for any other SPI devices. The card will drive DO signal Low again when

reselect it during internal process is in progress.

Therefore a preceding busy check (wait ready immediately before command and data packet)

instead of post Wait can eliminate waste wait time. In addition the internal process is initiated

a byte after the data response, this means eight clocks are required to initiate internal write

Operation.



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4.SPI INITIALIZATION

Operation:

When initializing the SPI, several options need to be specified. This is done by programming

the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (IDLE state of SCK)

• Data input sample phase (middle or end of data output time)• Clock edge (output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register

(SSPBUF). The SSPSR shifts the data in and out of the device, MSB first. The SSPBUF

holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits

of data have been received, that byte is moved to the SSPBUF register. Then the buffer full

detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double

buffering of the received data (SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data will be ignored, and the write

collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register

completed successfully. When the application software is expecting to receive valid data, the

SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF.

Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the

received data (transmission is complete).



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When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is

only a transmitter. Generally, the MSSP Interrupt is used to determine when the

transmission/reception has completed. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software polling can be done to ensure that a

write collision does not occur. SSPBUF (SSPSR) for data transmission. The SSPSR is not

directly readable or writable, and can only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions.

Enabling SPI I/O:

To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or

reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set

the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the

pins to behave as the serial port function, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit cleared

• SCK (Slave mode) must have TRISC<3> bit set

•SS must have TRISC<4> bit set

Any serial port function that is not desired may be overridden by programming the

corresponding data direction (TRIS) register to the opposite value.



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5. SSPSTAT REGISTER CONFIGURATION

SMP=1

CKE=1

These two bits are configured in order to read and write the data



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6. SSPCON1 REGISTER CONFIGURATION

SSPEN=1 (Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

Which are connected to SD card)

The last four bits are configured as 0010 to enable SPI module in MASTER Mode



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7. PORTC CONFIGURATION

TRISC=1 (Configure the PORTC as I/O Port)

RC0=RC3=RC5=0 (Configure the RC0 and RC1 as Output)RC7=1 & RC6=0 (For UART transmission RC7 as input and RC6 as Output)

8. USART REGISTER CONFIGURATION

In this mode, the USART uses standard non-return-to- zero (NRZ) format (one START bit,

eight or nine data bits and one STOP bit). The most common data format is 8-bits. An on-

chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies

from the oscillator.

The USART transmits and receives the LSb fir st. The USART’s transmitter and receiver are

functionally independent, but use the same data format and baud rate. The baud rate generator

produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH

(TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software

(and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>).

The USART Asynchronous module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit• Asynchronous Transmitter

• Asynchronous Receiver



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We configured as:

SYNC=0

BRGH=1

TRMPT=1



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RCSTA (Receiver Status And Control Register)

We Configured as:

SPEN=1

CREN=1



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USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in Figure. The heart of the transmitter is the

Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write

transmit buffer, TXREG. The TXREG register is loaded with data in software.

The TSR register is not loaded until the STOP bit has been transmitted from the

previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from

the TXREG register (if available). Once the TXREG register transfers the data to the TSR

register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is

set.

This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>).Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into the TXREG register.

While flag bit TXIF indicated the status of the TXREG register, another bit, TRMT

(TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read only bit, which

is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to

poll this bit in order to determine if the TSR register is empty.

To set up an asynchronous transmission:

1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is

desired, set bit BRGH

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit.

5. Enable the transmission by setting bit TXEN, which will also set bit TXIF.

6. If 9-bit transmission is selected; the ninth bit should be loaded in bit TX9D.

7. Load data to the TXREG register (starts transmission).



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USART Asynchronous Receiver

The receiver block diagram is shown in Figure The data is received on the RC7/RX/DT pin

and drives the data recovery block. The data recovery block is actually a high speed shifter

operating at x16 times the baud rate; whereas the main receive serial shifter operates at the bit

rate or at FOSC. This mode would typically be used in RS-232systems. To set up an

Asynchronous Reception:

1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is

desired, set bit BRGH

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if

enable bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error

occurred during reception.

8. Read the 8-bit received data by reading the RCREG register.

9. If any error occurred, clear the error by clearing enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register

(INTCON<7:6>) are set.



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9. PROGRAM TESTING & VERIFICATION

Memory Card Successfully Initialized. The response from SD card will take several thousand

micro seconds so we have to send the initialization command more than one time to confirm

the SD card is successfully initialized.

Reading the data from each sector of SD card is successfully received by pic controller and

at the same time another pic controller is able write the data into another SD card is verified

by winhex software

We configured the registers in pic controller as we mentioned it above and successfully

executed single block read and write program.

10. CONCLUSION

Furthermore we have to test the same procedure to transfer the entire sectors to another SD

card so, that data will transfer.

Up to now we completed 80% of the project.

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