progress 1st sem

Power management in DC -Grid

Presented by-

Satabdy Jena

PhD (Power Electronics)

Reg. No. 2017EEZ8158

Indian Institute of Technology Delhi

SEMESTER PROGRESS PRESENTATION

Under the supervision of

Prof. M. Veerachary

Professor, Indian Institute of Technology

Delhi

Contents

1. Courses

2. Introduction

3. Converter topologies

4. Conclusion and future scope

5. Bibliography

12/26/2017 2

1. Courses outline

12/26/2017 3

Coursework Credits Obtained

GPA

1. Power Electronic Converters

(ELL751)

3

2. Non Linear Systems

(ELL702)

3

• High efficiency, high reliability and ease of interconnection of renewable

• Telecom, automotive, portable power, power supply for WAN/LAN,

vehicular and distributed power systems

• In order to achieve safe and reliable MG performance, its dynamic stability

needs to be ensured in all operating conditions.

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2. introduction

3. CONVERTER analysis

• State space averaging

Where,

12/26/2017 5

.

g

g

x Ax Bv

y Ex Fv

1 1 2 2* *A A D A D

1 1 2 2* *B B D B D

1 1 2 2* *E E D E D

1 1 2 2* *F F D F D

2 1(1 )D D

(1)

• Small signal analysis

• Assuming that deviations are sufficiently small that the

non-linear and second order terms can be neglected, it

results in a small-signal linear model

12/26/2017 6

g g g

x X x

v V v

g zx Ax Bv mi Pd

1 2 1 2 1 2( ) ( ) ( )g zP A A X B B V M M I

1( )x

sI A Pd

(2)

(3)

(4)

(5)

12/26/2017 7

g zy Ex Fv Ki Qd

1 2 1 2 1 2( ) ( ) ( )g zQ E E X F F V K K I

4. Converter topologies

• KY Boost Converter

• Sepic and Cuk Converter

• Cascade 2 stage (with and without undamped input filter)

Converter

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(i) KY-Boost Converter

Fig. 1. KY-Boost converter

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Fig. 2. Mode-1 operation

Fig.3. Mode-2 operation

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c1

1 c1 c2 1 c1 c2 1 c1 c2 1

c1

2 c1 c2 2 c1 c2 2 c1 c2

3 c3 3

1

1

2

c1 c1 c1

2 2 c1 c2 2 c1 c2 2 c3 c1 c2 2

r-1 1 10 0

(C (r +r )) (C (r +r )) (C (r +r )) C

-r1 -10 0

(C (r +r )) (C (r +r )) (C (r +r ))

-1 10 0 0A1=

(C *(R+r )) C

-r0 0 0 0

L

r r (r )1 -R0

L (L (r +r )) (L (r +r )) (L (R+r )) ((r +r )L )

c12

2 2

rr

L L

T1

B1= 0 0 0 0L1

c3

RE1 0 0 0 0

(R+r )

F1 0

State Matrices

(7)

(8) (9)

(10)

12/26/2017 12

1 1

2

3 c3 3

c1 1 c1

1 1 1

c1 c2 2 c1

2 2 2 c3 2 2

1 -10 0 0

C C

-10 0 0 0

C

-1 10 0 0A2=

(C (R+r )) C

-(r +r ) r-10 0

L L L

r (r +r +r )1 1 -R0

L L (L (R+r )) L L

T1

B2= 0 0 0 0L1

c3

RE2 0 0 0 0

(R+r )

F2 0

State Matrices

(11)

(12)

(13)

(14)

12/26/2017 13

Parameters Values Parameters Values

rc1 0.1 Ω r1 0.01Ω

rc2 0.1 Ω r2 0.01Ω

rc3 0.1 Ω R 20Ω

C1 1000 µF L1 15 µH

C2 680 µF L2 15 µH

C3 470 µF D1 0.5

Vg 12 V fsw 195 kHz

Voltages and

currents

Values in Matlab Values in PSIM

Vc1 23.54 V 23.19 V

Vc2 23.02 V 23.19 V

Vc3 35.12 V 34.94 V

iL1 5.2427 A 5.24 A

iL2 1.7476 A 1.74 A

Table I. Values of state parameters

Table II. Voltages and currents in the steady state

12/26/2017 14

Fig.5. Step response of Gvo_d

The pole-zero map of the converter output voltage to duty transfer function

depicts a pole as shown in Fig.4 due to which there is inversion of response in

the step response shown in Fig.5

Fig. 4. Pole-zero map of Gvo_d

12/26/2017 15

Fig.6. Frequency response of iL1 to duty

4 3 2

5 4 3 2iL1_d

2.281 5 1.07 10 5.412 13 1.176 18 2.392 20

4.847 04 3.667 08 6.935G =

12 8.898 15 2.62 19

e s e s e s e s e

s e s e s e s e s e

0

-10

10

20

30

40

50

amp(il1_fr)

1 10 100 1000 10000 100000

Frequency (Hz)

0

-50

-100

-150

-200

50

100

phase(il1_fr)

(15)

12/26/2017 16

Fig.7. Frequency response of IL2 to duty

4 3 2

5 4 3 2iL2_d

1.695 05 7.511 09 5.405 12 2.458 17 4.912 19

4.847 04 3.667 08 6.935 12 8.898 15 2.62 1G

9=

e s e s e s e s e

s e s e s e s e s e

0

-10

10

20

30

40

amp(il2_fr)

10 1000 100000

Frequency (Hz)

0

-100

-200

-300

100

phase(il2_fr)

12/26/2017 17

Fig.9. Frequency response of VC1 to duty

4 3 2

5 4 3 2VC1_d

2942 1.006 08 1.49 13 8.708 15 2.468 20

4.847 04 3.667 08 6.935 12 8.8G

98 15 2.62 19

s e s e s e s e

s e s e s e s e s e

0

-10

-20

10

20

30

amp(Vc1_fr)

1 10 100 1000 10000 100000

Frequency (Hz)

0

-50

-100

-150

-200

-250

phase(Vc1_fr)

(16)

12/26/2017 18


4 3 2

5 4 3 2VC2_d

2942 1.006 08 1.49 13 8.708 15 2.468 20

4.847 04 3.667 08 6.93G =

5 12 8.898 15 2.62 19

s e s e s e s e

s e s e s e s e s e

0

-10

-20

-30

10

20

30

amp(Vc2_fr)

1 10 100 1000 10000 100000

Frequency (Hz)

0

-50

-100

-150

-200

50

phase(Vc2_fr)

(17)

12/26/2017 19


3 2

5 43 d 3 2VC _

1.688 08 7.448 12 3.9 15 2.456 20

4.847 04 3.667 08 6.935 12 8.898 15 2.62G =

19

e s e s e s e

s e s e s e s e s e

0

-10

10

20

30

40

amp(il2_fr)

1 10 100 1000 10000 100000

Frequency (Hz)

0

-100

-200

-300

100

phase(il2_fr)

(18)

12/26/2017 20

Vg

r1, L1

S1

rc1, C1

D1

r2, L2

rc2, C

2

RVo

Fig. 11. Cuk converter

(Ii) Sepic and Cuk converter

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Fig.12. Circuit diagram for mode-1 operation


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1

1

2 c1

2 2 2

1

2 c2 2

-r0 0 0

L

-(a+r +r ) -1 -b0

L L LA1

10 0 0

C

b -10 0

C ((R+r )C )

T

1

1B1 0 0 0

L

E1 0 -a 0 -b

F1=[0]

State Matrices

(19)

(20)

(21)

(22)

12/26/2017 23

1 c1

1 1

2

2 2

1

2 c2 2

-(r +r ) 10 0

L L

-(a+r ) -b0 0

L L[A2]

10 0 0

C

b -10 0

C ((R+r )C )

T

1

1[B2]=[ 0 0 0]

L

[E2]=[0 -a 0 -b]

[F2]=[0]

c2

c2

(R.r )a=

(R+r )

c2

Rb=

(R+r )

State Matrices

(23)

(24)

(25)

(26)

12/26/2017 24

Fig.14. Circuit diagram for SEPIC converter

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12/26/2017 26

1

1

2 c1

2 2

1

c2 2

-r0 0 0

L

-(r +r ) 10 0

L L[A1]

10 0 0

C

-10 0 0

((R+r )C )

T

1

1[B1]=[ 0 0 0]

L

c2

R[E1]=[0 0 0 ]

(R+r )

[F1]=[0]

State Matrices

(27)

(28)

(29)

(30)

12/26/2017 27

1 c2 c1 c2

1 1 1

2 c1

2 2

1

c2 2

-(r +a.r +r ) -(a.r ) -10

L L L

-(r +r ) 10 0

L L[A2]

10 0 0

C

-10 0 0

((R+r )C )

1

1[B2]=[ 0 0 0]

L

c2 c2[E2]=[a.r a.r 0 (1-b)]

[F2]=[0]

State Matrices

(31)

(32)

(33)

(34)

12/26/2017 28


rc1 0.1 Ω r1 0.01Ω

rc2 0.1 Ω r2 0.01Ω

C1 1000 µF R 20Ω

C2 680 µF L1 15 µH

Vg 12 V L2 15 µH

fsw 195 kHz D1 0.5

Voltages and

currents

Values in Matlab

(SEPIC/CUK)

Values in PSIM

(SEPIC/CUK)

Vc1 11.865/45.43 V 11.58/45.6977 V

Vc2 33.7406/-33.86 V 33.7406/-34.88 V

iL1 2.5305/2.62 A 2.6163/2.4316 A

iL2 0.8435/-0.808 A 0.7675/-0.8721 A

Table IV.Voltages and currents in the steady state

Table III. Values of state parameters

12/26/2017 29

12/26/2017 30

12/26/2017 31

Fig.17. Steady state comparison for cuk and sepic

12/26/2017 32

Fig.18. Frequency response analysis of iL1 to duty

3 2

4iL1 d 2c_ 3

2.339 05 7.702 08 2.045 13 6.085 15

4007 8.324 07G =

1.1 11 2.336 14

e s e s e s e

s s e s e s e

4 3 2

4 3_d 2IL1S

0.4186 2.324 05 5.571 08 1.275 13 5.922 15

3635 5.515 07 1.008 11 2.3 7 14G

4

s e s e s e s e

s s e s e s e

-40

-20

0

20

40

60

Mag

nit

ud

e (

dB

)

10-3

10-2

10-1

100

101

102

103

104

-180

-135

-90

-45

0

45

90

Ph

ase (

deg

)

Bode Diagram

Frequency (kHz)

GIL1c_d

GIL1s_d

GIL1c_d

GIL1s_d

(35)

(36)

12/26/2017 33

Fig.19. Frequency response analysis of iL2 to duty

3 2

4 3i _d 2L2c

1.514 05 2.381 07 3.915 12 9.724 14

4007 8.324 07 1.1 11 2.336 1G =

4

e s e s e s e

s s e s e s e

4 3 2

4 3_d 2IL2S

0.4186 1.499 05 2.716 07 3.802 12 8.524 14

3635 5.515 07 1.008 11 2.3 7 14G

4

s e s e s e s e

s s e s e s e

-40

-20

0

20

40

Mag

nit

ud

e (

dB

)

10-3

10-2

10-1

100

101

102

103

-720

-540

-360

-180

0

180

Ph

ase (

deg

)

Bode Diagram

Frequency (kHz)

GIL2c_d

GIL2s_d

GIL2c_d

GIL2s_d

(37)

(38)

12/26/2017 34

Fig. 20. Frequency response analysis of GVC1 to duty

3 2

4 3V _d 2C1c

7.212 04 1.461 09 2.287 12 3.836 16

4007 8.324 07 1.1 11 2.336 1G =

4

e s e s e s e

s s e s e s e

4 3 2

4 3_d 2VC1s

0.4186 7.331 04 1.457 09 1.717 12 6.305 14

3635 5.515 07 1.008 11 2.3 7 14G

4

s e s e s e s e

s s e s e s e

-40

-20

0

20

40

60

Mag

nit

ud

e (

dB

)

10-3

10-2

10-1

100

101

102

103

-360

-270

-180

-90

0

Ph

ase (

deg

)

Bode Diagram

Frequency (kHz)

GVC1c_d

GVC1s_d

GVC1c_d

GVC1s_d

(39)

(40)

12/26/2017 35

Fig.21 Frequency response analysis of GVC2 to duty

2

4 3VC c d 22 _

1.503 09 1.365 11 3.89 16

4007 8.324 07 1.1 11 2.33G =

6 14

e s e s e

s s e s e s e

4 3 2

4 3_d 2VC2S

0.4186 3.501 04 8.198 08 5.341 11 3.793 16

3635 5.515 07 1.008 11 2.3 7 14G

4

s e s e s e s e

s s e s e s e

-100

-50

0

50

Mag

nit

ud

e (

dB

)

10-2

10-1

100

101

102

103

-720

-540

-360

-180

0

Ph

ase (

deg

)

Bode Diagram

Frequency (kHz)

GVC2c_d

GVC2s_d

GVC2c_d

GVC2s_d

(41)

(42)

12/26/2017 36

-6 -5 -4 -3 -2 -1 0 1 2 3 4

x 104

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1x 10

4 Pole-Zero Map

Real Axis (seconds-1)

Imag

inar

y A

xis

(sec

on

ds

-1)

Fig.22. Pole-zero map of Sepic and Cuk

(iii) Cascade 2 stage converter

12/26/2017 37

Fig.24. Cascade 2 stage buck converter

Fig.25. Cascade 2 stage buck converter with input filter

Design and Effect of Input Filter on DC/DC Converter

Requirement of input filter:

• High frequency switching of DC/DC Converters leads to input source voltage

ripple and reflected input current ripple.

Design difference between input and EMI filter:

• Mismatch between source and input impedance of filter and mismatch between

load and out impedance of filter to ensure strong reflection rate are considered

in EMI filter design but not in input filter.

• EMI filter design targets to a frequency upto 30 MHz for conduction emission

+ radiated EMI. (noise from DC-DC converter are of two types: radiated and

conducted. EMI < 30 MHz--conduction noise and higher frequencies--radiation

noise) Input filter focuses on a much narrower range of emission only.

12/26/2017 38

• EMI filter's performance is highly related to parasitic parameters.

• Input filter's performance is much less affected by parameter parasitics.

• EMI filter considers both differential and common mode noise.

• Input filter only considers differential mode noise.

• (Differential mode emissions include the basic switching current

waveform and harmonics as well as periodic spikes arising due to

switching frequency. Common mode emissions consist of periodic current

spikes through chassis ground caused by rapidly switched voltage across

parasitic capacitance.)

12/26/2017 39

Self-resonant frequency:

• Every capacitor or inductor can be practically shown as a RLC circuit

combination, and hence they have a self resonant frequency beyond which

inductors behave as capacitors whereas capacitors behave as inductances.

RHS Zero Pair:

• RHS Zero pair occurs due to cascading of converters.

• Addition of input filter leads to addition of RHS zero pair.

Problem:

• The RHS zero pairs are the cause of instability in the closed loop and can

cause oscillations in the DC Circuit.

12/26/2017 40

Reason:

1. As input voltage increases, the PWM control circuitry cuts back the duty

cycle of the controlled switch to maintain constant output voltage. This

causes the averaged input current to decrease. Since the average input

current decreases in response to increase in voltage, the converter behaves

as a negative dynamic resistance.

2. Deriving the characteristic polynomial of the converter, there is a negative

term which causes an unbounded unstable system.

3. Thus addition of a lightly damped or un-damped input filter to the negative

resistance model causes to form a negative oscillator circuit. This explains

why addition of input filter causes instability.

12/26/2017 41

Solution:

• Damping can solve the problem. However internal circuit losses are not

sufficient to damp the oscillations. And hence external damping needs to

be included.

• Resistance should not be included in the input filter as it would lead to

increase in resistive losses.

• Design procedure is to include a DC blocking capacitor branch with

appropriate damping resistor whose capacitance is chosen very large as

compared to input filter capacitance. This enables less current to flow

through the branch and hence less resistive losses.

• This aids in bringing RHP zeroes to LHP by proper damping.

12/26/2017 42

Exceptions:

• DC/DC Converters have however been successfully implemented using

simple LC input filters due to the following reasons:

1. The LC input filter components may include sufficient parasitic resistance.

2. The resonant frequency of the input filter is above the converter gain-

bandwidth.

3. The gain-bandwidth of the converter may be relatively low than the

converter switching frequency.

• Hence the region of negative resistance is below input filter resonant

frequency.

12/26/2017 43

Margin for stability:

• The output impedance of filter = Input impedance of converter.

• (Higher ratio of ; higher is the stability)

Stability Analysis:

• The converter is modelled by averaging and then this averaged model is

used for stability analysis.

• But the model becomes inaccurate in high frequency since averaging

models reach their limitation once the frequency is above the half of the

switching frequency.

• Routh-Hurwitz criterion can be used to check the stability of the complete

system (converter and input filter) .

12/26/2017 44

Input impedance of converter

Output impedance of input filter

12/26/2017 45

CASCADE 2 STAGE (WITHOUT INPUT FILTER)

Fig.27. Cascade buck two stage Mode 2

Fig.26. Cascade buck two stage Mode-1

Mode-1 Operation (S1,S2-ON, D1,D2-OFF)

Mode-2 Operation (S1,S2-OFF, D1,D2-ON)

12/26/2017 46

1 c1 c1

1 1 1

c1 2 2 c2 c2

2 2 2 2

1 1

1 2

-(r +r ) r 10

L L L

r (r +r +b.r ) b.r1 1( 1)

L L L L R

1 -10 0[A1]=

C C

b b0 0

R.CC

T

1

1[B1]=[ 0 0 0 ]

L

[E1]=[0 a 0 b]

[F1]=0

(43)

(44)

(45)

(46)

12/26/2017 47

1 c1 c1

1 1 1

2

2 2

1

2 2

-(r +r ) r -10

L L L

-(r +a) -b0 0

L L[A2]=

10 0 0

C

b -b0 0

C (RC )

T[B2]=[0 0 0 0]

[E2]=[0 a 0 b]

[F2]=0

(47)

(48)

(49)

(50)

12/26/2017 48

CASCADE TWO STAGE (WITH UNDAMPED INPUT FILTER)

Vg

r1, L1 r3, L3

rc1 , C

1

rc3 , C

3

R

r2, L2

rc2 , C

2

+ +

++

+

+

+-

-- -

- --

ic1 ic2 ic3

i1 i2 i3

io

Vg

r1, L1 r3, L3

rc1 , C

1

rc3 , C

3

R

r2, L2

rc2 , C

2

+ +

++

+

+

+

-

-- -

- --

ic1 ic2 ic3

i1 i2 i3

io

Vo

Mode-1 Operation (S1,S2-ON, D1,D2-OFF)

Fig.28. Cascade buck two stage with input filter MODE-1

Mode-2 Operation (S1,S2-OFF, D1,D2-ON)

Fig.29. Cascade buck two stage with input filter MODE-2

12/26/2017 49


rc1 0 Ω r1 0.5 Ω

rc2 0 Ω r2 0.75 Ω

rc3 0 Ω r3 0.75 Ω

C1 1 µF L1 15 µH

C2 1 µF L2 15 µH

C3 1 µF D1 0.5

Vg 48 V R 33 Ω

Table V. Values of parameters used

12/26/2017 50

-16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 0 2000 4000-1.5

-1

-0.5

0

0.5

1

1.5x 10

5

0.0120.0240.0380.0540.080.115

0.18

0.35

0.0120.0240.0380.0540.080.115

0.18

0.35

5

10

15

20

5

10

15

20

Pole-Zero Map

Real Axis (seconds-1)

Im

ag

in

ary A

xis (seco

nd

s-1)

WITH UNDAMPED INPUT FILTER

WITHOUT FILTER

Fig.30. Pole-zero plot of cascade converter with and without input filter

RHP Complex Conjugate zero pairs

12/26/2017 51

-50

0

50

Mag

nitu

de (d

B)

10-1

100

101

102

103

-900

-720

-540

-360

-180

0

Ph

ase (d

eg

)

Bode Diagram

Frequency (kHz)

WITHOUT UNDAMPED INPUT FILTER

WITHOUT INPUT FILTER

Fig.31. Frequency response of the cascade two stage converter with and without input filter

Converter-1 dynamics

Converter-2 dynamics

Input filter

Glitch due to RHP complex conjugate zero pairs

• Method for steady state analysis and small-signal analysis.

• The effect of input filter interactions with the converter rendering

instability was shown with the help of frequency response.

• Further analysis has to be done on the effect of damping employed to

the filter in order to shift the RHP poles.

12/26/2017 52

Conclusion

Bibliography

• [1] M.Usman Iftikhar, A. Bilal, D.Sadarnac, P. Lefranc and C. Karimi, "Analysis of

Input filter interactions in cascade buck converters", in proceedings of IEEE

International Conference on Industrial Technology, 2008. ICIT 2008.

• [2] Xiaoyan Yu, and Maurizio Salato, " An optimum minimum component DC-DC

converter input filter design and its stability analysis", IEEE Transactions on Power

Electronics, 29(2), pp.829-840,2014.

• [3] Filter Network Design for VI Chip® DC-DC Converter Modules

• [4] Daniel M Mitchell, "Power line filter design considerations for DC-DC

converters", IEEE Industry Applications Magazine,pp.16-26,1999.

• [5] Slobodan Cuk, 'Modelling, analysis, and design of switching converters',

California Institute of Technology,1977.

12/26/2017 53

Thank you for your patienceSuggestions please

12/26/2017 54

progress 1st sem

Engineering