1st sem report

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belgaum - 580 014

AProject Report

on Differential Amplifier with Buffer Configuration

Submitted in Partial Fulfillment for the award of the Degree

Master of Technologyin

VLSI Design and Testing

Submitted By

Mr.Abhishek C Math(USN:2BV13LDT02)

Under the guidance of

Dr.Rajshekar.B.Shettar

B. V. BHOOMARADDI COLLEGE OFENGINEERING AND TECHNOLOGY HUBLI-31

2013-2014

B.V.BHOOMARADDI COLLEGE OF


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ENGINEERING AND TECHNOLOGY HUBLI-31

CERTIFICATE

This is to certify that the Project report entitled Differential Am-

plifier with Buffer Configuration is a bonafide work carried out byMr. Abhishek C Mathi bearing (USN: 2BV13LDT02) as a partof VISVESVARAYA TECHNOLOGICAL UNIVERSITYS M.Tech in VLSI

Design and Testing at B. V. Bhoomaraddi College of Engineering and Tech-

nology, Vidyanagar, Hubli for the academic year 2013-2014.

Dr.Rajshekar.B.Shettar Dr.Uma Mudenagudi Dr.Ashok ShettarGuide Head of the Department Principal

External VivaName of Examiners Signature with date

1) ..................

2)..................

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ABSTRACT

In this paper we present a design of a cmos amplifier with the bufferconfiguration which operates at 1.8V power supply. Here we are making todesign the op amp as a buffer which drives a 2pf capacitive load. The pro-posed design produces an open loop gain of 50dB and Unity Gain Bandwidthof 10MHz in UMC 0.18micron technology. The op amp designed is a singlestage differential amplifier. The differential amplifier plays an excellent per-formance as input amplifier and application with the possibility of feedbackto the input. The differential amplifier circuit is characterised in terms of

self bias capability, common mode rejection, voltage gain and the unity gainbandwidth product.


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ACKNOWLEDGMENTS

The sense of contentment and elation that accompanies the successfulcompletion of our project and its report would be incomplete without men-tioning the names of the people who helped us in accomplishing this.

We take this opportunity to thank our principal Dr. Ashok Shettar, forproviding healthy environment in the college, which helped in concentratingon the task. We express a deep sense of gratitude to our H. O. D. Dr. UmaMudenagudi for providing the inspiration required for taking the project toits completion.

We sincerely thank to our guide Dr.Rajshekar.B.Shettar for their in-spiring guidance and promising support they gave during the course of com-pletion.

We sincerely thank to our project coordinator Dr.Saroja Sidmal,forgreat support and encouragement

Last but not the least we like to thank all the staff members, teachingand non - teaching staff for helping us during the course of the project.

Mr.Abhishek C Math


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Contents

1 Introduction 1

1.1 Buffer Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Why is this circuit useful? . . . . . . . . . . . . . . . . . . . . 21.3 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Objective of the Project . . . . . . . . . . . . . . . . . . . . . 31.5 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6 Organization of the report . . . . . . . . . . . . . . . . . . . . 4

2 Literature Survey 5

2.1 Simple Differential Amplifier . . . . . . . . . . . . . . . . . . . 52.2 Telescopic cascode op amps . . . . . . . . . . . . . . . . . . . 5

3 Design of Differential Amplifier 8

3.1 differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . 83.2 Large signal analysis of differential amplifier . . . . . . . . . . 93.3 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . 113.4 Frequency Response of Fifferential Amplifier . . . . . . . . . . 12

4 Simulation and Results 16

4.1 EVALUATION OF DEVICE . . . . . . . . . . . . . . . . . . 164.2 PVT Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.3 Schematic of Differential Amplifier . . . . . . . . . . . . . . . 184.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Conclusion 22

5.1 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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List of Figures

1.1 Buffer Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Telescopic cascode op amps . . . . . . . . . . . . . . . . . . . 72.3 cascode op amp with input and output shorted . . . . . . . . 7

3.1 Single-ended output differential amplifier in dc state. . . . . . 93.2 Variations of differential amplifier drain currents versus input. 103.3 Variations of differential amplifier drain currents versus input. 113.4 5 pack differential amplifier . . . . . . . . . . . . . . . . . . . 113.5 Differential amplifier with two main capacitances impacting

on frequency response . . . . . . . . . . . . . . . . . . . . . . 143.6 High-frequency small-signal equivalent circuit for differential

amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2 AC response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 Amplifier in the Buffer Configuration . . . . . . . . . . . . . . 21

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List of Tables

3.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Evaluation of NMOS Device . . . . . . . . . . . . . . . . . . . 16

4.2 Evaluation of PMOS Device . . . . . . . . . . . . . . . . . . . 174.3 Device Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.4 PVT Analysis for 1.8V . . . . . . . . . . . . . . . . . . . . . . 174.5 PVT Analysis for 1.62V . . . . . . . . . . . . . . . . . . . . . 184.6 PVT Analysis for 1.92V . . . . . . . . . . . . . . . . . . . . . 184.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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Chapter 1

Introduction

CMOS Op amp is one of the most versatile and important building blocksin analog circuit design. Based upon the value of their output resistance theyare being classified into two categories

1. UNBUFFERED OPERATIONAL AMPLIFIER: These are Opera-tional Transconductance Amplifiers (OTA), which have high output resis-tance.

2. BUFFERED OPERATIONAL AMLIFIER: These are Voltage Oper-ational Amplifiers, which have low output resistance. Operational amplifiersare amplifiers (controlled sources) that have sufficiently high forward gainso that when negative feedback is applied, the Closed-loop transfer function

is practically independent of the gain of the opamp. The primary require-ment of an op-amp is to have an open loop gain that is sufficiently large toimplement negative feed back concept.

1.1 Buffer Amplifier

A buffer amplifier, or simply a buffer, is an electronic amplifier thatis designed to have an amplifier gain of 1. Buffers are used in Impedancematching, the benefit of which is to maximize energy transfer between circuitsor systems. The below fig1 shows the diagram of a voltage buffer. There are

two main kinds of buffer circuits, Voltage buffers and Current buffers. Thepurposes of each is to isolate the mentioned characteristic to avoid loading theinput circuit or source from the output stage. Another name by which bufferamplifiers are known as is a voltage follower. The name is given because of

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Differential Amplifier with Buffer configuration

Figure 1.1: Buffer Amplifier

the characteristic of the amplifier to output a signal of the same amplitudeas the input (given the unity gain [gain of 1 or 0dB] ). If the differencebetweenV+ and V is negligibly small so thatV+ = V we must have:

Vout= Vin (1.1)

A buffer amplifier is used to isolate the oscillator from the following circuits,impedance matching, and extra tuned circuits to clean up the signal. Butgain is usually less than one. With a buffer amp, you get a cleaner more stablesignal of the proper impedance for the next circuits and they cant effect theoscillator. If the load on the oscillator varies it will cause frequency andamplitude instability. This is what the buffer amp is used to avoid. A bufferamp has a very high input impedance so it doesnt load up the oscillator.And it has the right output impedance to satisfy the following circuit

1.2 Why is this circuit useful?

There are many situations where you do not want to draw current from acircuit (i.e. load the circuit). Some of those situations are: oA bridge

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31. 2


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circuit or a voltage divider circuit - maybe where there is a resistive sensorin the bridge or voltage divider - and drawing current when you measurethe voltage would be enough to change the voltage. oA rectifier/filter wherethe output is across a capacitor. In that situation drawing current from thecapacitor will discharge the capacitor, reducing the voltage.

1.3 Problem Statement

The amplifier block is to be designed to meet the defined specification ofbuffered amplifier. Buffered amplifier which provides the high input impedance

to low output impedance. The design is to be implemented using UMC180nm technology for a gain factor of 1. Tool: Cadence (Virtuoso Schematicand Layout Editor, Spectre and Assura DRC, LVS).

1.4 Objective of the Project

To design the buffer configuration in differential amplifier for open loop gainof 50db and UGB=10MHz and evaluate the performance parameter .Thelayout of the amplifier is build.To understand the characteristics and appli-cations of the buffer amplifier. The main characteristics under consideration

are high gain, high PSRR, high output swing and UGB. Performance of anycircuit depends upon these characteristics. At reduced supply voltages, out-put swing becomes an important parameter. At large supply voltages, thereis a trade off among speed, power and gain.

1.5 Methodology

Literature survey of the amplifier architectures is carried out after goingthrough various papers. All the devices used in the design were character-ized and the required parameters like threshold voltage Vth,VDS and VGS

of a transistor were extracted. After under-standing the working of am-plifier, basic circuits were simulated with ideal conditions and specifications.Later with these specifications, the circuits are designed in Cadence Virtuososchematic editor and simulated using ADE tool. The schematic and sym-bol representation for major units of buffered amplifier namely differentialamplifier, current mirror is done and the behaviour of each unit is verified



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by transient, DC and AC analysis. The layout is designed and checked byrunning DRC and LVS using cadence virtuoso layout simulator.

1.6 Organization of the report

1. Chapter 1 - Deals with the project definition, objective and specifica-tions of the project.

2. Chapter 2 - Deals with the Literature Survey .

3. Chapter 3 - This chapter deals with working of Differential Amplifier.4. Chapter4 - Deals with Result Analysis



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Chapter 2

Literature Survey

The differential amplifier is an important stage of a very large area of appli-cations, including high-performances analog/mixed ICs, such as operationalamplifiers, voltage comparators, voltage regulators, video amplifiers, modu-lators and demodulators or A/D and D/A converters. The linearity of theclassical CMOS differential amplifier is relatively poor because of the funda-mental nonlinear characteristic of MOS transistors, resulting the possibilityof achieving a relatively good linearity only for a restricted input voltagerange (the amplitude of the input voltage for the classic differential amplifier

using MOS transistors in saturation have to be below a few hundreds of mV).

2.1 Simple Differential Amplifier

In a differential amplifier the output signal generally is the amplified versionof the difference of two inputs of the amplifier. Because of the exclusive prop-erties of this type of amplifier, it is considered as one of the most importantbuilding blocks in many analog circuits. The fig 2.1 shows the single endedoutput differential amplifier.the small signal ,low frequency gain of both cir-cuits is equal togmN(rON||rOP).The bandwidth is usualyy determined by theload capapcitance CL

2.2 Telescopic cascode op amps

In order to achieve high gain ,the differential cascade topologies can beused.such circuits displays a gain on the order ofgmN[(gmNr

2ON||(gmPr2OP)],but

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Figure 2.1: Differential Amplifier

at the cost of output swing and additional poles these configuration are calledtelescopic cascade op amps. (a): The circuit providing a single-ended outputsuffers from a mirror pole at node X, creating stability issues. (b): Fullydifferential topology, the output swing is given by 2[VDD (VOD1 + VOD3

+ VCSS + VOD5 + VOD7)] where V ODj denotes the overdrivevoltage ofMjAnother drawback of telescopic cascodes is the difficult in short-ing their inputs and outputs, e.g., to implement a unity-gain buffer. Cas-code op amp with input and output shorted unit gain feedback topology asshown in fig2.2 Output swing: M2 and M4 in saturationVout= Vb+VTH4. Since Vx


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Figure 2.2: Telescopic cascode op amps

Figure 2.3: cascode op amp with input and output shorted



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Chapter 3

Design of Differential Amplifier

In this chapter we present the method for designing the differential ampli-fier using small signal model analysis.We have designed a CMOS differentialamplifier with active load single-ended output for the specifications men-tioned in Table1.We have used UMC 180nm CMOS Technologyin which weselected the modelN33MM andP33MMfor NMOS and PMOS respectively,for simulation in Cadence Spectre tool.

3.1 differential AmplifierA single-ended output differential amplifier can be implemented by puttinga PMOS current mirror on top of the circuit as illustrated in Figure 3.1. Inthis circuit, (M1, M2) and also (M3, M4) are mutually identical with eachother and thus the tail current I0 is equally divided between M1 (M3) and M2(M4) in the absence of differential input voltage. In this situation because ofthe circuit symmetry, the dc voltage level at the drain of M1 and M2 is thesame and equals to whereP = c0x (W/L)pP is th ehole charge carrier

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3.2 Large signal analysis of differential am-plifier

Figure 3.1: Single-ended output differential amplifier in dc state

When an ac differential input voltage is superimposed on the bias commonmode voltage the drain current in M1 and M2 will change around its static

value ofI0/2 in the opposite direction. In the differential amplifier shownin Figure 3.2 for variation ofvi in the range of

2I0/ < vi < +

2I0/

When vi rises rises, due to the positive voltage gain of the amplifier, theoutput voltage with a steep positive slope goes up and M4 quickly approachesthe triode region where the voltage gain starts dropping. This occurs for arather low positive change in vi .After M4 enters the triode region, with moreincrease in vi the output voltage v0 continues to rise with a lower rate. Atthe same time the tail current steers toward M1 and the current of M2 andM4 approaches zero. When differential input voltage reaches the entire tailcurrent flows through M1 and thus M2 turns off. At this point, M4 is intriode with zero drain current, which means the drain-source voltage of M4is zero and thus the output voltage is fixed on VDD. When input voltagechanges in the negative direction, the output voltage rapidly drops again dueto the differential amplifier voltage gain and this time M2 goes to the trioderegion. As long as the tail transistor operates in saturation, M5 acts as acurrent source, and M3 with a diode connection structure always remains insaturation. On the other hand, if the source-to-drain voltage of M4 is more



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Figure 3.3: Variations of differential amplifier drain currents versus input

transistors and biasing transistors should be in linear region.The elow fig 3.4shows the 5 pack differential amplifier

Figure 3.4: 5 pack differential amplifier

3.3 Small Signal Model

The transistor sizes for this design have been calculated through the analysisof the small signal model of the circuit shown in Fig3.4.1In the differential



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amplifier the design parameters are the W/L values of M1 through M5 andthe current in M5,I5(Vbiasis an external voltage that defines I5 and generallyis replaced by the input of a current mirrors)the starting point of design consists of two types of information. One is thedesign constraint such as the poer supply,the technology and the tempera-ture. The other type of information is the specifications.The specificationsfor the differential amplifier is shown in table3.1.Small signal gain,Av2.Frequency response for a given load capacitance

3dB

3.Input Common Mode Voltage range

4.Slew rate for a given load capacitance ,SRthe design is implemented with the relationships that describe the specifica-tions and the use of these relationships to solve for the dc currents and W?Lvalues of all transistors.Av=gm1*Rout(1)from the above eqn (1) we get the (W/L)1,2 value

3dB=1/(Rout CL) (2)

the eqn920 gives the first pole location of the diff amp

V ic(max) =V dd

V gs3 + V tn1 (3)

from eqn(3)we get the (W/L)3,4 value

V ic(min) =V ds5(sat) + V gs1 =V ds5(sat) + V gs2 (4)we get the ratio of current mirrors (W/L)5 Specification

3.4 Frequency Response of Fifferential Am-

plifier

The study of the behavior of both differential and common-mode voltage

gains (Acm and Acm) of a differential amplifier in the frequency domain isimportant. Indeed, the first shows how fast the amplifier is able to followthe rapid changes in the input differential signal and the second providesa figure of merit for the amplifier about its capability to attenuate high-frequency disturbance signals that appear at the input as common-modenoise. To simplify the frequency analysis we consider only two main inter-



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Table 3.1: Specification

nal capacitances of the circuit that form two largest time constants at theircorresponding nodes. Figure 3.11 shows a differential amplifier where Carepresents the gate capacitance of the current mirror load and Cb is thetotal capacitance including the load capacitance at the output node. Theequivalent resistance seen at node A is rather small 1/gm3 but its parasiticcapacitance Ca that mainly consists of the gate-source capacitance of M3

and M4 could be considerable in such a way that its corresponding timeconstant is noticeable. The high resistance at the output and the equivalentcapacitance at this node create the dominant time constant of the circuitat this node. The highfrequency small-signal equivalent circuit of Figure3.11 is depicted in Figure 3.12 in which we have ignored the body effectin M1 and M2 and also neglected the output resistance of the tail current.It is also assumed that two pairs of (M1, M2) and (M3, M4) are mutu-ally symmetrical. The transconductance and output resistance for NMOSdevices are denoted by gmN and roN respectively, and those of PMOS de-vices by gmP and roP. Before writing the required equations to obtain thecircuit transfer function, first we replace the indicated lower-part of the cir-cuit with its Thevenin equivalent circuit. This can be done by replacing thetwo voltage-controlled current sources by their Thevenin equivalent circuitsas illustrated in Figure 3.13. The equivalent Thevenin voltage and resis-tance are Vt=gMnroN(V1V2)=gMnroNV i and Rt=2roN , respectively.Byreplacing the lower-part circuit in Figure 3.12 with the Thevenin equiva-



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lent circuit, we get a simplified form of the small-signal equivalent circuitshown in Figure 3.14 whereZA=1/(gmp+ sCA) andZB=rop/(roP sCB) arethe impedances obtained from the parallel combination ofCA with 1/(gmp

Figure 3.5: Differential amplifier with two main capacitances impacting onfrequency response

Figure 3.6: High-frequency small-signal equivalent circuit for differential am-plifier.

and that of CA with roP, respectively. the voltgae gain for for the differ-ential amplifier is AV s=Avo(1 +s/wz)/(1 +s/wp1)(1 +s/wp2)) where



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Avo = (2gmNgmProNroP)/(1 + 2gmP(roN+ roP))where wp1 is the dominant pole of the circuit and is given by

wp1 = 1/(roN||roP)CbThe nondominant pole is created by the current mirror circuit, hence knownas the mirror pole



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Chapter 4

Simulation and Results

4.1 EVALUATION OF DEVICE

The below table shows the evaluation of the device, which helps in the properselection of the device. since inumc180nmtechnology there are two types ofdevices one is thep33mm and n33mm and p18mm and n18mm. in this paperwe using then33mmand p33mmdevice for the simulation which provides thehigh gain and ugbFor L=2u,W=18u,Idc=20uA

Table 4.1: Evaluation of NMOS Device

// // //

The W/L ratios of the different devices

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Table 4.2: Evaluation of PMOS Device

Table 4.3: Device Sizes

4.2 PVT Analysis

In the below table the PVT Analysis is done for the different devices

for VDD=1.8V

Table 4.4: PVT Analysis for 1.8V

for VDD=1.62V



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for VDD=1.92V


4.3 Schematic of Differential Amplifier

The below figurs shows the schematic of Differential amplifier AC Responsefor the open loop gain and also show the first loop location of the diff ampThe below figures show the Amplifier in the Buffer Configuration

4.4 Summary

Simulation results obtained using Cadence Spectre tool shown in below table



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Figure 4.2: AC response



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Figure 4.3: Amplifier in the Buffer Configuration



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Chapter 5

Conclusion

5.1 Conclusion

In this paper a high performance CMOS differential amplifier with active loadand single-ended outputcircuit is designed and characterized. The design iscarried out using UMC 180technology in Cadence Spectretool. The modelsused are N33MMand P33MMfor the NMOS and PMOS transistorsrespectively. We have achieved better results than the target values set forthe design. The obtained results are summarized in Table 4.

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Bibliography

[1] Han Shuguang Chi Baoyong,Wang Zhihua A Novel Off

set2Cancellation Technique for Low Voltage CMOS DifferentialAmplifiers Chines journal of semiconductors, Vol. 27, No. 5, pp.778-782, 2006.

[2] A.D. Grasso,S. Pennisi, High-Performance CMOS Pseudo-DifferentialAmplifierCircuits and Systems, ISCAS 2005. IEEE InternationalSym-posium on, pp. 1569 1572, 23-26 May 2005.

[3] B.J. Hosticka, Improvement of the Gain of CMOS Amplifiers IEEEJournal of Solid-State Circuits, vol. SC-14, Issue 6, Dec.1979, pp.1111-1114. 1996.

[4] Behzad Razavi Design of analog cmos integrated circuits McGraw-Hill, 2001.

[5] Phillip E. Allen and Douglas R. Holberg CMOS analog circuit DesignMcGraw-Hill, 2001.

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