princess sumaya univ. computer engineering dept. chapter 3: it students

Princess Sumaya Univ.Computer Engineering Dept.

Chapter 3:Chapter 3:

IT StudentsIT Students

Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.

22 / 41 / 41

Signed Number RepresentationsSigned Number Representations

Sign-Magnitude

Example:

+ 5 =

– 5 =

Range:

2’s Complement

Example:

+ 5 =

– 5 =

S Magnitude

–7 ≤ N ≤ +7 –(2n –1 –1) ≤ N ≤ +(2n –1 –1)

0 Magnitude 1 2’s Complement



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Signed Number RepresentationsSigned Number Representations

2’s Complement

Range:

Exercise:

Calculate the range for 8 bits

–(2n –1) ≤ N ≤ +(2n –1 –1)

8 C

omb

inat

ion

s8

Com

bin

atio

ns



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Used to represent integers, both positive & negative

Distinguish:

“2’s Comp. System” from “2’s Comp. Operation”

Example:

Represent the number +5 in 2’s Comp. System

Correct: Incorrect:

+5 = ( )2

+5 = ( )2

( )2

2’s Complement System2’s Complement System



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2’s Complement System2’s Complement System

Example:

Given a number represented in 2’s comp. system, write an algorithm to square it.

Answer

1)

2)

3)



66 / 41 / 41

Bit-by-bit addition, with carry propagation.

Unsigned Binary Operands:

● Produces unsigned binary

● Possible overflow (Cy = 1)

Signed 2’s Comp. Operands:

● Produces 2’s complement

● Possible overflow

Cy Cy-1

+ .

AdditionAddition

+ .

+ .



77 / 41 / 41

– .

.+ .

SubtractionSubtraction

2’s Complement Addition

Unsigned Binary Operands:

● If Cy = 1, result is unsigned binary

● If Cy = 0, result is negative (2’s comp)

● No overflow


● Produces 2’s complement

● Possible overflow

Cy Cy-1

– .

.+ .



88 / 41 / 41

× .

+ .+ . .+ . . .

MultiplicationMultiplication

Bit-by-bit Multiplication

Unsigned Binary Operands

● Unsigned result

● 2n-bit result from n × n bits operands

● No overflow

● Partial Sum0 1 1 0

× 0 1 0 10 1 1 0

0 0 0 0 .0 1 1 0 . .

0 0 0 0 . . .

Partial Sum0 0 0 0 0 0 0 0+

=



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Sequential MultiplicationSequential Multiplication

0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0

Multiplicand

Product

Multiplier

0 1 0 11 1 1 1

× 0 1 0 11 1 1 1

0 0 0 0 .0 1 1 0 . .

0 0 0 0 . . .

Control Unit

ALU



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0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0

Multiplicand

Product

Multiplier

Control Unit

0 1 0 1

Add

Load

1

1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . . ALU



1111 / 41 / 41


0 0 0 0 1 1 1 1

0 0 0 0 1 1 1 1

Multiplicand

Product

Multiplier

0 1 0 1

Control Unit

Shift Left

Shift Right

1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . . ALU



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0 0 0 1 1 1 1 0

0 0 0 0 1 1 1 1

Multiplicand

Product

Multiplier1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . .

0

Shift Left

Shift Right0 0 1 0

Control Unit

ALU



1313 / 41 / 41


0 0 1 1 1 1 0 0

0 0 0 0 1 1 1 1

Multiplicand

Product

Multiplier1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . .

Add

Load

1

0 0 0 1Shift Left

Shift Right

Control Unit

ALU



1414 / 41 / 41


0 1 1 1 1 0 0 0

0 1 0 0 1 0 1 1

Multiplicand

Product

Multiplier1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . .

0

0 0 0 0Shift Left

Shift Right

Control Unit

ALU



1515 / 41 / 41


1 1 1 1 0 0 0 0

0 1 0 0 1 0 1 1

Multiplicand

Product

Multiplier1 1 1 1× 0 1 0 1

1 1 1 10 0 0 0 .

1 1 1 1 . .0 0 0 0 . . .1 0 0 1 0 1 1

0 0 0 0

Control Unit

Delay: Number of Clocks = . . . . Clocks

ALU



1616 / 41 / 41


0 0 0 0 M M M M

0 0 0 0 0 0 0 0

Multiplicand

Product

Multiplier


Control Unit

m m m m

ALU

Clock



1717 / 41 / 41


0 0 0 M M M M 0

0 0 0 0 p p p p

Multiplicand

Product

Multiplier


Control Unit

0 m m m

ALU

Clock



1818 / 41 / 41


0 0 M M M M 0 0

0 0 p p p p p p

Multiplicand

Product

Multiplier


Control Unit

0 0 m m

ALU

Clock



1919 / 41 / 41


0 M M M M 0 0 0

0 p p p p p p p

Multiplicand

Product

Multiplier


Control Unit

0 0 0 m

ALU

Clock



2020 / 41 / 41


M M M M 0 0 0 0

p p p p p p p p

Multiplicand

Product

Multiplier


Control Unit

0 0 0 0

ALU

Clock



2121 / 41 / 41

Signed MultiplicationSigned Multiplication


● Convert negative operands to positive values

● Perform unsigned multiplication

● Negate the result if the two operands differ in sign



2222 / 41 / 41

DivisionDivision

Subtract Divisor & Drop a Bit

Unsigned Binary Operands

● Unsigned result

● 2n-bit Dividend by n-bit divisor

n-bit quotient and n-bit remainder

● Possible overflow (big quotient)

♦ Divide by zero

♦ Quotient ≥ 2n

. .. │ 0

0 0

0 0

0 0

0

0



2323 / 41 / 41

Sequential DivisionSequential Division

0 1 1 0 0 0 0 0

0 1 0 1 0 0 1 0

Divisor

Remainder

(Dividend)

Quotient

0 0 0 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0



2424 / 41 / 41


0 1 1 0 0 0 0 0

0 1 0 1 0 0 1 0

Divisor

Remainder

(Dividend)

Quotient

0 0 0 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Subtract

Load



2525 / 41 / 41


0 1 1 0 0 0 0 0

1 1 1 1 0 0 1 0

Divisor

Remainder

Quotient

0 0 0 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Add

Load

Shift Left

0

Shift Right



2626 / 41 / 41


0 0 1 1 0 0 0 0

0 1 0 1 0 0 1 0

Divisor

Remainder

Quotient

0 0 0 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Subtract

Load



2727 / 41 / 41


0 0 1 1 0 0 0 0

0 0 1 0 0 0 1 0

Divisor

Remainder

Quotient

0 0 0 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Shift Left

1

Shift Right



2828 / 41 / 41


0 0 0 1 1 0 0 0

0 0 1 0 0 0 1 0

Divisor

Remainder

Quotient

0 0 0 1

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Subtract

Load



2929 / 41 / 41


0 0 0 1 1 0 0 0

0 0 0 0 1 0 1 0

Divisor

Remainder

Quotient

0 0 0 1

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Shift Left

1

Shift Right



3030 / 41 / 41


0 0 0 0 1 1 0 0

0 0 0 0 1 0 1 0

Divisor

Remainder

Quotient

0 0 1 1

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Subtract

Load



3131 / 41 / 41


0 0 0 0 1 1 0 0

1 1 1 1 1 1 1 0

Divisor

Remainder

Quotient

0 0 1 1

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

0 1 0 1 0– 0 1 1 0

0 1 0 0

Add

Load

Shift Left

0

Shift Right



3232 / 41 / 41


0 0 0 0 0 1 1 0

0 0 0 0 1 0 1 0

Divisor

Remainder

Quotient

0 1 1 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0– 0 1 1 0

0 1 0 0

Subtract

Load



3333 / 41 / 41


0 0 0 0 0 1 1 0

0 0 0 0 0 1 0 0

Divisor

Remainder

Quotient

0 1 1 0

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0– 0 1 1 0

0 1 0 0

Shift Left

1

Shift Right



3434 / 41 / 41


0 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0

Divisor

Remainder

Quotient

1 1 0 1

Control Unit

ALU

. 0 1 1 0 10 1 1 0│0 1 0 1 0 0 1 0

– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0 0– 0 1 1 0 0

0 1 0 0 0 0– 0 1 1 0 0

0 0 1 0 1 0– 0 1 1 0 0+ 0 1 1 0 0

1 0 1 0– 0 1 1 0

0 1 0 0

How many times was the Divisor & Quotient shifted?How many clocks?



3535 / 41 / 41

Signed DivisionSigned Division


● Convert negative operands to positive values

● Perform unsigned division

● Negate the result (?) if the two operands differ in sign

♦ Which result? Quotient or remainder or both?

● Dividend = Quotient × Divisor + Remainder

♦ Example: 16 ÷ 3

● Rule: Dividend & Remainder must have the same sign



3636 / 41 / 41

Floating PointFloating Point

Scientific Notation

Example: (10.5 × 10 – 7 is not good)

Normalized Scientific Notation


Binary Numbers


(Normalized)

. × 10

. × 2



3737 / 41 / 41

Floating PointFloating Point

Sign & Magnitude

Overflow: The exponent is too large to be represented

Underflow: The exponent is too small to be represented

Single & Double Precision

. × 2±

S Exponent Fraction32 bits

±

?



3838 / 41 / 41

IEEE 754 Floating Point StandardIEEE 754 Floating Point Standard

Single Precision:

Biased Exponent

S Exponent Fraction

32 bits

1bit

8bits

23bits

255

0

256

• •

= 0111 1111 (biased by 127)

• •

• • •

0

+

–



3939 / 41 / 41


Implicit ‘1’

1.01 × 2 0

Examples:

75 =

– 0.75 =

0.0 = ?

S Exponent Fraction

This bit is always 1No need to store it, hence implicit

( ) 2

0 1000 0101 0 0 1 0 1 1 0 • • • • 0

– ( ) 2

1 0111 1110 1 0 0 0 • • • • • • • 0



4040 / 41 / 41


Reserved Bit Patterns

● Zero:

● ± Infinity:

● Others like denormalized number and Not-a-Number

0 0000 0000 0 0 0 0 • • • • • • • 0

1111 1111 0 0 0 0 • • • • • • • 0



4141 / 41 / 41

Floating-Point Addition / SubtractionFloating-Point Addition / Subtraction

Need to Align Decimal Points

Example:

Add 0.5 + 0.4375

Normalized Forms:

Align Decimal Point:

Perform Addition:Normalize Result:

0.5 = ( ) 2 =

0.4375 = ( ) 2 =

0 0

× 2 –1

× 2 –1

× 2 –1

× 2 –1

0 0111 1110 0 0 0 • • • 0 0 0111 1101 1 1 0 • • • 0

0 0111 1110 1. 0 0 0 • • 0 0 0111 1101 1. 1 1 0 • • 0 0 0111 1110 0. 1 1 1 • • 0 0 0111 1110 1. 1 1 1 • • 0 0 0111 1110 1 1 1 • • • 0



4242 / 41 / 41

Floating-Point MultiplicationFloating-Point Multiplication

Need to Account for Biased Exponents

Example:

Multiply 0.5 × 0.4375

Normalized Forms:

Multiply Fractions:

Add Exponents:Sub Extra Bias:

Round & Normalize:

0.5 = ( ) 2 =

0.4375 = ( ) 2 =

0 0111 1110 0 0 0 • • • 0 0 0111 1101 1 1 0 • • • 0

× .

0 0111 1110 1. 0 0 0 • • 0 0 0111 1101 1. 1 1 0 • • 0 0 0111 1101 1. 1 1 0 • • 0

+ – . 0 0111 1100 1 1 0 • • •

0IT StudentsIT Students

Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.Chapter 3Chapter 3

Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.Chapter 3 Exercise 1Chapter 3 Exercise 1

Determine the magnitude of (10001000)2 in:a) sign-magnitude and b) 2’s complement system

Determine if there was an overflow error in: unsigned int a, b; // Assume 8-bit registers a= (10001000) 2 ; b = a + a;

Show how the CPU computes b: int a, b; // Assume 8-bit registers a= (10001000) 2 ; b = a – a;

How many addition are done in (1001)2.IT StudentsIT Students

princess sumaya univ. computer engineering dept. chapter 3: it students

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